Gotowe bibliografie tematyczne / CMOS VOLTAGE

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Gotowa bibliografia na temat „CMOS VOLTAGE”

Autor: Grafiati

Data publikacji: 11 września 2023

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Artykuły w czasopismach na temat "CMOS VOLTAGE"

Dai, Y., D. T. Comer, D. J. Comer i C. S. Petrie. "Threshold voltage based CMOS voltage reference". IEE Proceedings - Circuits, Devices and Systems 151, nr 1 (2004): 58. http://dx.doi.org/10.1049/ip-cds:20040217.

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Fouad, Hafez, Hesham Kamel i Adel Youssef. "High Precision Low Input Voltage of 65nm CMOS Rectifier for Energy Harvesting using Threshold Voltage Minimization in Telemedicine Embedded System". International Journal of Circuits, Systems and Signal Processing 16 (7.10.2022): 1135–47. http://dx.doi.org/10.46300/9106.2022.16.137.

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Telemedicine applications run at very low input voltages, necessitating the use of Great Precision Rectifier with high sensitivity to function at low input voltages. In this study, we used a 65 nm CMOS rectifier to achieve a 0.2V input voltage for Energy Harvesting Telemedicine application. The suggested rectifier, which has two-stage structure and operates at frequency of 2.4GHz, has been found to perform better in cases where the minimum operating voltage is lower than previously published papers, and the rectifier can operate over a wide range of low input voltage amplitudes. Full-Wave Fully gate cross-coupled Rectifiers (FWFR) CMOS Rectifier Efficiency at Freq of 2.4 GHz: With an input voltage amplitude of 2V, the minimum and maximum output voltages are 0.49V and 1.997V, respectively, with a peak VCE of 99.85 percent and a peak PCE of 46.86 percent. This enables the suggested rectifier to be used in a variety of vibration energy collecting systems, including electrostatic, electromagnetic, and piezoelectric energy harvesters. The proposed rectifier, which is built at 2.4GHz and has a two-stage structure, performs better in the event of low input voltage amplitude and has lower minimum operation voltage than previously published papers. Full-wave fully gate cross-coupled rectifiers (FWFR) CMOS Rectifier Performance Summary at Freq of 2.4 GHz: With a 2V input voltage amplitude, the minimum and maximum output voltages are 0.49V and 1.997V, respectively, with a maximum VCE of 99.85% and a maximum PCE of 46.86%.

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Fouad, Hafez, i Hesham Kamel. "Threshold Voltage Cancellation For Low Input Voltage of 65nm CMOS Rectifier of Energy Harvesting For Implantable Medical Devices in Telemedicine Embedded System". International Journal of Mathematics and Computers in Simulation 16 (27.10.2022): 103–14. http://dx.doi.org/10.46300/9102.2022.16.16.

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Telemedicine applications run at very low voltages, necessitating the use of a Great Precision Rectifier with high sensitivity to function at low input voltages. In this study, we used a 65 nm CMOS rectifier to achieve a 0.2V input voltage for Energy Harvesting Telemedicine application. The suggested rectifier, which has two-stage structure and operates at frequency of 2.4GHz, has been found to perform better in cases where the minimum operating voltage is lower than previously published papers, and the rectifier can operate over a wide range of low input voltage amplitudes. Full-Wave Fully gate cross-coupled Rectifiers (FWFR) CMOS Rectifier Efficiency at Freq of 2.4 GHz: With an input voltage amplitude of 2V, the minimum and maximum output voltages are 0.49V and 1.997V, respectively, with a peak VCE of 99.85 percent and a peak PCE of 46.86 percent. This enables the suggested rectifier to be used in a variety of vibration energy collecting systems, including electrostatic, electromagnetic, and piezoelectric energy harvesters. The proposed rectifier, which is built at 2.4GHz and has a two-stage structure, performs better in the event of low input voltage amplitude and has a lower minimum operation voltage than previously published papers. Full-wave fully gate cross-coupled rectifiers (FWFR) CMOS Rectifier Performance Summary at Freq of 2.4 GHz: With a 2V input voltage amplitude, the minimum and maximum output voltages are 0.49V and 1.997V, respectively, with a maximum VCE of 99.85% and a maximum PCE of 46.86%.

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Ehrler, F., R. Blanco, R. Leys i I. Perić. "High-voltage CMOS detectors". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 824 (lipiec 2016): 400–401. http://dx.doi.org/10.1016/j.nima.2015.09.004.

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Marzaki, Abderrezak, V. Bidal, R. Laffont, W. Rahajandraibe, J.-M. Portal i R. Bouchakour. "New Schmitt Trigger with Controllable Hysteresis using Dual Control Gate-Floating Gate Transistor (DCG-FGT)". International Journal of Reconfigurable and Embedded Systems (IJRES) 2, nr 1 (1.03.2013): 49. http://dx.doi.org/10.11591/ijres.v2.i1.pp49-54.

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This paper presents different low voltage adjustable CMOS Schmitt trigger using DCG-FGT transistor. Simple circuits are introduced to provide flexibility to program the hysteresic threshold in this paper. The hysteresis can be controlled accurately at a large voltage range. The proposed Schmitt trigger have been designed using 90nm 1.2V CMOS technology and simulated using Eldo with PSP device models. The simulation results show rail-to-rail operation and adjustable switching voltages VTH- (low switching voltage) and VTH+ (high switching voltage).

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BISDOUNIS, LABROS. "ANALYTICAL MODELING OF OVERSHOOTING EFFECT IN SUB-100 nm CMOS INVERTERS". Journal of Circuits, Systems and Computers 20, nr 07 (listopad 2011): 1303–21. http://dx.doi.org/10.1142/s0218126611007967.

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Modeling of CMOS inverters and consequently, CMOS gates, is a critical task for improving accuracy and speed of simulation in modern sub-100 nm digital circuits. One of the key factors that determine the operation of a CMOS structure is the influence of the input-to-output coupling capacitance, also called overshooting effect. In this paper, an analytical model for this effect is presented, that computes the time period which is necessary to eliminate the extra output charge transferred through the input-to-output capacitance at the beginning of the switching process in a CMOS inverter. In addition, the maximum or minimum output voltage (depending on the considered edge) is analytically computed. The derived model is based on analytical expressions of the CMOS inverter output voltage waveform, which include the influences of both transistor currents and the input-to-output (gate-to-drain) coupling and load capacitances. An accurate version of the alpha-power law MOSFET model is used to relate the terminal voltages to the drain current in sub-100 nm devices, with an extension for varying transistor widths. The resulting model also accounts for the influences of input voltage transition time, transistors' sizes, as well as device carrier velocity saturation and narrow-width effects. The results produced by the presented model for three sub-100 nm CMOS technologies, several input voltage transition times, capacitive loads and device sizes, show very good agreement with BSIM4 HSPICE simulations.

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Hu, Jian Ping, i Jia Guo Zhu. "Voltage Scaling for SRAM in 45nm CMOS Process". Applied Mechanics and Materials 39 (listopad 2010): 253–59. http://dx.doi.org/10.4028/www.scientific.net/amm.39.253.

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Scaling supply voltage is an efficient approach to achieve low energy. Scaling supply voltage to sub-threshold region can reach minimum energy consumption but only suits for ultra-low operation frequencies. In order to attain more extensive application, scaling supply voltage to medium-voltage region is an attractive approach especially suiting for mid performances. This paper investigates performances of conventional SRAMs in near-threshold and super-threshold regions in terms of energy dissipation and max operating frequency. All circuits are simulated with HSPICE at PTM 45nm CMOS technology by varying supply voltages from 0.4V to 1.1V with 0.1V steps. The simulation results demonstrate that the conventional SRAMs operate on medium-voltage region can not only keep reasonable speed but also reduce greatly energy consumptions.

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AL-Qaysi, Hayder Khaleel, Musaab Mohammed Jasim i Siraj Manhal Hameed. "Design of very low-voltages and high-performance CMOS gate-driven operational amplifier". Indonesian Journal of Electrical Engineering and Computer Science 20, nr 2 (1.11.2020): 670. http://dx.doi.org/10.11591/ijeecs.v20.i2.pp670-679.

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This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.

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Meyer, Joseph, Reza Moghimi i Noah Sturcken. "Package Voltage Regulators: The Answer for Power Management Challenges". International Symposium on Microelectronics 2019, nr 1 (1.10.2019): 000438–43. http://dx.doi.org/10.4071/2380-4505-2019.1.000438.

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Abstract The generational scaling of CMOS device geometries, as predicted by Moore's law, has significantly outpaced advances in CMOS package and power electronics technology. The conduction of power to a high-performance integrated circuit (IC) die typically requires close to 50% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur in advanced CMOS nodes. The disparity in scaling of logic, package, and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. By performing power conversion and voltage regulation in-package, this limitation can be mitigated. Integration of thin-film ferromagnetic inductors with CMOS technology enables single-chip power converters to be co-packaged with processors, high bandwidth memory (HBM), and/or other modules. This paper highlights the advantages of fully integrated package voltage regulators (PVRs), which include: reducing package I/O allocated for power, eliminating the need for upstream power-conversion stages, and improving transient response. These benefits substantially reduce the size, weight, and power of modern electronic systems.

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Wang, San-Fu. "A 5 V-to-3.3 V CMOS Linear Regulator with Three-Output Temperature-Independent Reference Voltages". Journal of Sensors 2016 (2016): 1–7. http://dx.doi.org/10.1155/2016/1436371.

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This paper presents a 5 V-to-3.3 V linear regulator circuit, which uses 3.3 V CMOS transistors to replace the 5 V CMOS transistors. Thus, the complexity of the manufacturing semiconductor process can be improved. The proposed linear regulator is implemented by cascode architecture, which requires three different reference voltages as the bias voltages of its circuit. Thus, the three-output temperature-independent reference voltage circuit is proposed, which provides three accurate reference voltages simultaneously. The three-output temperature-independent reference voltages also can be used in other circuits of the chip. By using the proposed temperature-independent reference voltages, the proposed linear regulator can provide an accurate output voltage, and it is suitable for low cost, small size, and highly integrated system-on-chip (SoC) applications. Moreover, the proposed linear regulator uses the cascode technique, which improves both the gain performance and the isolation performance. Therefore, the proposed linear regulator has a good performance in reference voltage to output voltage isolation. The voltage variation of the linear regulator is less than 2.153% in the temperature range of −40°C–120°C, and the power supply rejection ratio (PSRR) is less than −42.8 dB at 60 Hz. The regulator can support 0~200 mA output current. The core area is less than 0.16 mm2.

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Rozprawy doktorskie na temat "CMOS VOLTAGE"

Duncan, Martin Russell. "CMOS-compatible high-voltage transistors". Thesis, University of Edinburgh, 1994. http://hdl.handle.net/1842/12182.

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Bipolar transistors are known to be the most suitable for high-voltage and power applications, due to their inherently greater current handling capability. In contrast, MOS technology is preferable for logic applications, due to its superior packing density. Therefore the 'ideal' solution to the smart power problem of integrating control elements on the same die as power switches is a marriage of the two different technologies. This results in a complex process that can only be cost effective in high volume applications. For ASIC applications and low volume product runs a less expensive compromise solution is needed. By analyzing both bipolar and MOS, low and high voltage devices, it was found that if more than one power transistor is needed on the circuit, and a single technology is to be used, then MOS power transistors are inherently easier to integrate into a low voltage process. In particular the lateral double-diffused transistor (LDMOS) with all terminal contacts on the surface is to be preferred. Analyzing a CMOS process, common processing steps were found for both the low and high-voltage devices, leading to a smart power solution that doesn't need many masking levels. By making small changes to an established n-well CMOS process, and developing a novel power transistor structure with a field oxidation separating the channel and drain, a 120 Volt n-channel power transistor could be realised within a conventional process with no additional processing steps. By adding one further masking layer, a complementary p-channel power transistor that supported -55 Volts could be fabricated. If these transistors were fabricated on a p- epitaxial layer on an n- substrate then by changing the p-channel power device structure, a breakdown voltage of -95 Volt could be achieved using only nine masking layers.

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Ng, Wing Lun. "Low-voltage high-frequency CMOS transformer-feedback voltage-controlled oscillators /". View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20NG.

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Holman, William Timothy. "A low noise CMOS voltage reference". Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/14968.

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Shabra, Ayman U. (Ayman Umar). "Ultra-low voltage CMOS operational amplifiers". Thesis, Massachusetts Institute of Technology, 1997. http://hdl.handle.net/1721.1/29876.

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Colombo, Dalton Martini. "Bandgap voltage references in submicrometer CMOS technology". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/16136.

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Referências de tensão são blocos fundamentais em uma série de aplicações de sinais mistos e de rádio frequência, como por exemplo, conversores de dados, PLL's e conversores de potência. A implementação CMOS mais usada para referências de tensão é o circuito Bandgap devido sua alta previbilidade, e baixa dependência em relação à temperatura e tensão de alimentação. Este trabalho estuda aplicação de Referência de Tensão Bandgap. O princípio, as topologias tradicionalmente usadas para implementar este método e as limitações que essas arquiteturas sofrem são investigadas. Será também apresentada uma pesquisa das questões recentes envolvendo alta precisão, operação com baixa tensão de alimentação e baixa potência, e ruído de saída para as referências Bandgap fabricadas em tecnologias submicrométricas. Além disso, uma investigação abrangente do impacto causado pelo o processo da fabricação e do ruído no desempenho da referência é apresentada. Será mostrado que o ruído de saída pode limitar a precisão dos circuitos Bandgap e seus circuitos de ajuste. Para desenvolver nosso trabalho, três Referências Bandgap foram projetadas utilizando o processo IBM 7RF 0.18 micra com uma tensão de alimentação de 1.8V. Também foram projetados os leiautes desses circuitos para prover informações pósleiaute extraídos e resultados de simulação elétrica. Este trabalho provê uma discussão de algumas topologias e das práticas de projeto para referências Bandgap.
A Voltage Reference is a pivotal block in several mixed-signal and radio-frequency applications, for instance, data converters, PLL's and power converters. The most used CMOS implementation for voltage references is the Bandgap circuit due to its highpredictability, and low dependence of the supply voltage and temperature of operation. This work studies the Bandgap Voltage References (BGR). The most relevant and the traditional topologies usually employed to implement Bandgap Voltage References are investigated, and the limitations of these architectures are discussed. A survey is also presented, discussing the most relevant issues and performance metrics for BGR, including, high-accuracy, low-voltage and low-power operation, as well as the output noise of Bandgap References fabricated in submicrometer technologies. Moreover, a comprehensive investigation on the impact of fabrication process effects and noise on the reference voltage is presented. It is shown that output noise can limit the accuracy of the BGR and trim circuits. To support and develop our work, three BGR´s were designed using the IBM 0.18 Micron 7RF process with a supply voltage of 1.8 V. The layouts of these circuits were also designed to provide post-extracted layout information and electrical simulation results. This work provides a comprehensive discussion on the structure and design practices for Bandgap References.

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Kim, Hyung-Seuk 1976. "Low voltage CMOS frequency synthesizers for RF applications". Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=82607.

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Frequency synthesizers play an important role in modern communications and timing systems. The output of frequency synthesizers may be used as the local oscillator signal in superheterodyne transceivers, or in frequency modulation/demodulation. Fully integrated CMOS RF synthesizers are currently a major research topic. Several publications demonstrated improvements in a variety of aspects such as phase noise, power consumption, and tuning range. However, very low voltage frequency synthesizers are very challenging, since they usually have a limited tuning range and a relatively high phase noise. This research work demonstrates a new architecture to achieve a wide tuning range and low phase noise from a very low voltage supply. The synthesizer is fully integrated in a 0.18 mum CMOS technology covering the 5 GHz WLAN frequency range, requiring only a 1-V power supply. The second part of this thesis consists of the implementation of a 2.4-GHz fractional-N frequency synthesizer to be compatible with two MEMS resonators that resonate at 20-MHz and 70-MHz.

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Naude, Neil. "Differential current sensor linearisation in low-voltage CMOS". Diss., University of Pretoria, 2017. http://hdl.handle.net/2263/62785.

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The viability of low cost, distributed, and autonomous wireless sensor networks is determined by the affordability of the integration and operation of each sensor node. Self-sufficient nodes which harvest energy from the local environment decrease operating and maintenance costs over extended periods of time. This affordability can be achieved by increasing the power usage efficiency of designs implemented in an older and cheaper CMOS process. This circumvents the use of a more compact technology node which trades increased efficiency for cost. The efficiency of power conversion is determined by topology, component quality, control scheme, and internal measurement accuracy. This research focuses on improving internal measurement during the power conversion process, in order to reduce conversion loss from the internal control error. A current sensing integrated circuit was proposed which is insensitive to dominant process characteristics which degrade the performance of other sensing solutions. In particular, the detrimental effect of channel length modulation is compensated for. This compensation is achieved by decoupling the sensor biasing and differential steering pair from being influenced by the external current being measured. Widely used solutions were studied and analysed in the context of implementation in a low cost and low-voltage CMOS process. Key process characteristics which negatively influenced these solutions were identified and formed the basis of developing an improved integrated current sensor. Current research in the literature is tightly focused on improved accuracy without the constraints of process costs, low operating voltage (800mV – 1.2 V), and prevalent second order effects of device operation. A study of the literature on CMOS-based integrated current sensing demonstrates a common goal towards improving sensor accuracy by developing either new topologies or augmenting known topologies. New and augmented topologies focus on novel analogue networks which aim to improve the linearity of CMOS based current sensing. The colloquially named SenseFET circuit is a foundation for many variations of integrated current sensor. This integrated circuit generates an estimate of the current flowing into a DC-DC boost-buck converter by sampling the current sourced into the converters inductor. The low maximum operating voltage of the chosen CMOS process restricts the application of typical published solutions. The sensitivity of other solutions to second order effects limits application as well. The proposed solution is based on such a sampling topology with a focus on achieving linearity in a process with pronounced channel-length modulation effects as well as a relatively low operating voltage. The goal of the improved design is to test if linearity can be improved by developing a circuit which is robust towards second-order process effects. Discreet and integrated boost-buck converters were studied and analysed to form the basis of further sensor developments. An integrated non-inverting converter topology suitable for single rail operation was identified and designed as the system environment for which an integrated sensor would be developed. This would allow for comparison of sensor designs in a known environment, both in simulation and in prototyping of the integrated system. The proposed integrated current sensor was developed analytically before being simulated both mathematically and at transistor gate level. This iterative process was applied to a known design as a performance baseline and to demonstrate the improvements achieved.
Dissertation (MEng)--University of Pretoria, 2017.
Electrical, Electronic and Computer Engineering
MEng
Unrestricted

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Layton, Kent D. "Low-voltage analog CMOS architectures and design methods /". Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd2141.pdf.

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Layton, Kent Downing. "Low-Voltage Analog CMOS Architectures and Design Methods". BYU ScholarsArchive, 2007. https://scholarsarchive.byu.edu/etd/1218.

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This dissertation develops design methods and architectures which allow analog circuits to operate at VT + 2Vds,sat, the minimum supply for CMOS circuits with all transistors in the active region where Vds,sat is the drain to source saturation voltage of a MOS transistor. Techniques which meet this criteria for rail-to-rail input stages, gain enhancement stages, and output stages are discussed and developed. These techniques are used to design four fully-differential rail-to-rail amplifiers. The highest gain is shown to be attained using a drain voltage equalization (DVE) or active-bootstrapping technique which produces more than 100dB of gain in a two stage amplifier with a bulk-driven input pair while showing no bandwidth degradation when compared to amplifier architectures with similar biasing. The low voltage design techniques are extended to switching and sampling circuits. A 10-bit digital to analog converter (DAC) and a 10-bit analog to digital converter (ADC) are designed and fabricated in a 0.35um dual-well CMOS process to prove the developed design methods, architectures, and techniques. The 10-bit DAC operates at 1MSPS with near rail-to-rail differential output operation with a 700mV supply voltage. This supply voltage, which is 150mV lower than the VT+2Vds,sat limit, is attained by using a bulk driven threshold voltage lowering technique. The ADC design is a fully-differential pipelined 10-bit converter that operates at 500kSPS with a full scale input range equal to the supply voltage and can operate at supply voltages as low as 650mV, 200mV below the VT + 2Vds,sat limit. The design methods and architectures can be used in advanced processes to maintain gain and minimize supply voltage. These designs show a minimum supply improvement over previously published designs and prove the efficacy of the design architectures and techniques presented in this dissertation.

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Ballan, Hussein Declercq Michel Declercq Michel Declercq Michel. "High voltage devices and circuits in standard CMOS technologies /". Dordrecht : Kluwer Academic Publishers, 1999. http://opac.nebis.ch/cgi-bin/showAbstract.pl?u20=079238234X.

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Książki na temat "CMOS VOLTAGE"

Kok, Chi-Wah, i Wing-Shan Tam. CMOS Voltage References. Fusionopolis Walk, Singapore: John Wiley & Sons Singapore Pte. Ltd., 2012. http://dx.doi.org/10.1002/9781118275696.

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Kursun, Volkan, i Eby G. Friedman. Multi-Voltage CMOS Circuit Design. Chichester, UK: John Wiley & Sons, Ltd, 2006. http://dx.doi.org/10.1002/0470033371.

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Sakurai, Satoshi, i Mohammed Ismail. Low-Voltage CMOS Operational Amplifiers. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2267-6.

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Kursun, Volkan. Multiple-voltage CMOS circuit design. Chichester, UK: John Wiley, 2006.

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Kursun, Volkan. Multi-voltage CMOS Circuit Design. New York: John Wiley & Sons, Ltd., 2006.

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Jea-Hong, Luo, red. Low-voltage CMOS VLSI circuits. New York: Wiley, 1999.

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Motorola. LCX data: Low-voltage CMOS logic. Wyd. 2. Phoenix, AZ: Motorola, 1995.

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Semiconductors, Philips. Advanced low voltage CMOS logic: Data handbook. Eindhoven: Philips Semiconductors, 1998.

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Kursun, Volkan. Multiple supply and threshold voltage CMOS circuits. Chichester, England: John Wiley, 2006.

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Yeo, Kiat Seng. CMOS/BiCMOS ULSI: Low voltage, low power. Upper Saddle River, NJ: Prentice Hall PTR, 2002.

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Części książek na temat "CMOS VOLTAGE"

Chandrakasan, Anantha P., i Robert W. Brodersen. "Voltage Scaling Approaches". W Low Power Digital CMOS Design, 105–40. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2325-3_4.

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Maurath, Dominic, i Yiannos Manoli. "Low-Voltage CMOS Design Fundamentals". W CMOS Circuits for Electromagnetic Vibration Transducers, 73–92. Dordrecht: Springer Netherlands, 2014. http://dx.doi.org/10.1007/978-94-017-9272-1_3.

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Sakurai, Satoshi, i Mohammed Ismail. "Introduction". W Low-Voltage CMOS Operational Amplifiers, 1–4. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2267-6_1.

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Sakurai, Satoshi, i Mohammed Ismail. "Conclusion and Future Work". W Low-Voltage CMOS Operational Amplifiers, 195–99. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2267-6_10.

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Sakurai, Satoshi, i Mohammed Ismail. "Operational Amplifiers in 3-V Supply". W Low-Voltage CMOS Operational Amplifiers, 5–20. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2267-6_2.

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Sakurai, Satoshi, i Mohammed Ismail. "Constant-gm Input Stages, Kn = Kp". W Low-Voltage CMOS Operational Amplifiers, 21–29. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2267-6_3.

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Sakurai, Satoshi, i Mohammed Ismail. "Robust Bias Circuit Techniques". W Low-Voltage CMOS Operational Amplifiers, 31–43. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2267-6_4.

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Sakurai, Satoshi, i Mohammed Ismail. "Constant-gm Input Stages, Kn ≠ Kp". W Low-Voltage CMOS Operational Amplifiers, 45–70. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2267-6_5.

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Sakurai, Satoshi, i Mohammed Ismail. "Rail-to-Rail Output Stages". W Low-Voltage CMOS Operational Amplifiers, 71–86. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2267-6_6.

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Sakurai, Satoshi, i Mohammed Ismail. "Single-Stage Operational Amplifiers". W Low-Voltage CMOS Operational Amplifiers, 87–110. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2267-6_7.

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Streszczenia konferencji na temat "CMOS VOLTAGE"

Raikos, George, i Spyridon Vlassis. "Low-voltage CMOS voltage squarer". W 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009). IEEE, 2009. http://dx.doi.org/10.1109/icecs.2009.5410960.

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Haas, J., K. Au, L. C. Martin, T. L. Portlock i T. Sakurai. "High voltage CMOS LCD driver using low voltage CMOS process". W 1989 Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/cicc.1989.56755.

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Roy, Kaushik. "Ultra low voltage CMOS". W the 14th ACM/IEEE international symposium. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1594233.1594341.

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Padilla-Cantoya, Ivan, Jesus Ezequiel Molinar-Solis i Gladis O. Ducoudary. "Class AB low-voltage CMOS Voltage Follower". W 2007 Joint 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) and the IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007). IEEE, 2007. http://dx.doi.org/10.1109/mwscas.2007.4488713.

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Ohmori, K., P. Ahmet, K. Shiraishi, H. Watanabe, Y. Akasaka, K. Yamabe, M. Yoshitake i in. "Influences of annealing conditions on flatband voltage properties using continuously workfunction-tuned metal electrodes". W 2006 International Workshop on Nano CMOS (IWNC). IEEE, 2006. http://dx.doi.org/10.1109/iwnc.2006.4570988.

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Berg, Yngvar, i Omid Mirmotahari. "Low voltage precharge CMOS logic". W 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. IEEE, 2009. http://dx.doi.org/10.1109/ddecs.2009.5012115.

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Di Cataldo, Giuseppe, Alfio Dario Grasso i Salvatore Pennisi. "CMOS voltage feedback current amplifier". W 2007 European Conference on Circuit Theory and Design (ECCTD 2007). IEEE, 2007. http://dx.doi.org/10.1109/ecctd.2007.4529524.

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Berg, Yngvar, Omid Mirmotahari, Per Andreas Norseng i Snorre Aunet. "Ultra low voltage CMOS gates". W 13th IEEE International Conference on Electronics, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/icecs.2006.379914.

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Gandhi, Priyesh P., i N. M. Devashrayee. "High performance CMOS voltage comparator". W 2013 Nirma University International Conference on Engineering (NUiCONE). IEEE, 2013. http://dx.doi.org/10.1109/nuicone.2013.6780141.

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Alioto, Massimo, i David Esseni. "Comparative evaluation of Tunnel-FET ultra-low voltage SRAM bitcell and impact of variations". W 2014 5th European Workshop on CMOS Variability (VARI). IEEE, 2014. http://dx.doi.org/10.1109/vari.2014.6957083.

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