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1
Rakheja, Shaloo. "Interconnects for post-CMOS devices: physical limits and device and circuit implications". Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45866.
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The objective of this dissertation is to classify the opportunities, advantages, and limits of novel interconnects for post-CMOS logic that can augment or eventually replace the CMOS logic. Post-CMOS devices are envisaged on the idea of using state variables other than the electron charge to store and manipulate information. In the first component of the thesis, a comprehensive analysis of the performance and the energy dissipation of novel logic based on various state variables is conducted, and it is demonstrated that the interconnects will continue to be a major challenge even for post-CMOS logic.
The second component of the thesis is focused on the analysis of the interconnection aspects of spin-based logic. This research goal is accomplished through the development of physically-based models of spin-transport parameters for various metallic, semiconducting, and graphene nanoribbon interconnects by incorporating the impact of size effects for narrow cross-sectional dimensions of all-spin logic devices. Due to the generic nature of the models, they can be used in the analysis of spin-based devices to study their functionality and performance more accurately. The compact nature of the models allows them to be easily embedded into the developing CAD tools for spintronic logic. These models then provide the foundation for (i) analyzing the spin injection and transport efficiency in an all-spin logic circuit with various interconnect materials, and (ii) estimating the repeater-insertion requirements in all-spin logic, and (iii) estimating the maximum circuit size for all-spin logic. The research is crucial in pinpointing the implications of the physical limits of novel interconnects at the material, device, circuit, and architecture levels.
2
Yu, Chuanzhao. "STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY". Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3551.
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The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices – low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices – from device level to circuit level; The more real voltage stress case – high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future.Ph.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
3
Jain, Ishita. "Modeling and simulation of self-heating effects in sub-14NM CMOS devices". Thesis, IIT Delhi, 2019. http://eprint.iitd.ac.in:80//handle/2074/8137.
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Wu, Dongping. "Novel concepts for advanced CMOS : Materials, process and device architecture". Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3805.
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The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration.
High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO2and Al2O3as well as their mixtures are investigated assubstitutes for the traditionally used SiO2in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed.
A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode.
Key words:CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.
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Xu, Chen. "Low voltage CMOS digital imaging architecture with device scaling considerations /". View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20XU.
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Thesis (Ph. D.)--Hong Kong University of Science and Technology, 2004.Includes bibliographical references (leaves 131-136). Also available in electronic version. Access restricted to campus users.
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Kopalle, Deepika Niu Guofu. "RF linearity analysis in nano scale CMOS using harmonic balance device simulations". Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Fall/Thesis/KOPALLE_DEEPIKA_43.pdf.
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Odanaka, Shinji. "A STUDY OF NUMERICAL PROCESS AND DEVICE MODELING CAD FOR SUBMICROMETER CMOS". Kyoto University, 1990. http://hdl.handle.net/2433/86214.
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Wang, Haihong. "Advanced transport models development for deep submicron low power CMOS device design /". Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
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HUSSAIN, IZHAR. "TAMTAMS: A web based performance estimation tool from Device to System level for advanced CMOS processes to beyond CMOS technologies". Doctoral thesis, Politecnico di Torino, 2018. http://hdl.handle.net/11583/2710840.
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We presented here a web-based tool, named TAMTAMS that can accurately calculate the IV characteristics of a transistor based technology and estimate the performance evaluation at system level. We have shown how the modular structure of the tool, makes it possible to estimate an electrical quantity, let’s say A, and evaluate further electrical quantities depending on A in a single run of processing. The tree structure and dependence tree enables a user do analysis from a single nano-scale transistor to a system containing hundreds of thousands of transistors. TAMTAMS Web, as a tool, enables the technologist to observe the effect of changes in process parameters (such as doping Nd)at system level. In other words, the changes in device parameters like Vth, Ion, Ioff etc are reflected in changes in system level performance parameters like Static and Dynamic power consumption.
We started the development of the tool from BULK transistor technology by translating the physics based mathematical models as Octave scripts. Moving towards more complex structures like SOI, FinFET, Gate-All-Around, Double/Triple Gate transistors and Post-Silicon technologies like Graphene and Molecular transistors. The technology files (physical parameters)are derived from ITRS roadmap. Transistor models for electrical quantities such as drive current Ion, Off-state current Ioff, Gate leakage current Igate, Threshold voltage Vth etc are integrated inside TAMTAMS. We have shown in our results the tunnelling effect in a transistor i-e how change in Oxide thickness Tox , using parametric analysis, affects gate leakage current Igate . This highlights the intensive nature of the analysis performed with TAMTAMS web. We have shown in our results how static and dynamic power consumption of a Vertex 4 FPGA can be compared for BULK, SOI, DG, GAA and molecular transistor-based technologies. This highlights the extensive nature of the analysis performed with the TAMTAMS Web tool.
For interconnection and gate level analysis, NAND and NOR are incorporated inside TAMTAMS as universal gates. Different capacitance models are defined and integrated that acts as bridge between transistors based technologies and system level modules like FPGA, Adders, Multipliers, Memories etc. The tool enables Performance estimation at gate level as well e.g we have shown how reliability models predict the increase in Static/Dynamic power consumption and Delay time for NAND/NOR based circuits. TAMTAMS can be used to analyse different applications under many scenarios. For example, at interconnection level, electromigration models enable the comparison of electromigration effect in copper and Aluminium material based interconnection wires.
At system level, different system level modules are written and integrated inside TAMTAMS. For example FPGA module, different types of Adder modules, Multipliers, Content Addressable Memory (CAM), Static RAM (SRAM), Arithmetic and Logic unit (ALU), Finite impulse response filters (FIR) etc. We have shown in the analysis, how a static/dynamic power consumption of an Adder and CAM circuit are affected taking reliability issues into consideration using different technologies. Also in the system level analysis, we have compared performance analysis for Virtex 4 FPGA CLB using current and emerging transistor technologies. Time and space does not allow us to discuss all the technologies and all the integrated modules as it is beyond the scope of this work, but we have analysed few interesting case studies in the analysis part.
Regarding the development of the tool TAMTAMS Web, we conclude we have achieved enough and have come a long way considering from where we started, but it is still an on-going work as the technology further evolves. Further we conclude that the tool TAMTAMS Web, as presented in this work, can prove vital for i) technologists in analysis of the process variations ii) for designers to evaluate their circuit design at each of the three levels of abstraction, iii) for transistor model developers to benchmark their proposed models with other industry standard models and iv) for the futurists to know what can be predicted in the years to come regarding transistor based circuit.
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Abel, Christopher J. "An investigation of nonideal process and device effects in fundamental CMOS analog subcircuits /". The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487865929454587.
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Greig, Thomas Alexander. "Development of CMOS active pixel sensors". Thesis, Brunel University, 2008. http://bura.brunel.ac.uk/handle/2438/5345.
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This thesis describes an investigation into the suitability of complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) devices for scientific imaging applications. CMOS APS offer a number of advantages over the established charge-coupled device (CCD) technology, primarily in the areas of low power consumption, high-speed parallel readout and random (X-Y) addressing, increased system integration and improved radiation hardness. The investigation used a range of newly designed Test Structures in conjunction with a range of custom developed test equipment to characterise device performance. Initial experimental work highlighted the significant non-linearity in the charge conversion gain (responsivity) and found the read noise to be limited by the kTC component due to resetting of the pixel capacitance. The major experimental study investigated the contribution to dark signal due to hot-carrier injection effects from the in-pixel transistors during read-out and highlighted the importance of the contribution at low signal levels. The quantum efficiency (QE) and cross-talk were also investigated and found to be limited by the pixel fill factor and shallow depletion depth of the photodiode. The work has highlighted the need to design devices to explore the effects of individual components rather than stand-alone imaging devices and indicated further developments are required for APS technology to compete with the CCD for high-end scientific imaging applications. The main areas requiring development are in achieving backside illuminated, deep depletion devices with low dark signal and low noise sampling techniques.
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Moen, Kurt Andrew. "Predictive modeling of device and circuit reliability in highly scaled CMOS and SiGe BiCMOS technology". Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44700.
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The advent of high-frequency silicon-based technologies has enabled the design of mixed-signal circuits that incorporate analog, RF, and digital circuit components to build cost-effective system-on-a-chip solutions. Emerging applications provide great incentive for continued scaling of transistor performance, requiring careful attention to mismatch, noise, and reliability concerns. If these mixed-signal technologies are to be employed within space-based electronic systems, they must also demonstrate reliability in radiation-rich environments. SiGe BiCMOS technology in particular is positioned as an excellent candidate to satisfy all of these requirements. The objective of this research is to develop predictive modeling tools that can be used to design new mixed-signal technologies and assess their reliability on Earth and in extreme environments. Ultimately, the goal is to illuminate the interaction of device- and circuit-level reliability mechanisms and establish best practices for modeling these effects in modern circuits. To support this objective, several specific areas have been targeted first, including a TCAD-based approach to identify performance-limiting regions in SiGe HBTs, measurement and modeling of carrier transport parameters that are essential for predictive TCAD, and measurement of device-level single-event transients to better understand the physical origins and implications for device design. These tasks provide the foundation for the bulk of this research, which addresses circuit-level reliability challenges through the application of novel mixed-mode TCAD techniques. All of the individual tasks are tied together by a guiding theme: to develop a holistic understanding of the challenges faced by emerging broadband technologies by coordinating results from material, device, and circuit studies.
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Canals, Gil Joan. "A portable device for time-resolved fluorescence based on an array of CMOS SPADs with integrated microfluidics". Doctoral thesis, Universitat de Barcelona, 2020. http://hdl.handle.net/10803/669582.
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Traditionally, molecular analysis is performed in laboratories equipped with desktop instruments operated by specialized technicians. This paradigm has been changing in recent decades, as biosensor technology has become as accurate as desktop instruments, providing results in much shorter periods and miniaturizing the instrumentation, moving the diagnostic tests gradually out of the central laboratory. However, despite the inherent advantages of time-resolved fluorescence spectroscopy applied to molecular diagnosis, it is only in the last decade that POC (Point Of Care) devices have begun to be developed based on the detection of fluorescence, due to the challenge of developing high-performance, portable and low-cost spectroscopic sensors. This thesis presents the development of a compact, robust and low-cost system for molecular diagnosis based on time-resolved fluorescence spectroscopy, which serves as a general-purpose platform for the optical detection of a variety of biomarkers, bridging the gap between the laboratory and the POC of the fluorescence lifetime based bioassays. In particular, two systems with different levels of integration have been developed that combine a one-dimensional array of SPAD (Single-Photon Avalanch Diode) pixels capable of detecting a single photon, with an interchangeable microfluidic cartridge used to insert the sample and a laser diode Pulsed low-cost UV as a source of excitation. The contact-oriented design of the binomial formed by the sensor and the microfluidic, together with the timed operation of the sensors, makes it possible to dispense with the use of lenses and filters. In turn, custom packaging of the sensor chip allows the microfluidic cartridge to be positioned directly on the sensor array without any alignment procedure. Both systems have been validated, determining the decomposition time of quantum dots in 20 nl of solution for different concentrations, emulating a molecular test in a POC device.Tradicionalment, l'anàlisi molecular es realitza en laboratoris equipats amb instruments de sobretaula operats per tècnics especialitzats. Aquest paradigma ha anat canviant en les últimes dècades, a mesura que la tecnologia de biosensor s'ha tornat tan precisa com els instruments de sobretaula, proporcionant resultats en períodes molt més curts de temps i miniaturitzant la instrumentació, permetent així, traslladar gradualment les proves de diagnòstic fora de laboratori central. No obstant això i malgrat els avantatges inherents de l'espectroscòpia de fluorescència resolta en el temps aplicada a la diagnosi molecular, no ha estat fins a l'última dècada que s'han començat a desenvolupar dispositius POC (Point Of Care) basats en la detecció de la fluorescència, degut al desafiament que suposa el desenvolupament de sensors espectroscòpics d'alt rendiment, portàtils i de baix cost. Aquesta tesi presenta el desenvolupament d'un sistema compacte, robust i de baix cost per al diagnòstic molecular basat en l'espectroscòpia de fluorescència resolta en el temps, que serveixi com a plataforma d'ús general per a la detecció òptica d'una varietat de biomarcadors, tancant la bretxa entre el laboratori i el POC dels bioassaigs basats en l'anàlisi de la pèrdua de la fluorescència. En particular, s'han desenvolupat dos sistemes amb diferents nivells d'integració que combinen una matriu unidimensional de píxels SPAD (Single-Photon Avalanch Diode) capaços de detectar un sol fotó, amb un cartutx microfluídic intercanviable emprat per inserir la mostra, així com un díode làser UV premut de baix cost com a font d'excitació. El disseny orientat a la detecció per contacte de l'binomi format pel sensor i la microfluídica, juntament amb l'operació temporitzada dels sensors, permet prescindir de l'ús de lents i filtres. Al seu torn, l'empaquetat a mida de l'xip sensor permet posicionar el cartutx microfluídic directament sobre la matriu de sensors sense cap procediment d'alineament. Tots dos sistemes han estat validats determinant el temps de descomposició de "quantum dots" en 20 nl de solució per a diferents concentracions, emulant així un assaig molecular en un dispositiu POC.
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Brotman, Susan Rose. "The Evaluation of Device Model Dependence in the Design of a High-Frequency, Analog, CMOS Transconductance-C Filter". PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4701.
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It is important to have the ability to predict the effects of device model variation when designing integrated transconductance-C type active filters. Applying these filters to integrated circuit design has become increasingly popular due to its ease of implementation in monolithic form. With the introduction of fully automated design tools, predictable behavior of high-level variables becomes still more important. The purpose of this study is to evaluate the process parameter spread of analog device models to determine the effect on the design parameters of an active filter. This information's significant contribution directly effects the feasibility and realization of automating analog filter design. In order to explore the dependence of filter performance on the device v model parameter spread, a fifth-order inverse Chebyshev filter is designed and simulated using a two year history of process models. It has not been observed that higher order filters have been successfully designed using fully automated design tools. This filter was realized using automated filter design currently being developed in parallel with this study. A single-ended input to single-ended output transconductance amplifier is chosen for this design for its simplicity and small size. Differential performance is easily adapted with exact duplication which is demonstrated in the measurements of the fabricated filter. Simulation of the design is performed using MOSIS SCNA device parameters. Filter performance data such as cutoff frequency, stopband attenuation, and phase response is collected. Experimental results from the fabricated device are compared to simulation and the original prototype. 2 It is shown that the most predicable effect on the design parameters of a filter is caused by the parasitic output conductance parameter g0. This process dependent variable causes both a deviation in the cutoff frequency, and a decrease in the filter quality factor. In addition, it is also shown that the practice employed to predistort for absorption of parasitic capacitors in a MOS technology is a very effective tool in the reduction of capacitive process dependence.n software
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MA, JUN. "STUDY OF GATE OXIDE BREAKDOWN AND HOT ELECTRON EFFECT ON CMOS CIRCUIT PERFORMANCES". Doctoral diss., University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3547.
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In the modern semiconductor world, there is a significant scaling of the transistor dimensions--The transistor gate length and the gate oxide thickness drop down to only several nanometers. Today the semiconductor industry is already dominated by submicron devices and other material devices for the high transistor density and performance enhancement. In this case, the semiconductor reliability issues are the most important thing for commercialization. The major reliability issues caused by voltage are hot carrier effects (HCs) and gate oxide breakdown (BD) effects. These issues are recently more important to industry, due to the small size and high lateral field in short-channel of the device will cause high electrical field and other reliability issues. This dissertation primarily focuses on the study of the CMOS device gate oxide breakdown effect on different kinds of circuits performance, also some HC effects on circuit's performance are studied. The physical mechanisms for BD have been presented. A practical and accurate equivalent breakdown circuit model for the CMOS device was studied to simulate the RF performance degradation on the circuit level. The BD location effect has been evaluated. Furthermore, a methodology was developed to predict the BD effects on the circuit's performances with different kinds of BD location. It also provides guidance for the reliability considerations of the digital, analog, and RF circuit design. The BD effects on digital circuits SRAM, analog circuits Sample&Hold, and RF building blocks with the nanoscale device--low noise amplifier, LC oscillator, mixer, and power amplifier, have been investigated systematically. Finally 90 nm device will be used to study the HC effect on the circuit's performance.
The contributions of this dissertation include: Providing a thorough study of the gate oxide breakdown issues caused by the voltage stress on the device--from device level to circuit level; Studying real voltage stress case--high frequency (950 MHz) dynamic stress, and comparing with the traditional DC stress; A simple, practical, and analytical method is derived to study the gate oxide breakdown effect including breakdown location effect and soft / hard breakdown on the digital, analog and RF circuits performances. A brief introduction and simulation for 90 nm device HC effect provide some useful information and helpful data for the industry. The gate oxide breakdown effect is the most common device reliability issue. The successful results of this dissertation, from device level to circuit level, provide an insight on how the BD affects the circuit's performance, and also provide some useful data for the circuit designers in their future work.Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD
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LI, HANG. "DESIGN OF A 32 BY 32 BIT READ HEAD DEVICE FOR PAGE-ORIENTED OPTICAL MEMORY". University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1037304111.
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TANG, JIANJING. "DESIGN AND ANALYSIS OF A 32X32-BIT DATABASE FILTER CHIP BASED ON A CMOS COMPATIBLE PHOTONIC VLSI DEVICE TECHNOLOGY". University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1059399964.
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Larsen, Frode. "Bipolar device characterization and design in CMOS technologies for the design of high-performance low-cost BiCMOS analog integrated circuits /". The Ohio State University, 1994. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487857546387163.
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Nikolaidis, Théodoros. "Optimisation des performances ESD de circuits intègres CMOS submicroniques". Grenoble INPG, 1995. http://www.theses.fr/1995INPG0185.
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Apres avoir presente les notions de base au sujet des decharges electrostatiques (esd) (origine des decharges electrostatiques, modeles de decharge, effet de snap-back et effet de deuxieme claquage, modelisation des effets esd, caracterisation et methodes d'analyse de defaillance ainsi que modes de defaillance), les structures de protection de base des deux procedes cmos de cinq cent et trois cent cinquante nanometres (diodes zener-ldd et transistors npn lateraux et nmos avec/sans ldd) ont ete analysees et optimisees a l'egard des contraintes esd. Ensuite, la performance esd de circuits integres avec des differentes configurations des etages d'entree/sortie utilisant ces structures de protection a ete egalement analysee et optimisee
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Alzoubi, Khawla Ali. "NANO-ELECTRO-MECHANICAL SWITCH (NEMS) FOR ULTRA-LOW POWER PORTABLE EMBEDDED SYSTEM APPLICATIONS: ANALYSIS, DESIGN, MODELING, AND CIRCUIT SIMULATION". Case Western Reserve University School of Graduate Studies / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=case1278511770.
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Sahoo, Amit Kumar. "Electro-thermal Characterizations, Compact Modeling and TCAD based Device Simulations of advanced SiGe : C BiCMOS HBTs and of nanometric CMOS FET". Thesis, Bordeaux 1, 2012. http://www.theses.fr/2012BOR14557/document.
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Ce travail de thèse présente une évaluation approfondie des différentes techniques de mesure transitoire et dynamique pour l’évaluation du comportement électro-thermique des transistors bipolaires à hétérojonctions HBT SiGe:C de la technologie BiCMOS et des transistors Métal-Oxyde-Semiconducteur à effet de champ (MOSFET) de la technologie CMOS 45nm. En particulier, je propose une nouvelle approche pour caractériser avec précision le régime transitoire d'auto-échauffement, basée sur des mesures impulsionelles. La méthodologie a été vérifiée par des mesures statiques à différentes températures ambiantes, des mesures de paramètres S à basses fréquences et des simulations thermiques transitoires. Des simulations thermiques par éléments finis (TCAD) en trois dimensions ont été réalisées sur les transistors HBTs de la technologie submicroniques SiGe: C BiCMOS. Cette technologie est caractérisée par une fréquence de transition fT de 230 GHz et une fréquence maximum d’oscillation fMAX de 290 GHz. Par ailleurs, cette étude a été réalisée sur les différentes géométries de transistor. Une évaluation complète des mécanismes d'auto-échauffement dans les domaines temporels et fréquentiels a été réalisée. Une expression généralisée de l'impédance thermique dans le domaine fréquentiel a été formulée et a été utilisé pour extraire cette impédance en deçà de la fréquence de coupure thermique. Les paramètres thermiques ont été extraits par des simulations compactes grâce au modèle compact de transistors auquel un modèle électro-thermique a été ajouté via le nœud de température. Les travaux théoriques développés à ce jour pour la modélisation d'impédance thermique ont été vérifiés avec nos résultats expérimentaux. Il a été montré que, le réseau thermique classique utilisant un pôle unique n'est pas suffisant pour modéliser avec précision le comportement thermique transitoire et donc qu’un réseau plus complexe doit être utilisé. Ainsi, nous validons expérimentalement pour la première fois, le modèle distribué électrothermique de l'impédance thermique utilisant un réseau nodal récursif. Le réseau récursif a été vérifié par des simulations TCAD, ainsi que par des mesures et celles ci se sont révélées en excellent accord. Par conséquent, un modèle électro-thermique multi-géométries basé sur le réseau récursif a été développé. Le modèle a été vérifié par des simulations numériques ainsi que par des mesures de paramètre S à basse fréquence et finalement la conformité est excellente quelque soit la géométrie des dispositifsAn extensive evaluation of different techniques for transient and dynamic electro-thermal behavior of microwave SiGe:C BiCMOS hetero-junction bipolar transistors (HBT) and nano-scale metal-oxide-semiconductor field-effect transistors (MOSFETs) have been presented. In particular, new and simple approach to accurately characterize the transient self-heating effect, based on pulse measurements, is demonstrated. The methodology is verified by static measurements at different ambient temperatures, s-parameter measurements at low frequency region and transient thermal simulations. Three dimensional thermal TCAD simulations are performed on different geometries of the submicron SiGe:C BiCMOS HBTs with fT and fmax of 230 GHz and 290 GHz, respectively. A comprehensive evaluation of device self-heating in time and frequency domain has been investigated. A generalized expression for the frequency-domain thermal impedance has been formulated and that is used to extract device thermal impedance below thermal cut-off frequency. The thermal parameters are extracted through transistor compact model simulations connecting electro-thermal network at temperature node. Theoretical works for thermal impedance modeling using different networks, developed until date, have been verified with our experimental results. We report for the first time the experimental verification of the distributed electrothermal model for thermal impedance using a nodal and recursive network. It has been shown that, the conventional single pole thermal network is not sufficient to accurately model the transient thermal spreading behavior and therefore a recursive network needs to be used. Recursive network is verified with device simulations as well as measurements and found to be in excellent agreement. Therefore, finally a scalable electro-thermal model using this recursive network is developed. The scalability has been verified through numerical simulations as well as by low frequency measurements and excellent conformity has been found in for various device geometries
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Simionovski, Alexandre. "Sensor de corrente transiente para um sistema de proteção de circuitos integrados contra erros induzidos por radiação ionizante". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/179523.
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Este trabalho apresenta o desenvolvimento de um sensor de corrente transiente destinado a detectar a ocorrência de um evento transiente causado pela incidência de radiação ionizante em um circuito integrado. Iniciando com uma descrição dos efeitos da radiação sobre os circuitos integrados e dos tipos de radiação de interesse, os fundamentos da técnica Bulk- BICS são apresentados e as propostas existentes na literatura são expostas e avaliadas, com ênfase no sensor que utiliza a célula de memória dinâmica DynBICS, resultado de um trabalho prévio e do qual se dispõe de amostras fabricadas. Sobre essas amostras são efetuados testes elétricos, um ensaio de dose total irradiada TID e um ensaio de estimulação laser, cujos resultados são apresentados e confirmam a funcionalidade da topologia da célula de memória dinâmica aplicada a circuitos Bulk-BICS. Em seguida, é apresentada a topologia da célula de memória integrativa como uma evolução da célula de memória dinâmica e propõe-se o circuito de um novo sensor Bulk-BICS baseado na nova célula. O funcionamento elétrico do circuito desse novo sensor TRIBICS é avaliado através de simulação de circuitos determinando-se a sensibilidade e o tempo de resposta do sensor utilizando-se pulsos de corrente em dupla exponencial. É feita uma análise do funcionamento da célula de memória estática e, através de uma comparação de desempenho entre as células de memória estáticas utilizadas em três circuitos propostos e a célula de memória integrativa, utilizando um modelo simplificado, mostra-se que a célula de memória integrativa é mais rápida e sensível do que as contrapartes estáticas O sensor TRIBICS é então simulado em conexão com um modelo de dispositivo, sendo antes apresentados os modelos TCAD do inversor utilizado como alvo da incidência da radiação nas simulações. São apresentados resultados obtidos individualmente para o transistor NMOS e para o transistor PMOS, nos quais se mostra a formação de um canal condutivo entre dreno e fonte durante o SET. Mostra-se, também, que os resultados obtidos com a simulação de dispositivos não concorda com aqueles proporcionados pela simulação de circuitos no tocante à divisão das correntes transitórias entre dreno, fonte e substrato. O resultado das simulações de dispositivo efetuadas com os modelos TCAD em modo misto com o circuito TRIBICS descrito em SPICE mostram a relação entre a transferência de energia da irradiação LET e a efetiva deteção do SET provocado, em função da distância entre os contatos de bulk ou substrato, permitindo determinar a máxima distância entre contatos para 100% de certeza na deteção do SET. Com isso, obtém-se uma estimativa do número de transistores que pode ser monitorado pelos Bulk-BICS. É proposta a estratégia de implementação dos Bulk-BICS na forma de uma standard cell a ser posicionada entre os grupos de transistores sob monitoração, e uma estimativa da relação entre as áreas dos transistores monitorados e do Bulk-BICS é apresentada. Por fim, é estudada a questão da fabricação dos Bulk-BICS no mesmo substrato dos transistores monitorados e uma maneira de fazê-la é proposta. Os resultados encontrados permitem definir a viabilidade e a eficácia da técnica Bulk-BICS como forma de deteção de eventos transientes em sistemas digitais.A current sensor to detect the occurrence of a single-event transient that is caused by the incidence of ionizing radiation in an integrated circuit is presented. Radiation of interest and their effects on the integrated circuits are discussed. Fundamentals of the Bulk-BICS technique and the circuits proposed in the literature to implement this technique are discussed and evaluated, with emphasis on the dynamic memory cell-based circuit DynBICS, which was developed as a previous work and with fabricated samples available. Experimental results obtained from a series of electrical tests, a TID test, and a laser-stimulated test that were conducted on a number of fabricated and packaged samples are presented. The results confirm that the dynamic memory cell is suitable and robust enough to be used in Bulk-BICS circuits. Next, evolution of the dynamic memory cell into an integrative memory cell is discussed and the circuit of a Bulk-BICS using this new memory cell topology is presented. The electrical operation of this new sensor TRIBICS is evaluated using circuit simulations. By using double-exponential current pulses, both the sensitivity and the response time are determined. The static memory cell operation is analyzed and a comparison of performance between static and integrative cells is performed using a simplified model. The results show that the integrative memory cell is faster and more sensitive than the static cells used in three state-ofthe- art sensors published in literature Then the TRIBICS sensor is simulated connected to a TCAD-modeled device, comprising an inverter, which is used as a target for radiation impact. TCAD models are previously presented and the results obtained when the PMOS and NMOS transistors are separately excited by radiation show the formation of a conductive link between drain and source regions during the occurrence of SET. The simulations also show that the results obtained by using TCAD simulations do not agree with the ones obtained by using circuit simulation regarding the current share among drain, source and bulk during the SET. Mixed-mode simulations using the TCAD models in conjunction of TRIBICS circuits described in SPICE show the relationship between LET and the effective SET-detection with the inter-tap distance as a parameter, and allows to determine the inter-tap distance for 100% of SET detection efficiency. Based on these results, an estimate of how many transistors can be monitored by the Bulk-BICS is obtained. It is proposed to implement the Bulk-BICS as a standard cell, to be positioned in between the standard cell that compose a digital circuit and the area overhead necessary to implant the sensors in a real circuit is estimated. The problem on how to manufacture the Bulk-BICS circuit in the same substrate of the monitored transistors is studied and a solution is proposed. The results show the viability and effectiveness of the Bulk-BICS technique, as a means to detect single-event transients in digital systems.
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Chouard, Florian Raoul Verfasser], Doris [Akademischer Betreuer] [Schmitt-Landsiedel i Sebastian M. [Akademischer Betreuer] Sattler. "Device Aging in Analog Circuits for Nanoelectronic CMOS Technologies / Florian Raoul Chouard. Gutachter: Sebastian M. Sattler ; Doris Schmitt-Landsiedel. Betreuer: Doris Schmitt-Landsiedel". München : Universitätsbibliothek der TU München, 2012. http://d-nb.info/1024355020/34.
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Osberger, Laurent. "Etude de magnétomètres haute performance intégrés en technologie silicium". Thesis, Strasbourg, 2017. http://www.theses.fr/2017STRAD012.
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La thématique de ce sujet de thèse porte sur l'étude des capteurs de champ magnétique intégrés en technologie CMOS standard basse tension sans étapes de fabrication supplémentaires. La co-intégration du transducteur (l'élément sensible qui transforme le champ magnétique en une grandeur électrique) et de son électronique de conditionnement du signal sur la même puce permet réaliser des fonctions spécifiques qui améliorent significativement les performances du capteur. Les travaux présentés dans cette thèse portent plus particulièrement sur deux types de transducteur : le transducteur à effet Hall dit vertical et un magnéto-transistor particulier appelé « CHOPFET ». Nous avons développé des modèles numériques de ces transducteurs afin d’analyser finement leurs comportement mais aussi d’optimiser leurs performances. En nous basant sur ces résultats, nous avons adapté des techniques de traitement du signal et proposé plusieurs architectures originales dédiées au conditionnement du signal magnétique. Cela a permis d’améliorer significativement les performances de ces capteurs en termes de résolution, d’offset et de consommation électriqueThe subject of thesis subject concerns the study of magnetic field sensors integrated in low-voltage standard CMOS process without additional post-processing steps. Co-integrating the magnetic transducer (the sensitive element transforming the magnetic field into an electrical quantity) together with its conditioning electronics onto a same chip allows to implement specific features, which dramatically improve the sensor performances. This work particularly focuses on two types of transducer: the vertical Hall device and a specific magneto-transistor called “CHOPFET”. We developed numerical simulation models in order to predict and optimize the behavior of these transducers. Based on the results, we adapted dedicated signal processing techniques and proposed several innovative magnetic signal conditioning architectures. This led to significant improvement in terms of resolution, offset and power consumption
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Ma, Wei. "Linearity Analysis of Single and Double-Gate Silicon-On-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistor". Ohio University / OhioLINK, 2004. http://www.ohiolink.edu/etd/view.cgi?ohiou1103138153.
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Jouvet, Nicolas. "Intégration hybride de transistors à un électron sur un noeud technologique CMOS". Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00863770.
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Cette étude porte sur l'intégration hybride de transistors à un électron (single-electron transistor, SET) dans un noeud technologique CMOS. Les SETs présentent de forts potentiels, en particulier en termes d'économies d'énergies, mais ne peuvent complètement remplacer le CMOS dans les circuits électriques. Cependant, la combinaison des composants SETs et MOS permet de pallier à ce problème, ouvrant la voie à des circuits à très faible puissance dissipée, et à haute densité d'intégration. Cette thèse se propose d'employer pour la réalisation de SETs dans le back-end-of-line (BEOL), c'est-à-dire dans l'oxyde encapsulant les CMOS, le procédé de fabrication nanodamascène, mis au point par C. Dubuc.
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Bari, Mohammad Rezaul. "Fabrication, Characterization, and Modelling of Self-Assembled Silicon Nanostructure Vacuum Field Emission Devices". Thesis, University of Canterbury. Electrical and Computer Engineering, 2011. http://hdl.handle.net/10092/6601.
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The foundation of vacuum nanoelectronics was laid as early as in 1961 when Kenneth Shoulders proposed the development of vertical field-emission micro-triodes. After years of conspicuous stagnancy in the field much interest has reemerged for the vacuum nanoelectronics in recent years. Electron field emission under high electric field from conventional and exotic nanoemitters, which have now been made possible with the use of modern day technology, has been the driving force behind this renewal of interest in vacuum nanoelectronics. In the research reported in this thesis self-assembled silicon nanostructures were studied as a potential source of field emission for vacuum nanoelectronic device applications.
Whiskerlike protruding silicon nanostructures were grown on untreated n- and p-type silicon surfaces using electron-beam annealing under high vacuum. The electrical transport characteristics of the silicon nanostructures were investigated using conductive atomic force microscopy (C-AFM). Higher electrical conductivities for the nanostructured surface compared to that for the surrounding planar silicon substrate region were observed. Non-ideal diode behaviour with high ideality factors were reported for the individual nanostructure-AFM tip Schottky nanocontacts. This demonstration, indicative of the presence of a significant field emission component in the analysed current transport phenomena was also detailed. Field emission from these nanostructures was demonstrated qualitatively in a lift-mode interleave C-AFM study.
A technique to fabricate integrated field emission diodes using silicon nanostructures in a CMOS process technology was developed. The process incorporated the nanostructure growth phase at the closing steps in the process flow. Turn-on voltages as low as ~ 0.6 V were reported for these devices, which make them good candidates for incorporation into standard CMOS circuit applications.
Reproducible I V characteristics exhibited by these fabricated devices were further studied and field emission parameters were extracted. A new consistent and reliable method to extract field emission parameters such as effective barrier height, field conversion factor, and total emitting area at the onset of the field emission regime was developed and is reported herein. The developed parameter extraction method used a unified electron emission approach in the transition region of the device operation. The existence of an electron-supply limited current saturation region at very high electric field was also confirmed.
Both the C-AFM and the device characterization studies were modelled and simulated using the finite element method in COMSOL Multiphysics. The experimental results – the field developed at various operating environments – are explained in relation to these finite element analyses. Field enhancements at the atomically sharp nanostructure apexes as suggested in the experimental studies were confirmed. The nanostructure tip radius effect and sensitivity to small nanostructure height variation were investigated and mathematical relations for the nanostructure regime of our interest were established. A technique to optimize the cathode-opening area was also demonstrated.
Suggestions related to further research on field emission from silicon nanostructures, optimization of the field emission device fabrication process, and fabrication of field emission triodes are elaborated in the final chapter of this thesis.
The experimental, modelling, and simulation works of this thesis indicate that silicon field emission devices could be integrated into the existing CMOS process technology. This integration would offer goods from both the worlds of vacuum and solid-sate nanoelectronics – fast ballistic electron transport, temperature insensitivity, radiation hardness, high packing density, mature technological backing, and economies of scale among other features.
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Kerber, Andreas. "Methodology for electrical characterization of MOS devices with alternative gate dielectrics". Phd thesis, [S.l. : s.n.], 2004. http://elib.tu-darmstadt.de/diss/000404.
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Bouaziz, Jordan. "Mémoires ferroélectriques non-volatiles à base de (Hf,Zr)O2 pour la nanoélectronique basse consommation". Thesis, Lyon, 2020. http://www.theses.fr/2020LYSEI057.
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Depuis 2005, la miniaturisation des composants mémoires, qui, auparavant, suivait la loi de Moore, a ralenti. Ceci a conduit les chercheurs à multiplier les approches pour continuer à améliorer les dispositifs mémoires. Parmi ces approches, la piste des composants ferroélectriques semble très prometteuse. En 2011, une équipe du NamLab, à Dresde, en Allemagne, a découvert que le HfO2 dopé Si pouvait devenir ferroélectrique, avec une couche isolante de seulement 10 nm, ce qui résout le problème de compatibilité avec l’industrie CMOS des matériaux de structure pérovskite. Depuis, d’autres dopants ont été découverts. Cependant, de nouveaux problèmes freinent désormais l’apparition sur le marché des dispositifs ferroélectriques à base de HfO2. Comprendre les mécanismes qui régissent les propriétés ferroélectriques de ces matériaux est alors devenu un enjeu industriel majeur. Dans ce manuscrit, nous étudions le (Hf,Zr)O2 (HZO), et nous employons une technique peu utilisée pour élaborer ce type de matériau : la pulvérisation cathodique magnétron. L’objectif de cette thèse est d’établir des relations entre les conditions de croissance des différents matériaux et les propriétés électriques, de comprendre les mécanismes qui les régissent, ainsi que de rendre viable les dispositifs mémoires. Lors de l’élaboration de condensateurs, nous démontrons que des propriétés cristallochimiques particulières sont indispensables pour obtenir la ferroélectricité, et de nouvelles propriétés du HZO sont découvertes. Ensuite, nous cherchons à dépasser l’état de l’art. Par pulvérisation, nous obtenons parmi les meilleurs résultats au monde. Les tests industriels d’endurance et de rétention sont poussés au-delà de ce qui avait été fait auparavant dans la littérature. En particulier, l’influence des conditions de contraintes électriques y est décrite en détail, et nous mettons en évidence la présence d’une relaxation au cours des différents tests pouvant s’avérer problématique pour l’avènement d’applications industriels. Ce problème ne semble jamais avoir été clairement identifié auparavantSince 2005, the scaling of memory devices, which used to follow Moore's law, slowed down. This lead researchers to conduct multiple approaches in order to keep improving memory devices. Among these approaches, the pathway on ferroelectric components seems very promising. In 2011, a research team from the NamLab in Dresden, Germany, discovered that Si-doped HfO2 could become ferroelectric with an insulating layer of only 10 nm, which resolves the compatibility issue of perovskite-structured materials with CMOS industry. Since then, other dopants have been investigated. However, new issues are now slowing down the emergence of HfO2-based ferroelectric devices on the market. Understanding the mechanisms behind the ferroelectric properties of these materials has, therefore, become a major industrial issue. In this manuscript, we study (Hf,Zr)O2 (HZO), and we perform an under-utilized technique to elaborate this kind of material: magnetron sputtering. The goal of this thesis is to establish connections between the growth conditions of this material and the electrical properties, to understand the mechanisms behind them, as well as to make the memory devices viable. During the fabrication of the capacitors, we demonstrate that the particular cristallochemical properties are essential to obtain ferroelectricity, and that novel HZO properties are discovered. Afterwards, we seek to cross the state of the art. The results we obtain by sputtering are among the best in the world. The industrial endurance and retention tests are pushed beyond what has been done in the literature so far. Particularly, the influence of electrical stress conditions is thoroughly detailed, and we put to evidence the presence of a relaxation during the different tests that could turn out to become problematic for the emergence of industrial applications. It does not seem that this problem has been identified beforehand
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Chang, Meng-Jen, i 張夢仁. "Automatic Measurement for Device/Process Parameters Extraction of Advanced CMOS Device". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/00152933355850759911.
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碩士國立臺北科技大學
機電整合研究所
89
The MOSFET is the building block of ULSI circuits in microprocessor and dynamics memories. In order to increase the packing density and to improve circuit performance, many researchers have invested their efforts in scaling down the CMOS device size. However, simply reducing device dimension without paying attention to other processing parameters will cause a variety of non-ideal characteristic. In CMOS technology, channel length is a key parameter used for device design and circuit simulation. Though many methods have been proposed for the extraction of effective channel length. Most of them are based on I-V measurement and some others are based on C-V measurement. But they are all failed as the generation goes down to quarter micron or beyond. In this thesis we proposed a new approach for extracting advanced CMOS device parameters by using a modified C-V method, named capacitance-ratio method (C-R method). According to the C-R method, we could determine the effective channel length , metallurgical channel length , process bias , extension overlap bias , source-to-drain series resistance , and the gate to drain capacitance easily. By the algorithm of C-R method, we want to develop an automatic measurement system to help extracting these parameters. With the help of automatic measurement system, one can easily extract parameters and monitor fabrication process. The greatest worth of the system is able to get reasonable and consistent results, besides the cost and time in measurement will be lower in future application. Finally, We show the ease of using our system to extract thin gate oxide parameter.
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Cheng, C. B., i 鄭召寶. "CMOS/SOI Device Simulation:Accumulation Mode vs.Enhancement Mode". Thesis, 1995. http://ndltd.ncl.edu.tw/handle/84418223502980781303.
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碩士國立交通大學
電子研究所
83
Silicon on insulator (SOI) technology is a promising candidate for future ULSI as the quality of SOI material continues to improve. Thin (less than 1000A) SOI film thickness which makes fully depleted SOI MOSFETs is important for minimization of short channel effects, easy isolation, elimination of latch-up, steeper subthreshold slopes, and increased current drive capability which will make low power and high speed devices work well. The purpose of this research is to investigate: A. the dependence of fully depleted SOI as the devices are scaled down to deep submicron area. Three key parameters: (1). The threshold voltage (2). Subthreshold swing (3). Current drive capability B. the scaling rule of CMOS/SOI. Si film thickness, gate oxide thickness , channel length, and channel doping will be the key parameters in this investigation. 2D device simulator is used in device optimization and in gaining insight of physical mechanism.
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Huang, Shin-Duen, i 黃信惇. "Gate oxide reliability of advance CMOS device". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/51931041390158072911.
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碩士國立成功大學
微電子工程研究所碩博士班
91
In this thesis, the sample is an 8inch wafer for 0.15μm technology n-MOSFET’s and p-MOSFET’s and we researched on oxide reliability. As devices scaling down, the device operational voltage and some characteristic still decreases slowly. The area and the thickness of the device oxide layer also decreased that varied the characteristic representation. So the dielectric oxide layer in MOSFET is to pay much attention to people. My experiment focuses on the difference between thin and thick oxide layer and finds the difference of the characteristic between before breakdown and after breakdown. First, I use ramp voltage test and constant voltage test to confer the difference of the I-V changes. Then I use the past breakdown definition to analyze the I-V curve. I want to find what influence on device between thin and thick oxide layer. Besides, I try to generalize it has the more accurate way to define the device breakdown. In these experiments, we used ICS (Interactive Characterization Software) to control HP4155B (Semiconductor Parameter Analyzer) produced by Agilent Technologies and 4200-SCS system produced by Keithley to finish various researches.
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Lin, Feng-Wei, i 林峰濰. "Device-partition method and its application to 2-D CMOS device simulation". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/68438742946534956455.
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碩士國立中央大學
電機工程研究所
91
Abstract In this thesis, we focus on how to effectively save required memory space when simulate a semiconductor device. We develop four different methods to simulate semiconductor devices. First method is coupled method(CM). It requires biggest memory space in all of the methods. Second method is partial decoupled method(PDM). The memory space with PDM is less than CM. Last, we develop device-partition method. It can be divided into two different modes. One is overlapped mode, the other is unoverlapped mode. The advantage of device-partition method is that our program can be compiled without limitation by memory space. We will use these methods to simulate an n-channel MOSFET and compare simulation result. Finally, we will use these methods to simulate a CMOS circuit and compare simulation result also.
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Wang, Chun-Sheng, i 王俊升. "Study on substrate effect of RF CMOS device". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/32772666654583251198.
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碩士國立中興大學
電機工程學系所
98
In this thesis, the substrate resistance of multi-finger MOSFET have been analyzed. Concentrate on the extraction methods and performance analysis of substrate resistance. Using four kinds of guard-ring structure of NMOS transistors to analyze the behavior of Rsub. A small signal model with substrate resistance is proposed to extract the model parameters. In corporate the calculation of substrate resistance using layout configuration, the substrate resistance is characterized comprehensively. We can find that transistor M3(two-sides structure) has biggest Rsub, M1(ring structure) is smallest. To predict the behavior using layout configuration and identify the impact factor in the layout of Rsub. Finaly, two figure-of-merit (FOMs) of MOSFETs, cut off frequency (fT) and maximum oscillation frequency (fmax) were used to characterize these four NMOS FETs in radio-frequency operation. The results show that the fT are the same , while the fmax is proportional to the Rsub. Hence the Rsub affects unilateral power gain U. Measurement demonstrates that the proposed algorithm is consort with the extract approach.
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Tsao, Chih-Pin, i 曹志彬. "Hot-Carrier reliability in deep submicron CMOS device". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/16925700898041641574.
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碩士國立成功大學
微電子工程研究所碩博士班
90
In this study, the effects of hot-carrier induced drain current degradation and gate leakage current induced by ultra-thin gate oxide on 0.18μm and 0.15μm CMOS devices will be investigated. In the first chapter, the background of hot-carrier effects will be discussed. Results show that in deep submicron device, the worst case of hot-carrier induced drain current degradation is characterized at drain voltage higher than 0.1V which was well known as the worst case condition in long channel device. The worst case of characterized Vd was found to lager at higher temperature and substrate bias. A simplified model was presented to explain this new observation. Results show that the lowering of quasi-fermi level and the effect of the velocity saturation region (DL) contribute to the monotonically decrease ΔID/ID (%) as a function of measured VD. However, Qinv near the drain side also decreases since Vc increases. This mechanism results in the increase in DId/Id. Hence, the value of the worst case of characterized Vd is determined by this two competing mechanisms. In the third chapter, enhanced hot-carrier induced Id degradation under high gate voltage stress was observed in pMOSFETs. Some mechanisms which may contribute to this phenomenon are discussed here。Results show that (I) F-N tunneling-current stress has finite effect on enhanced high gate voltage stress although gate oxide electric field as high as above 15MV/cm was applied. Anode hole injection model was adopted to explain the server F-N tunneling effect on pMOSFET than on nMOSFET. The hole component of the injected F-N tunneling-current was found to the dominant mechanism. (II) Electron tunneling from the gate due to ultra-thin gate oxide and Auger recombination assisted hot hole energy gain process were found to contribute to this phenomenon. Besides, this enhancement in Id degradation is more significant under high temperatures or lower supply voltages. Finally, in the last chapter, future work is discussed.
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Bhatnagar, Mayank. "Implementing single electron device in standard CMOS process /". 2008. http://proquest.umi.com/pqdweb?did=1597619851&sid=3&Fmt=2&clientId=10361&RQT=309&VName=PQD.
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LIN, JIAN-HUI, i 林建輝. "The CMOS device characteristics under high-frequency operations". Thesis, 1990. http://ndltd.ncl.edu.tw/handle/20335808483286326160.
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Chang, Kai-Chun, i 張凱鈞. "CMOS LNAs Using Integrated Passive Device Technology and Design of SPDT CMOS Switch Circuit". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/22114588493060895606.
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碩士國立交通大學
電信工程研究所
104
This thesis is mainly classified into two major parts: First, starting from Chapter 2, we discuss the measured results of MOSFET, especially the performance of noise figure and optimal noise impedance. From measured results, the MOSFET devices possess low noise but fail to perform low noise in the circuits. Thus, it is important to find the main reason of noise figure degradation in the circuits. In Chapter 3, we consider all situations through simulations. Then, we find that the main cause is the input matching inductance. Due to the mismatch and non-ideal effect, they will contribute the most noise in the circuit. As a result, we substitute inductances using integrated passive process for the input match inductors. This design can improve the noise figure of a low noise amplifier (LNA). Using single-band, dual-band and wide-band LNAs, the MOS LNAs with/without IPD are compared by CMOS 0.18 m process. Second, Single-pole Double Throw (SPDT) switches are discussed. A SPDT needs to take into considerations insertion loss (IL), isolation and power handling. A switch in front of a power amplifier must handle large power. Therefore, body floating method and increasing the bias voltage are employed. The asymmetric SPDT switches are designed using CMOS process.
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Jamil, Mustafa. "Germanium and epitaxial Ge:C devices for CMOS extension and beyond". Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-08-3783.
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This work focuses on device design and process integration of high-performance Ge-based devices for CMOS applications and beyond. Here we addressed several key challenges towards Ge-based devices, such as, poor passivation, underperformance of nMOSFETs, and incompatibility of fragile Ge wafers for mass production. We simultaneously addressed the issues of bulk Ge and passivation for pMOSFETs, by fabricating Si-capped epitaxial Ge:C(C<0.5%) devices. Carbon improves the crystalline quality of the channel, while Si capping prevents GeOx formation, creates a quantum well for holes and thus improves mobility. Temperature-dependent characterization of these devices suggests that Si cap thickness needs to be optimized to ensure highest mobility. We developed a simple approach to grow GeO₂ by rapid thermal oxidation, which provides improved passivation, especially for nMOSFETs. The MOSCAPs with GeO₂ passivation show ~10× lower Dit (~8×10¹¹ cm⁻²eV⁻¹) than that of the HF-last devices. The Ge (111) nMOSFETs with GeO₂ passivation show ~2× enhancement in mobility (~715 cm²V⁻¹s⁻¹ at peak) and ~1.6× enhancement in drive current over control Si (100) devices. For improved n⁺/p junctions, we proposed a simple technique of rapid thermal diffusion from "spin-on-dopants" to avoid implantation damage during junction formation. These junctions show a high ION/IOFF ratio (~10⁵⁻⁶) and an ideality factor of ~1.03, indicating a low defect density, whereas, ion-implanted junctions show higher Ioff (by ~1-2 orders) and a larger ideality factor (~1.45). Diffusion-doped and GeO₂-passivated Ge(100) nMOSFETs show a high ION/IOFF ratio (~10⁴⁻⁵) , a low SS (111 mV/decade), and a high [mu]eff (679 cm²V⁻¹s⁻¹ at peak). Moreover, diffusion-doped Ge (111) nMOSFETs show even higher [mu]eff (970 cm²V⁻¹s⁻¹ at peak) that surpasses the universal Si mobility at low Eeff. For Beyond CMOS devices, we investigated Mn-doped Ge:C-on-Si (100), a novel Si-compatible ferromagnetic semiconductor. The investigation suggests that the magnetic properties of these films depend strongly on crystalline structure and Mn concentration. On a different approach, we developed LaOx/SiOx barrier for Spin-diodes that reduces contact resistance by ~10⁴, compared to Al₂O₃ controls and hence is more conducive for spin injection. These ferromagnetic materials and devices can potentially be useful for novel spintronic devices.text
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Mangan, Alain Marc. "Millimetre-wave device characterization for nano-CMOS IC design". 2005. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=370235&T=F.
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Chen, kuan-hao, i 陳冠豪. "High Frequency Deep-Submicron CMOS device and circuit modeling". Thesis, 2000. http://ndltd.ncl.edu.tw/handle/02579999569987998973.
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碩士長庚大學
電機工程研究所
88
As the gate lengths of silicon MOSFET’s become smaller and smaller, The conventional device model is not accurate in the GHz range. Because BSIM3v3 has been widely accepted as a standard CMOS model for low and medium frequency applications, we must find a method to solve this problem. Recent research has proposed a high frequency device model by adding a complicated substrate resistance network and modifying the BSIM3v3 source code. So we study the sensitivities of S-parameter to each model parameter at 1GHz and some guide lines are given for parameter extraction. A parameter extraction technique utilizing S-parameter data at the GHz range is finally proposed for a SPICE BSIM3V3 for RF MOSFET. Besides, chip size increases and signal wavelengths approach interconnect wire lengths. Therefore, signal delay due to interconnect become a major concern for high-performance integrated circuits. That is because the capacitance and resistance of wires increase rapidly as chip size grows and the minimum feature size is reduced. The purpose of this project is to establish RF CMOS ring oscillators delay model and to study the sensitivity of delay time to device parameters. The dimensions of the multi-finger type MOSFET is W/L=200μm /0.25μm~W/L=200μm/0.5μm, but we use single finger type NMOS (W/L=5μm/0.35μm) and PMOS (W/L=10μm/0.35μm)devices in ring oscillator. The extracted substrate resistance in high frequency device model for multi-finger type devices cannot be directly applied to the single finger type device in ring oscillators. First, we will establish NMOS (W/L=5μm/0.35μm) model and PMOS (W/L=10μm/0.35μm) BSIM3V3 model. Second, the substrate resistances are extracted by measuring S-parameter of the multi-finger type MOSFET. The substrate resistances for the single finger type device are subsequently calculated according to a proposed method as described in Chapter4.In general, RF modification of BSIM3V3 model significantly improves the accuracy of the high-frequency performance prediction. Furthermore, For high frequency operation, According to the simulation of ring oscillator performance based on RF MOS model, with further consideration of delay time model’s interconnection effect, the accuracy of delay time prediction is much better improved.
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Su, Jia-Chern, i 蘇嘉晨. "Modeling of Partially Depleted SOI and Bulk CMOS Device". Thesis, 1999. http://ndltd.ncl.edu.tw/handle/66447000338097748373.
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碩士國立臺灣大學
電機工程學研究所
87
In this thesis, analytical models for partially-depleted SOI and Bulk CMOS devices are described. In Chapter 2, solving Poisson's equation, the boundary model between PD and FD SOI NMOS device, including uniform doped and nonuniform doped are obtained. In Chapter 3, the threshold voltage model considering short channel effect and drain-source voltage effect of bulk dynamic threshold voltage MOS (B-DTMOS) device is obtained first, then, we derived the drain current model in strong inversion region that consider channel length modulation, effective mobility and pre-pinchoff velocity saturation effect. At the end of Chapter 3, the DC and transient behaviors of B-DTMOS inverter and proposed B-DTMOS inverter are simulated and analyzed.
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Tuan, Fu-Yuan, i 段復元. "Discussion on the Leakage Current of Advanced CMOS device". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/36512855547683253188.
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碩士國立臺北科技大學
製造科技研究所
90
In the coming silicon-nano-device generation, the critical gate oxide thickness is getting much thinner than any process generation else before. We can obviously suppose that the gate leakage current would increase exponentially with decreasing gate oxide thickness. In this thesis, a new model “GCIP (Gate Current Induced Punch-through) model “ is proposed and verified by using our experiment results. We pay much attention to the off-state leakage current of the CMOS device especially the current induced around the Source/Drain extension region. This model describes that a high SDE leakage current causes a large amount E-H(electron-hole) pairs. And at the meanwhile, these E-H pair will enlarge the lateral p-n depletion width. This depletion width modulation effect will make the device become much easier to punch-through. This new GCIP model can also be used to verify the MSJZ Model, which proposed by our lab one year ago.
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Kranthi, Nagothu Karmel. "ESD Reliability Physics and Reliability Aware Design of Advanced High Voltage CMOS & Beyond CMOS Devices". Thesis, 2021. https://etd.iisc.ac.in/handle/2005/5474.
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Electrostatic Discharge (ESD) reliability is one of the major reliability concerns in integrated circuits (IC), which if not addressed while designing devices and circuits, can lead to a permanent damage to the Integrated Circuits. The same becomes a rather more stringent in case of system level ESD events (System level ESD), which usually occurs in uncontrolled or harsh environments. To address these issues physical insights into the non-equilibrium electron-phonon (electro-thermal) behaviour of these devices, under nano-second time scale high-current conditions, are required to be developed. These insights are subsequently used to develop reliability aware device. Keeping this larger problem in mind, in this work, we focus on developing physical insights into ESD behaviour of advanced high voltage CMOS/BiCMOS & beyond CMOS device options. Using the physical insights developed, this work also demonstrates using computations and experiment’s reliability aware device design. The thesis/work is divided into following threads:
In the first part of this work, insights into various system level ESD problems in advanced High Voltage CMOS devices is developed. High voltage functionalities are the key for building system on chips (SoC) in mobile and automotive products. However, high voltage LDMOS/DeNMOS devices are prone to early ESD induced damages with charge modulation induced current _laments. To withstand extremely high current levels ( 30 A), during system level ESD events, in lowest possible area footprint, Silicon Controlled Rectifier (SCR) solutions are preferred. SCR can switch from a high voltage blocking state to an ohmic state and conduct high current levels. However, implementing SCR in High voltage LDMOS/DeNMOS technologies presents different challenges. First part of the thesis focuses on three of such major challenges i.e. Power scalability, Window failures when stressed through Common Mode Choke (CMC) and Air discharge failures. Furthermore, HBM and CDM qualified HV-SCR devices have found to cause early failures during system level stress conditions. System level discharges can last longer than HBM & CDM time scales (100ns), SCR should survive for pulse widths > 100ns. In this thesis, a unique low current ESD failures in LDMOS based SCRs during snapback is reported for the first time. Failure is universal to LDMOS-SCR devices designed as an efficient MOS switch and found to be specific to a window of current between trigger and holding state and can only be captured using high resistance load-line in Transmission Line Pulse (TLP) test system. This resulted in severe power scalability issues in LDMOS-SCRs for longer stress durations (Pulse width>100 ns). While using systematic experiments and 3D Technology Computer Aided Design (TCAD) simulations, we have developed detailed physical insights into the low current ESD failure phenomenon in LDMOS-SCR devices. Physical insights developed has resulted in design solutions to avoid low current failure and mitigate power scalability issue without interfering with functional operation and MOS performance. Further, the severity of the power scalability problem with increasing LDMOS voltage classes (from 40V Design to 80V LDMOS) is highlighted with a need for novel design strategies. A systematic design approach is presented to evaluate the effect of different design parameters on LDMOS _lament and SCR turn-on near the snapback region. New design guidelines are presented to improve the power scalability without compromising on its ON-state DC (functional) and Safe Operating Area (SOA) characteristics. On the other hand, signalling at certain high voltage I/Os can go below ground levels. Hence, Bidirectional SCR (BDSCR) protection elements are needed to block high voltage under different stress polarities. Power Scalability of High Voltage BDSCR for long duration pulse discharges (PW >100 ns), is also studied in this thesis. Power scalability trends are found to be sensitive to the Transmission Line Pulse (TLP) measurement set-up. Detailed physical insights into the early formation of current filaments along with filament motion in BDSCR is presented in detail using 3D TCAD. Dynamic current filament motion in Bi-directional high voltage SCRs is found. Back and forth current filament motion is found to improve the power scalability trends in BDSCR devices for long stress durations. Finally, impact of silicide blocking in mitigating filament strength has been studied, which in turn improves the ESD robustness and overall power scalability. The device design and physical understanding from investigations in helped to come-up with a new approach to engineer LDMOS drivers for safe snapback. Proposed method considers engineering both static filament & Dynamic/Moving current filaments in LDMOS design. Dynamic filament motion and its relation to NPN turn-on engineering is studied. A unique window failure in LDMOS near snap-back discussed for the first time in LDMOS designs. The presented approach resulted in 10-time improvement in ESD robustness for self-protecting concepts. Finally, different fundamental questions related to origin of filament motion are explored with the help of engineered LDMOS Designs. Another major challenge in development of HVSCR is, its survival against system level ESD stress through Common Mode Choke (CMC). Some of the communication pins (CAN) in automotive ICs need to pass system level IEC test through choke. CMC is an on-chip component present in ESD stress path. A unique failure mechanism for system level ESD stress through a CM choke is investigated. Presence of choke in stress path is found to change current waveform shape that ESD protection devices experience on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in Drain Extended NMOS SCRs (DeNMOS-SCR). 3D TCAD simulations are used to understand the device behaviour and failure under the peculiar two-pulse shaped IEC current waveform. A novel DeNMOS-SCR design is demonstrated to increases ESD robustness against the peculiar two pulse stimulus and to avoid system level ESD failures. Air discharge failure in HV-SCRs is another major bottleneck in developing on- chip system level protections. High voltage BDSCR devices are found to be vulnerable to system level air discharge failures. The failure observed is sporadic in nature and found to be function of pulse rise time. Root cause for such SCR failure sensitivity to specific rise times is studied in detail using Multi-Finger 3D TCAD Simulations. A novel design solution is prosed to improve BDSCR robustness against the air discharge failures.
Second part of the thesis focuses on understanding ESD device physics of new transistor concepts such as Tunnel FETs and graphene-based FETs. Current as well as the time evolution of the junction breakdown, device turn-ON, voltage snapback, and finally the failure mechanism is studied using both 2-D and 3-D TCAD simulations In Tunnel FETs. The interaction between the band-to-band tunnelling, avalanche multiplication, and thermal carrier generation leading to voltage snapback and failure is presented in detail, along with the electro-thermal instability initiated _lamentation. Impact of various technology and device design parameters on the ESD behavior and robustness of TFETs is discussed. The obtained details will be useful in designing ESD protection concepts in future TFET technologies. Experimental ESD studies on Graphene FETs using matured technology platform are carried out to study the impact of diffusive vs. ballistic carrier transport and top-gate vs. back-gate on failure mechanisms. Insights on current saturation in graphene FET in ESD time scales and a novel step by step failure in dielectric capped transistors is presented. Finally, influence of various top-gate designs on the ESD performance is reported. Safe Operating area boundary definitions in Graphene FETs is also explored. Obtained insights on device failures in these budding technologies, will help in building stronger ESD protection concepts in graphene-based technologies.
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Yueh-Ping, Yu, i 于岳平. "A Novel CMOS Image Sensing Device with High Dynamic Range". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/01352162170585616572.
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碩士國立清華大學
電子工程研究所
92
A high dynamic range pixel has been developed for an active-pixel CMOS image sensor, by using a standard 0.25-µm CMOS logic process. The operation method is the same with conventional 3T pixel cell, and applying a control pulse voltage to photo-gate. The experimental results demonstrate that extended dynamic range is obtained when we delay the pulse voltage to apply to photo-gate, and sensing device design also affects dynamic range. So, the high dynamic range can be approached by optimizing pixel design and photo-gate pulse timing. The imaging sensitivity can be improved through optimizing the PG to PD area ratio and the bias pulse high level. The experimental results demonstrate the pixel can achieve both high sensitivity at low illumination and extended dynamic range for high illumination.
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Wu, Yang-Zheng, i 吳洋政. "A Differential Capacitive Sensing Circuit for CMOS-MEMS pressure device". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/g66e9x.
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碩士國立臺北科技大學
機電整合研究所
100
In this thesis, a new type of capacitor sensor composed of pressure and CMOS circuitry is proposed. The capacitor variation can be measured directly by means of the sensing circuit, which is composed of an impedance amplifier or a switched-capacitor amplifier. The goal of this sensor is to detect various blood vessel pressures. It also provides an effective way in applications of bio-sensors. Furthermore, an array-typed MEMS-Pressure sensor can be to detect blood vessel pressures in various pressure ranges, and it is desired to become a wearable or implantable device. The sensing capacitor range of the proposed sensor is about 1~200 fF. By using readout circuits and comparing the I/O waveforms (in sine wave), we can calculate the capacitor variation of MEMS-Pressure sensor. We converted the Pressure-Sensor output capacitance into a voltage by a convert in this study. The sensing signals are then amplified and readout with instrumentation amplifier (IA) circuit. The proposed system is implemented in TSMC 0.35 μm 2P4M technology. The chip area is roughly 2.500*2.482 with power supply of 3.0V. The input signal is 1 MHz sine waves. The proposed structure has a capacitance measuring range from 1 femto-farad to hundreds of femto-farad. This study successfully presents a smart sensor which can detect a very small capacitance variation of MEMS-Pressure sensor.
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Chang, Chun-Yuan, i 張峻源. "RF CMOS Device Modeling and Broadband Active Inductor Circuit Design". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/43478743279765619045.
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碩士逢甲大學
電機工程學系
89
In the thesis, we present RF CMOS active and passive device modeling and broadband active inductor integrated circuit design. The geometry aspect influence of a spiral inductor on inductance and Q-factor was studied. The methodologies to improve Q-factor were also investigated. RF CMOS integrated circuits were designed using extracted device modeling. In addition, we developed a novel cascode cross-couple negative resistance circuit and applied it to active inductor. The Q-factor of the broadband active inductor can easily attain 10000 by tuning bias voltage of negative resistance circuit. The inductance values of the active inductor can be tuned by scaling transistor size. At 2.5-V supply voltage, the active inductor exhibited excellent performance. The active inductor can be applied to the next generation IC process. Finally, we complete a simple, high Q-factor, high-performance, tunable active filter using the active inductor.
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Lee, Jeng-Hung, i 李政宏. "CMOS Radio Frequency Device Model and High Frequency Power Performance". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/79489309304787717217.
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碩士國立中正大學
電機工程所
95
A research of CMOS BSIM4 DC and RF model parameters and power MOS transistor is investigated in this thesis. In the first part, a set of DC test devices which is fabricated by using TSMC 0.35 μm CMOS technology is designed for the BSIM4 CMOS DC model parameters extraction. It employs eight designs in the test set for measurement that all of the devices are implemented based on the design rule of TSMC 0.35 μm CMOS technology to obtain the reasonable BSIM4 DC model parameters. By the aid of extraction software ICCAP-2006A, the DC model parameters of 0.35 μm CMOS technology were extracted. A single-finger and multi-finger high-frequency devices are used to extract the RF model parameters in the second part. The DC model parameters in the first part will be also included to derive the RF model parameters. Some of calibration kits for de-embedded are used to verify the measured S-parameters and small-signal characteristic. Following the two steps, the BSIM4 RF model parameters will be obtained. The last part is a design of CMOS power cell. There are four devices with different sizes being built up of which are measured by a load-pull system for the output power, efficiency , power gain and the optimal impedance for load and source terminals.
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Lin, Geng-Cing, i 林耕慶. "Device Threshold Voltage Measurement Circuit of Nano-scale CMOS SRAM". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/60550065200696051283.
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碩士國立交通大學
電子研究所
100
Variation issue is one of the key design factors for robust current VLSI systems, and this kind of issue will affect the device threshold voltage (VTH) value. However, the VTH value is still associated with the device performance, stability and reliability, then when we talk about the variation issue that the VTH is the important indicator to reflect this phenomenon. So we want to create a measurement structure that can measure the device threshold voltage, then we can collect the voltage data to realize how the variation issue will affect this testing chip. We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (VTH) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the VTH measurement scheme is about 2-7mV at TT corner across temperature range from 85oC to -45oC, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit.
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Hung-YuChiu i 邱宏裕. "Studies of Novel Processing Technologies for Nano CMOS Device Applications". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/79175923032847322963.
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博士國立成功大學
微電子工程研究所碩博士班
101
This dissertation presents various skills; including a new STI (shallow trench isolation) etch method, small grain size with low temperature polygen process, post-nitridation annealing (PNA) and the carbon co-implant to promote nano CMOS device performances. First, we use automatically top corner rounding (ATCR) STI etch to improve CMOS narrow width device performances. Compared to the conventional methods, the ATCR could increase 8% of the driving current (Idsat) together in a unit process step, thus getting easy process control and cost down benefits. Additionally, the ATCR has a wider process window. Besides, the technique does not degrade the gate oxide integrity, and junction leakage current. Next, we reduce the grain size of poly Si gate by lowering deposition temperature to achieve low sub-threshold leakage and gate leakage. This is due to the smaller grain size can offer a smoother interface to an ultra-thin gate oxide than a big one. Besides, the driving currents are also respectively increased ~9% and ~7% for n- and p- MOSFETs, as the temperatures are lowered from 715oC to 705oC. The most importance is that the small grain size does not degrade the gate oxide integrity and device junction leakage current. Additionally, used a high temperature post-nitridation annealing (PNA) to improve nano devices with pulsed radio frequency decoupled plasma nitrided ultra-thin (〈 50Å) gate dielectric. Results indicate that for a n-type MOSFET, as the PNA temperature rising from 1000oC to 1050oC, the saturation current and gate leakage are increased and reduced 7.9% and 3.81%, respectively. For a p-type MOSFET, the improvement is more significant i.e., 16.7% and 4.31% in saturation current increase and gate leakage reduction, respectively. The significant improvements are attributed to the higher PNA temperature caused Si/SiON interface improvement and increase of EOT. In final, a new molecular carbon co-implant technique was developed. The introduction of carbon ions induces the tensile strain to enhance the mobility. We optimized the dose and energy ranges for both P and C implants along with some anneal parameters to produce low sheet resistance (Rs) and high tensile strain. Besides, Rs measurement, SIMS, XTEM and HRXRD techniques were employed to characterize the doped layer. The optimized implants effectively improved 55nm n-MOSFET performances with Idsat 4.7% gain and significantly reduced transient enhanced diffusion (TED) due to the formation of SiC complex to sink Si interstitials.