Gotowe bibliografie tematyczne / CMOS device

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Gotowa bibliografia na temat „CMOS device”

Autor: Grafiati

Data publikacji: 6 września 2023

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Artykuły w czasopismach na temat "CMOS device"

Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty i Ravikumar Guru Samy. "Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application". Indonesian Journal of Electrical Engineering and Computer Science 28, nr 2 (1.11.2022): 716. http://dx.doi.org/10.11591/ijeecs.v28.i2.pp716-723.

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when compared with Fin Field-Effect Transistor (FinFET) device. The leakage current is more in CMOS devices while in FinFET device due to the control of multi-Gates on the channel, the leakage current is reduced. This will improve the power consumption in the FinFET device when compared to CMOS devices. The comparator results shows that CMOS device is inferior when compared with FinFET device comparator. For the implementation of the comparator Spice model were used in this work. The software used in the project is synopsis Hspice.

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Xiong, Qi, Shao Hua Zhou i Jiang Ping Zeng. "The Analysis of Device Model in CMOS Integrated Temperature Sensor". Advanced Materials Research 986-987 (lipiec 2014): 1600–1605. http://dx.doi.org/10.4028/www.scientific.net/amr.986-987.1600.

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According to the requirement of the CMOS integrated temperature sensor on the device, we analyzed the sub-threshold model of MOS device and the bipolar device under MOS technology. We found the latter is more suitable for a components of CMOS integrated temperature sensor devices. Therefore, we analyzed the influence of the substrate PNP tube’s piezoelectric effect on temperature sensor and compared different types of resistance that lays a theoretical basis for the design of CMOS integrated temperature sensor.

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Chiovetti, Bob. ""Chip Wars" Heat Up On The Digital Imaging Front". Microscopy Today 7, nr 2 (marzec 1999): 3–4. http://dx.doi.org/10.1017/s1551929500063847.

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Although the Charge-Coupled Device (CCD) imaging chip is the standard in today's video and digital cameras, things may change during the coming year. The CCD chip is being challenged by a competing device, the CMOS ("C-moss") chip.CMOS is the most widely used type of integrated circuit for memory and digital processing, virtually everything in computers is CMOS based. The economies of scale and production of CMOS devices are the main reasons why computer prices have continued to drop during the past few years. If a device or an instrument has a microprocessor in it, chances are it includes CMOS technology..

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Shawkat, Mst Shamim Ara, Mohammad Habib Ullah Habib, Md Sakib Hasan, Mohammad Aminul Haque i Nicole McFarlane. "Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes". International Journal of High Speed Electronics and Systems 27, nr 03n04 (wrzesień 2018): 1840018. http://dx.doi.org/10.1142/s0129156418400189.

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A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.

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Wong, Hei. "Abridging CMOS Technology". Nanomaterials 12, nr 23 (29.11.2022): 4245. http://dx.doi.org/10.3390/nano12234245.

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FOSSUM, JERRY G. "A SIMULATION-BASED PREVIEW OF EXTREMELY SCALED DOUBLE-GATE CMOS DEVICES AND CIRCUITS". International Journal of High Speed Electronics and Systems 12, nr 02 (czerwiec 2002): 563–72. http://dx.doi.org/10.1142/s0129156402001460.

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This paper gives a simulation-based preview of device-design issues and performance of extremely scaled DG CMOS. A suite of simulation tools, including a 2D numerical device simulator, a 1D numerical Poisson-Schrödinger solver, and a generic, physics/process-based DG MOSFET compact model in Spice, is applied to both asymmetrical-and symmetrical-gate DG CMOS devices and circuits to provide physical insight at the device and circuit levels. The results give added motivation as well as preliminary guidance for the development of DG CMOS.

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MOONEY, P. M. "MATERIALS FOR STRAINED SILICON DEVICES". International Journal of High Speed Electronics and Systems 12, nr 02 (czerwiec 2002): 305–14. http://dx.doi.org/10.1142/s0129156402001265.

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Strained Si devices exhibit enhanced carrier mobility compared to that of standard Si CMOS devices of the same dimensions. Recent strained Si CMOS device results are reviewed. Materials issues related to the strained Si/relaxed SiGe heterostructures required for a strained Si CMOS technology are discussed.

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Birla, Shilpi, Sudip Mahanti i Neha Singh. "Leakage reduction technique for nano-scaled devices". Circuit World 47, nr 1 (29.05.2020): 97–104. http://dx.doi.org/10.1108/cw-12-2019-0195.

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Purpose The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology. Design/methodology/approach Because of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices. Findings This study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology. Originality/value All the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

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Won, Jongun, Youngchae Roh, Minseung Kang, Yeaji Park, Jaehyeon Kang, Hyeongjun Seo, Changhoon Joe i SangBum Kim. "A Capacitor-Based Synaptic Device with IGZO Access Transistors for Neuromorphic Computing". ECS Transactions 111, nr 2 (19.05.2023): 133–36. http://dx.doi.org/10.1149/11102.0133ecst.

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Analog in-memory computing synaptic devices have been widely studied for efficient implementation of deep learning. As a candidate for a synaptic device, Si-CMOS and capacitor-based synaptic devices have been proposed. However, due to Si-CMOS leakage currents, it is difficult to achieve sufficient retention time. In our research, we verified IGZO TFT with low leakage current and capacitor-based synapses can show linear and symmetric weight update characteristics as well as excellent device variation characteristics. We also verified that IGZO TFT has a leakage current per channel width of 1μm of ~10-17A, which is much lower than the Si-CMOS, resulting in higher accuracy in deep neural network training.

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Tang, L., S. Latif i D. A. B. Miller. "Plasmonic device in silicon CMOS". Electronics Letters 45, nr 13 (2009): 706. http://dx.doi.org/10.1049/el.2009.0839.

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Rozprawy doktorskie na temat "CMOS device"

Rakheja, Shaloo. "Interconnects for post-CMOS devices: physical limits and device and circuit implications". Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45866.

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The objective of this dissertation is to classify the opportunities, advantages, and limits of novel interconnects for post-CMOS logic that can augment or eventually replace the CMOS logic. Post-CMOS devices are envisaged on the idea of using state variables other than the electron charge to store and manipulate information. In the first component of the thesis, a comprehensive analysis of the performance and the energy dissipation of novel logic based on various state variables is conducted, and it is demonstrated that the interconnects will continue to be a major challenge even for post-CMOS logic. The second component of the thesis is focused on the analysis of the interconnection aspects of spin-based logic. This research goal is accomplished through the development of physically-based models of spin-transport parameters for various metallic, semiconducting, and graphene nanoribbon interconnects by incorporating the impact of size effects for narrow cross-sectional dimensions of all-spin logic devices. Due to the generic nature of the models, they can be used in the analysis of spin-based devices to study their functionality and performance more accurately. The compact nature of the models allows them to be easily embedded into the developing CAD tools for spintronic logic. These models then provide the foundation for (i) analyzing the spin injection and transport efficiency in an all-spin logic circuit with various interconnect materials, and (ii) estimating the repeater-insertion requirements in all-spin logic, and (iii) estimating the maximum circuit size for all-spin logic. The research is crucial in pinpointing the implications of the physical limits of novel interconnects at the material, device, circuit, and architecture levels.

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Yu, Chuanzhao. "STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY". Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3551.

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The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices – low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices – from device level to circuit level; The more real voltage stress case – high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future.
Ph.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering

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Jain, Ishita. "Modeling and simulation of self-heating effects in sub-14NM CMOS devices". Thesis, IIT Delhi, 2019. http://eprint.iitd.ac.in:80//handle/2074/8137.

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Wu, Dongping. "Novel concepts for advanced CMOS : Materials, process and device architecture". Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3805.

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The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration.

High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO₂and Al₂O₃as well as their mixtures are investigated assubstitutes for the traditionally used SiO₂in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed.

A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode.

Key words:CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.

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Xu, Chen. "Low voltage CMOS digital imaging architecture with device scaling considerations /". View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20XU.

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Thesis (Ph. D.)--Hong Kong University of Science and Technology, 2004.
Includes bibliographical references (leaves 131-136). Also available in electronic version. Access restricted to campus users.

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Kopalle, Deepika Niu Guofu. "RF linearity analysis in nano scale CMOS using harmonic balance device simulations". Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Fall/Thesis/KOPALLE_DEEPIKA_43.pdf.

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Odanaka, Shinji. "A STUDY OF NUMERICAL PROCESS AND DEVICE MODELING CAD FOR SUBMICROMETER CMOS". Kyoto University, 1990. http://hdl.handle.net/2433/86214.

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Wang, Haihong. "Advanced transport models development for deep submicron low power CMOS device design /". Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.

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HUSSAIN, IZHAR. "TAMTAMS: A web based performance estimation tool from Device to System level for advanced CMOS processes to beyond CMOS technologies". Doctoral thesis, Politecnico di Torino, 2018. http://hdl.handle.net/11583/2710840.

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We presented here a web-based tool, named TAMTAMS that can accurately calculate the IV characteristics of a transistor based technology and estimate the performance evaluation at system level. We have shown how the modular structure of the tool, makes it possible to estimate an electrical quantity, let’s say A, and evaluate further electrical quantities depending on A in a single run of processing. The tree structure and dependence tree enables a user do analysis from a single nano-scale transistor to a system containing hundreds of thousands of transistors. TAMTAMS Web, as a tool, enables the technologist to observe the effect of changes in process parameters (such as doping Nd)at system level. In other words, the changes in device parameters like Vth, Ion, Ioff etc are reflected in changes in system level performance parameters like Static and Dynamic power consumption. We started the development of the tool from BULK transistor technology by translating the physics based mathematical models as Octave scripts. Moving towards more complex structures like SOI, FinFET, Gate-All-Around, Double/Triple Gate transistors and Post-Silicon technologies like Graphene and Molecular transistors. The technology files (physical parameters)are derived from ITRS roadmap. Transistor models for electrical quantities such as drive current Ion, Off-state current Ioff, Gate leakage current Igate, Threshold voltage Vth etc are integrated inside TAMTAMS. We have shown in our results the tunnelling effect in a transistor i-e how change in Oxide thickness Tox , using parametric analysis, affects gate leakage current Igate . This highlights the intensive nature of the analysis performed with TAMTAMS web. We have shown in our results how static and dynamic power consumption of a Vertex 4 FPGA can be compared for BULK, SOI, DG, GAA and molecular transistor-based technologies. This highlights the extensive nature of the analysis performed with the TAMTAMS Web tool. For interconnection and gate level analysis, NAND and NOR are incorporated inside TAMTAMS as universal gates. Different capacitance models are defined and integrated that acts as bridge between transistors based technologies and system level modules like FPGA, Adders, Multipliers, Memories etc. The tool enables Performance estimation at gate level as well e.g we have shown how reliability models predict the increase in Static/Dynamic power consumption and Delay time for NAND/NOR based circuits. TAMTAMS can be used to analyse different applications under many scenarios. For example, at interconnection level, electromigration models enable the comparison of electromigration effect in copper and Aluminium material based interconnection wires. At system level, different system level modules are written and integrated inside TAMTAMS. For example FPGA module, different types of Adder modules, Multipliers, Content Addressable Memory (CAM), Static RAM (SRAM), Arithmetic and Logic unit (ALU), Finite impulse response filters (FIR) etc. We have shown in the analysis, how a static/dynamic power consumption of an Adder and CAM circuit are affected taking reliability issues into consideration using different technologies. Also in the system level analysis, we have compared performance analysis for Virtex 4 FPGA CLB using current and emerging transistor technologies. Time and space does not allow us to discuss all the technologies and all the integrated modules as it is beyond the scope of this work, but we have analysed few interesting case studies in the analysis part. Regarding the development of the tool TAMTAMS Web, we conclude we have achieved enough and have come a long way considering from where we started, but it is still an on-going work as the technology further evolves. Further we conclude that the tool TAMTAMS Web, as presented in this work, can prove vital for i) technologists in analysis of the process variations ii) for designers to evaluate their circuit design at each of the three levels of abstraction, iii) for transistor model developers to benchmark their proposed models with other industry standard models and iv) for the futurists to know what can be predicted in the years to come regarding transistor based circuit.

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Abel, Christopher J. "An investigation of nonideal process and device effects in fundamental CMOS analog subcircuits /". The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487865929454587.

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Książki na temat "CMOS device"

Simon, Deleonibus, red. Electronic device architectures for the nano-CMOS era: From ultimate CMOS scaling to beyond CMOS devices. Singapore: Pan Stanford, 2009.

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Simon, Deleonibus, red. Electronic device architectures for the nano-CMOS era: From ultimate CMOS scaling to beyond CMOS devices. Singapore: Pan Stanford, 2009.

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Incorporated, Advanced Micro Devices. PAL device data book: Bipolar and CMOS. [Sunnyvale, CA]: Advanced Micro Devices Inc., 1990.

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Ytterdal, Trond, Yuhua Cheng i Tor A. Fjeldly. Device Modeling for Analog and RF CMOS Circuit Design. Chichester, UK: John Wiley & Sons, Ltd, 2003. http://dx.doi.org/10.1002/0470863803.

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Device modeling for analog and RF CMOS circuit design. Chichester: John Wiley & Sons, 2004.

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Semenov, Oleg, Hossein Sarbishaei i Manoj Sachdev. ESD Protection Device and Circuit Design for Advanced CMOS Technologies. Dordrecht: Springer Netherlands, 2008. http://dx.doi.org/10.1007/978-1-4020-8301-3.

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Hossein, Sarbishaei, i Sachdev Manoj, red. ESD protection device and circuit design for advanced CMOS technologies. [Dordrecht]: Springer, 2008.

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Madrid, Philip E. Device design and process window analysis of a deep submicron CMOS VLSI technology. Reading, Mass: Addison-Wesley, 1992.

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United States. National Aeronautics and Space Administration., red. Application of linear response theory to experimental data of simultasneous radiation and annealing response of a CMOS device. [Washington, DC: National Aeronautics and Space Administration, 1989.

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L, Helms Harry, red. CMOS devices: 1987 source book. Englewood Cliffs, N.J: Technipubs, 1987.

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Części książek na temat "CMOS device"

Martinez, A., A. Asenov i M. Pala. "NEGF for 3D Device Simulation of Nanometric Inhomogenities". W Nanoscale CMOS, 335–80. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118621523.ch10.

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Grasser, T., R. Strasser, M. Knaipp, K. Tsuneno, H. Masuda i S. Selberherr. "Device Simulator Calibration for Quartermicron CMOS Devices". W Simulation of Semiconductor Processes and Devices 1998, 93–96. Vienna: Springer Vienna, 1998. http://dx.doi.org/10.1007/978-3-7091-6827-1_26.

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Davies, M. S., i P. D. T. O’Connor. "Reliability Assessment of Cmos Asic Designs". W Semiconductor Device Reliability, 137–46. Dordrecht: Springer Netherlands, 1990. http://dx.doi.org/10.1007/978-94-009-2482-6_8.

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Solomon, P. M. "Device Proposals Beyond Silicon CMOS". W Future Trends in Microelectronics, 127–40. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2010. http://dx.doi.org/10.1002/9780470649343.ch10.

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Gharavi, Sam, i Babak Heydari. "mm-Wave Device Modeling". W Ultra High-Speed CMOS Circuits, 5–21. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0305-0_2.

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Gharavi, Sam, i Babak Heydari. "mm-Wave Device Optimization". W Ultra High-Speed CMOS Circuits, 23–34. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0305-0_3.

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Dubois, E., G. Larrieu, R. Valentin, N. Breil i F. Danneville. "Introduction to Schottky-Barrier MOS Architectures: Concept, Challenges, Material Engineering and Device Integration". W Nanoscale CMOS, 157–204. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118621523.ch5.

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Labiod, Samir, Abdelmalek Mouatsi, Zakaria Hadef i Billel Smaani. "Conventional CMOS circuit design". W Device Circuit Co-Design Issues in FETs, 21–56. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003359234-2.

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Salama, Husien, Alain Tshipamba i Khalifa Ahmed. "Modeling for CMOS circuit design". W Device Circuit Co-Design Issues in FETs, 1–20. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003359234-1.

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Cham, Kit Man, Soo-Young Oh, Daeje Chin i John L. Moll. "Transistor Design for Submicron CMOS Technology". W Computer-Aided Design and VLSI Device Development, 171–97. Boston, MA: Springer US, 1986. http://dx.doi.org/10.1007/978-1-4613-2553-6_9.

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Streszczenia konferencji na temat "CMOS device"

Horstmann, Manfred, i Reinhard Mahnkopf. "CMOS Devices - Device/Design Interaction". W 2007 IEEE International Electron Devices Meeting. IEEE, 2007. http://dx.doi.org/10.1109/iedm.2007.4418974.

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Chang, Chih-Sheng, i Akira Hokazono. "CMOS Devices - Advanced Device Structures". W 2007 IEEE International Electron Devices Meeting. IEEE, 2007. http://dx.doi.org/10.1109/iedm.2007.4419091.

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Xiao, Yang, Martin A. Trefzer, Scott Roy, James Alfred Walker, Simon J. Bale i Andy M. Tyrrell. "Circuit optimization using device layout motifs". W 2014 5th European Workshop on CMOS Variability (VARI). IEEE, 2014. http://dx.doi.org/10.1109/vari.2014.6957081.

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Hatakeyama, T., K. Fushinobu i K. Okazaki. "Investigation of Device Interactions Between Two MOSFETs in Si CMOS". W ASME 2008 International Mechanical Engineering Congress and Exposition. ASMEDC, 2008. http://dx.doi.org/10.1115/imece2008-67204.

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Streszczenie:

Experimental works about the device interactions between nMOS and pMOS in bulk Si CMOS were performed. In the bulk Si CMOS, in the case that the distance between two MOSFETs is not enough, it is important to consider the risk of the device interactions between nMOS and pMOS. In this work, we fabricated bulk Si CMOS, in which the distance between pMOS and nMOS can be variable. And we observed the characteristics of the device operation by using fabricated CMOS under the dc bias condition. In this research, we focused on the leakage current between two MOSFETs in CMOS inverter depending on the distance between two MOSFETs, applied voltage and temperature. Experimental results showed that our fabricated CMOS shows quite small leakage current and the leakage current is less than 1% compared to CMOS on state current even with small distance between two MOSFETs at the high voltage condition and the high temperature condition.

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"Silicon CMOS". W 2007 65th Annual Device Research Conference. IEEE, 2007. http://dx.doi.org/10.1109/drc.2007.4373644.

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Tang, Liang, Salman Latif i David A. B. Miller. "Plasmonic device in Si CMOS". W LEOS 2008 - 21st Annual Meeting of the IEEE Lasers and Electro-Optics Society (LEOS 2008). IEEE, 2008. http://dx.doi.org/10.1109/leos.2008.4688527.

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Trivedi, Fossum i Vandooren. "Non-classical CMOS device design". W 2003 IEEE International Conference on Robotics and Automation (Cat No 03CH37422) SOI-03). IEEE, 2003. http://dx.doi.org/10.1109/soi.2003.1242935.

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Sasagawa, Kiyotaka, Makito Haruta, Yasumi Ohta, Hironari Takehara i Jun Ohta. "Implantable Fluorescent CMOS Imaging Device". W 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). IEEE, 2020. http://dx.doi.org/10.1109/edtm47692.2020.9117820.

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Reddy, Anyam Apuroop Kumar, Syed Azeemuddin i M. R. Sayeh. "A CMOS proteretic bistable device". W 2016 IEEE Annual India Conference (INDICON). IEEE, 2016. http://dx.doi.org/10.1109/indicon.2016.7839016.

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"Emerging CMOS devices". W 2016 74th Annual Device Research Conference (DRC). IEEE, 2016. http://dx.doi.org/10.1109/drc.2016.7548398.

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Raporty organizacyjne na temat "CMOS device"

James F. Christian, PhD, i PhD Christopher Stapels. Next-Generation Active Pixel Sensor Device With CMOS APDs. Office of Scientific and Technical Information (OSTI), marzec 2007. http://dx.doi.org/10.2172/900308.

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Smith, J. H., S. Montague, J. J. Sniegowski i J. R. Murray. Characterization of the embedded micromechanical device approach to the monolithic integration of MEMS with CMOS. Office of Scientific and Technical Information (OSTI), październik 1996. http://dx.doi.org/10.2172/380312.

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Brotman, Susan. The Evaluation of Device Model Dependence in the Design of a High-Frequency, Analog, CMOS Transconductance-C Filter. Portland State University Library, styczeń 2000. http://dx.doi.org/10.15760/etd.6585.

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Koga, Rokutaro, i Wojciech A. Kolasinski. Heavy-Ion-Induced Snapback in CMOS Devices. Fort Belvoir, VA: Defense Technical Information Center, sierpień 1990. http://dx.doi.org/10.21236/ada226765.

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Plewa, Matthew I., i Justin Vandenbroucke. Detecting cosmic rays using CMOS sensors in consumer devices. Ames (Iowa): Iowa State University. Library. Digital Press, styczeń 2015. http://dx.doi.org/10.31274/ahac.9757.

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Koh, Seong J., i Choong-Un Kim. Fabrication of Single Electron Devices within the Framework of CMOS Technology. Fort Belvoir, VA: Defense Technical Information Center, grudzień 2008. http://dx.doi.org/10.21236/ada491301.

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Smith, J. H., S. Montague, J. J. Sniegowski i P. J. McWhorter. Embedded micromechanical devices for the monolithic integration of MEMS and CMOS. Office of Scientific and Technical Information (OSTI), lipiec 1995. http://dx.doi.org/10.2172/114489.

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Fonstad, Clifton G. Monolithic Integration of Optoelectronic Devices and Si-CMOS on Gallium Arsenide. Fort Belvoir, VA: Defense Technical Information Center, listopad 2000. http://dx.doi.org/10.21236/ada391141.

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Staple, B. D., H. A. Watts, C. Dyck, A. P. Griego, F. W. Hewlett i J. H. Smith. SPICE Level 3 and BSIM3v3.1 characterization of monolithic integrated CMOS-MEMS devices. Office of Scientific and Technical Information (OSTI), sierpień 1998. http://dx.doi.org/10.2172/663240.

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Koga, R., S. J. Hansel, W. R. Crain, K. B. Crawford, S. D. Pinkerton, J. Quan i M. Maher. Single Event Upset and Latchup Considerations for CMOS Devices Operated at 3.3 Volts. Fort Belvoir, VA: Defense Technical Information Center, styczeń 1998. http://dx.doi.org/10.21236/ada349539.

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