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Rozprawy doktorskie na temat „CMOS applications”

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Data publikacji: 6 września 2023

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1

Carletti, Luca. "Photonique intégrée nonlinéaire sur plate-formes CMOS compatibles pour applications du proche au moyen infrarouge". Thesis, Ecully, Ecole centrale de Lyon, 2015. http://www.theses.fr/2015ECDL0013/document.

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La photonique intégrée offre la possibilité d’exploiter un vaste bouquet de phénomènes optique nonlinéaires pour la génération et le traitement de signaux optiques sur des puces très compactes et à des débits potentiels extrêmement rapides. De nouvelles solutions et technologies de composants pourraient être ainsi réalisées, avec un impact considérable pour les applications télécom et datacom. L’utilisation de phénomènes optiques nonlinéaires (e.g. effet Kerr optique, effet Raman) permet même d’envisager la réalisation de composants actifs (e.g. amplificateurs, modulateurs, lasers, régénérateurs de signaux et convertisseurs en longueur d’onde).Pendant cette dernière décennie, les efforts ont principalement porté sur la plateforme Silicium sur isolant (SOI), profitant du fort confinement optique dans ce matériau, qui permet la miniaturisation et intégration de composants optiques clés (e.g. filtres passifs, jonctions coupleurs et multiplexeurs). Cependant, la présence de fortes pertes nonlinéaires dans ce matériau aux longueurs d’onde d’intérêt (i.e. autour de 1.55 µm dans les télécommunications) limite certaines applications pour lesquelles une forte réponse nonlinéaire est nécessaire et motive la recherche de nouvelles plates-formes, mieux adaptées. L’objectif premier de cette thèse était ainsi l’étude de matériaux alternatifs au Si cristallin, par exemple le silicium amorphe hydrogéné, alliant de très faibles pertes nonlinéaires et une compatibilité CMOS, pour la réalisation de dispositifs photoniques intégrés qui exploitent les phénomènes nonlinéaires. Alternativement, l’utilisation de longueurs d’onde plus élevées (dans le moyen-IR) permet de relaxer la contrainte sur le choix de la filière matériau, en bénéficiant de pertes nonlinéaires réduites, par exemple dans la filière SiGe, également explorée dans cette thèse. Ce travail est organisé de la façon suivante. Le premier chapitre donne un iii panorama des phénomènes nonlinéaires qui permettent de réaliser du traitement tout-optique de l’information, en mettant en évidence les paramètres clés à maitriser (confinement optique, ingénierie de dispersion) pour les composants d’optique intégrée, et en présentant le cadre de modélisation de ces phénomènes utilisé dans le travail de thèse. Il inclut également une revue des démonstrations marquantes publiées sur Silicium cristallin, donnant ainsi des points de référence pour la suite du travail. Le chapitre 2 introduit les cristaux photoniques comme structures d’optique intégrée permettant d’exalter les phénomènes nonlinéaires. On s’intéresse ici aux cavités, avec une démonstration de génération de deuxième et troisième harmoniques qui exploite un design original. Ce chapitre décrit également les enjeux associés à l’utilisation de guides à cristaux photoniques en régime de lumière lente, qui serviront de fondements pour le chapitre 4. Le chapitre 3 présente les résultats de caractérisation de la réponse nonlinéaire associée à des guides réalisés dans deux matériaux alternatifs au silicium cristallin : le silicium amorphe hydrogéné testé dans le proche infrarouge et le silicium germanium testé dans le moyen infrarouge. Le modèle présenté au chapitre 1 est exploité pour déduire la réponse de ces deux matériaux, et il est même étendu pour rendre compte d’effets nonlinéaires d’ordre plus élevé dans le cas du silicium germanium à haute longueur d’onde. Ce chapitre inclut également une discussion sur la comparaison des propriétés nonlinéaires de ces deux matériaux avec le SOI standard. Le chapitre 4 combine l’utilisation d’une plate-forme plus prometteuse que le SOI, avec des structures photoniques plus avancées que les simples guides réfractifs utilisés au chapitre 3 : il décrit l’ingénierie de modes (lents) dans des guides à cristaux photoniques en silicium amorphe hydrogéné et enterrés dans la silice. [...]
Integrated photonics offers a vast choice of nonlinear optical phenomena that could potentially be used for realizing chip-based and cost-effective all-optical signal processing devices that can handle, in principle, optical data signals at very high bit rates. The new components and technological solutions arising from this approach could have a considerable impact for telecom and datacom applications. Nonlinear optical effects (such as the optical Kerr effect or the Raman effect) can be potentially used for realizing active devices (e.g. optical amplifiers, modulators, lasers, signal regenerators and wavelength converters). During the last decade, the silicon on insulator (SOI) platform has known a significant development by exploiting the strong optical confinement, offered by this material platform, which is key for the miniaturization and realization of integrated optical devices (such as passive filters, splitters, junctions and multiplexers). However, the presence of strong nonlinear losses in the standard telecom band (around 1.55 µm) prevents some applications where a strong nonlinear optical response is needed and has motivated the research of more suitable material platforms. The primary goal of this thesis was the study of material alternatives to crystalline silicon (for instance hydrogenated amorphous silicon) with very low nonlinear losses and compatible with the CMOS process in order to realize integrated photonics devices based on nonlinear optical phenomena. Alternatively, the use of longer wavelengths (in the mid-IR) relaxes the constraints on the choice of the material platform, through taking advantage of lower nonlinear losses, for instance on the SiGe platform, which is also explored in this thesis. This work is organized as follows. In the first chapter we provide an overview of the nonlinear optical effects used to realize all optical signal processing functions, focusing on the key parameters that are essential (optical confinement and dispersion engineering) for integrated optical components, and presenting the main models used in this thesis. This chapter also includes a review of the main demonstrations reported on crystalline silicon, to give some benchmarks. Chapter 2 introduces the use of photonic crystals as integrated optical structures that can significantly enhance nonlinear optical phenomena. First we present photonic crystal cavities, with a demonstration of second and third harmonic generation that makes use of an original design. In the second part of the chapter, we describe the main features and challenges associated with photonic crystal waveguides in the slow light regime, which will be used later in chapter 4. In chapter 3, we report the experimental results related to the characterization of the optical nonlinear response of integrated waveguides made of two materials that are alternative to crystalline silicon : the hydrogenated amorphous silicon, probed in the near infrared, and the silicon germanium, probed in the mid-infrared. The model presented in chapter 1 is extensively used here for extracting the nonlinear parameters of these materials and it is also extended to account for higher order nonlinearities in the case of silicon germanium tested at longer wavelengths. This chapter also includes a comparison of the nonlinear properties of these two material platforms with respect to the standard SOI. In chapter 4, we combine the use of a material platform that is better suited than SOI for nonlinear applications with integrated photonics structures that are more advanced that those used in chapter 3. Here we describe the design of (slow) modes in photonic crystal waveguides made in hydrogenated amorphous silicon fully embedded in silica. [...]
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2

ALLEGRI, DANIELE GUIDO. "CMOS-Based Impedance Analyzer for Biomedical Applications". Doctoral thesis, Università degli studi di Pavia, 2017. http://hdl.handle.net/11571/1215968.

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This thesis presents a device which can be used to monitor the hydration level of patients suffering from renal diseases and who are forced to undergo regular dialysis sessions. The system comprises a skin interface and a stimulation and readout circuit. A dimensionless hydration index obtained by performing a bio impedance analysis has been proposed. The proposed device combines the tetra polar multifrequency bio impedance analysis with the 4-electrodes focused impedance measurement approach. Moreover, it combines the lock-in structure with the dual step super-heterodyne demodulation scheme. In contrast to the full analog approach, a mixed analog/digital solution is adopted. In particular, the proposed solution performs a first frequency down conversion in the analog domain and shifts the I,Q demodulation in the digital domain. This solution allows removing any sensible dual path from the analog domain with important benefits in terms of complexity, precision and power consumption. Moreover, with the adopted solution the digital demodulation step is achieved in a very simple and efficient way, without the need of high complexity digital multipliers. We compared the results obtained with a high precision LRC meter with the impedance measurement performed with the new chip and showed a relative error of less than 0.8%. In addition, a FEM model of the thorax tissue has been developed and simulated with the EIDORS toolbox. Simulated results have been compared with in-vivo measurements and we found good accordance between them.
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3

Muhammad, Wasim. "CMOS LNA Design for Multi-Standard Applications". Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7841.

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This thesis discusses design of narrowband low noise amplifiers for multi¬standard applications. The target of this work is to design a low noise ampli¬fier(LNA) for DCS1800 and Bluetooth standard frequency bands. Various designs for narrowband multi-standard LNAs have been studied and a new design for tunable multi-standard LNA has been presented and designed using accumulation mode MOS varactors.

As this design includes on-chip spiral inductors, the design, modelling and layout of on-chip inductors have been discussed briefly. The tool used for this purpose is ASITIC.

Also ESD protection techniques for RF circuits and their effect on LNA per¬formance has been discussed.

Finally fully differential LNA has been designed in O.35um AMS thick metal CMOS process using Cadence SpectreRF. The design also includes ESD pro¬tection at the input of LNA.

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4

Scholvin, Jörg 1976. "Deeply scaled CMOS for RF power applications". Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37904.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
Includes bibliographical references (p. 117-140).
The microelectronics industry is striving to reduce the cost, complexity, and form factor of wireless systems through single-chip integration of analog, RF and digital functions. Driven by the requirements of the digital system components, the 90 nm and 65 nm technology nodes are currently emerging as platforms for highly integrated systems. Achieving such integration while minimizing the cost of adding specialized RF modules places high demands on the base CMOS technology. In this regard, the integration of the power amplifier (PA) function becomes an increasing challenge as technology geometries and supply voltages scale down. Gate length (Lg) scaling yields improved frequency response, promising higher power-added efficiency (PAE), a key RF PA consideration. This benefit comes at the cost of a lower drain voltage, which demands a higher output current and thus wider devices in order to produce a given output power level (Po,,). In this work, we have investigated the potential of deeply scaled CMOS for RF power applications, from 0.25 um down to 65 nm. We demonstrate the frequency and power limitations that the different CMOS technologies face, and describe the physical mechanisms that give rise to these limitations.
(cont.) We find that layout considerations, such as splitting a single large device into many smaller parallel devices, become increasingly important as the technology scales down the roadmap, both for power and frequency. We also show that parasitic resistances associated with the back-end wiring are responsible for placing an upper limit on the RF power that can be obtained for a single bond pad. We demonstrate a power density of 31 mW/mm for the 65 nm node, with PAE in excess of 60% at 4 GHz and 1 V. Similar results are obtained in 90 nm, where a peak PAE of 66% was measured at 2.2 GHz and 1 V, with a power density of 24 mW/mm. We find that efficient integrated PA functionality for many applications can be achieved even in a deeply-scaled logic CMOS technology. For low power levels (below 50 mW), we find that the 65 nm CMOS devices offer excellent efficiency (>50%) over a broad frequency range (2-8 GHz). Their RF power performance approaches that of 90 nm devices both in peak PAE and output power density. This is possible without costly PA-specific add-ons, or the use of higher voltage input-output (I/O) device options.
(cont.) However, since I/O devices are often included as part of the process, they represent a real option for PA integration because they allow for higher power densities. The 0.25 /xm I/O device that is available in the 90 nm process, when biased at Vdd = 2.5 V showed excellent results, with a peak PAE of 60% and an output power of 75 mW (125 mW/mm) at 8 GHz.
by Jörg Scholvin.
Ph.D.
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5

Bardyn, Jean-Paul. "Amplificateurs CMOS faible bruit pour applications sonar". Lille 1, 1990. http://www.theses.fr/1990LIL10167.

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Ce travail a pour but d'évaluer les possibilités d'une intégration monolithique d'amplificateurs à très faible bruit dans une technologie CMOS. Il présente les principales caractéristiques et limitations des dispositifs actifs de cette technologie pour des applications analogiques pointues. En particulier, le bruit 1/F du transistor MOS est caractérisé et modélisé par une approche unifiée valide pour tous les régimes de fonctionnement. Dans le cadre d'applications en acoustique sous-marine, différents critères d'optimisation de l'amplificateur sont évalués. Ils ont été implémentés au sein d'un circuit prototype original de part certains aspects de sa structure. Le niveau de performances atteint par ce circuit nous permet d'envisager le remplacement des actuels circuits hybrides BIFET. Ceci ouvre la perspective d'une intégration monolithique de chaînes en traitement de signal complètes pour des capteurs sonar.
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6

Chao, Yu-Lin. "Germanium channel devices for nanoscale CMOS applications". Diss., Restricted to subscribing institutions, 2008. http://proquest.umi.com/pqdweb?did=1581637981&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.

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7

Czornomaz, Lukas. "Filière technologique hybride InGaAs/SiGe pour applications CMOS". Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT013/document.

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Les materiaux à forte mobilité comme l’InGaAs et le SiGe sont considérés comme des candidats potentiels pour remplacer le Si dans les circuits CMOS futurs. De nombreux défis doivent être surmontés pour transformer ce concept en réalité industrielle. Cette thèse couvre les principaux challenges que sont l’intégration de l’InGaAs sur Si, la formation d’oxydes de grille de qualité, la réalisation de régions source/drain auto-alignées de faible résistance, l’architecture des transistors ou encore la co-intégration de ces matériaux dans un procédé de fabrication CMOS.Les solutions envisagées sont proposées en gardant comme ligne directrice l’applicabilité des méthodes pour une production de grande envergure.Le chapitre 2 aborde l’intégration d’InGaAs sur Si par deux méthodes différentes. Le chapitre3 détaille le développement de modules spécifiques à la fabrication de transistors auto-alignés sur InGaAs. Le chapitre 4 couvre la réalisation de différents types de transistors auto-alignés sur InGaAs dans le but d’améliorer leurs performances. Enfin, le chapitre 5 présente trois méthodes différentes pour réaliser des circuits hybrides CMOS à base d’InGaAs et de SiGe
High-mobility channel materials such as indium-galium-arsenide (InGaAs) and silicon-germanium(SiGe) alloys are considered to be the leading candidates for replacing silicon (Si) in future lowpower complementary metal-oxide-semiconductor (CMOS) circuits. Numerous challenges haveto be tackled in order to turn the high-mobility CMOS concept into an industrial solution. Thisthesis addresses the majors challenges which are the integration of InGaAs on Si, the formationof high-quality gate stacks and self-aligned source and drain (S/D) regions, the optimizationof self-aligned transistors and the co-integration of InGaAs and SiGe into CMOS circuits. Allinvestigated possible solutions are proposed in the framework of very-large-scale integration requirements.Chapter 2 describes two different methods to integrate InGaAs on Si. Chapter 3 detailsthe developments of key process modules for the fabrication of self-aligned InGaAs metal-oxidesemiconductorfield-effect transistors (MOSFETs). Chapter 4 covers the realization of varioustypes of self-aligned MOSFETs towards the improvement of their performance. Finally, chapter5 demonstrates three different methods to make hybrid InGaAs/SiGe CMOS circuits
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8

Dryer, Benjamin James. "Characterisation of CMOS APS technologies for space applications". Thesis, Open University, 2013. http://oro.open.ac.uk/40637/.

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In recent years, the performance of scientific CMOS active pixel sensors has been improved to the point that it is now approaching that of the current silicon sensor of choice, CCDs. For some applications, CMOS APSs is believed to present significant advantages over CCDs, such as improved radiation hardness. In this work, the effect of radiation damage on a ‘baseline’ commercial APS, e2v technologies’ Jade APS, is characterised in response to gamma, proton and heavy ion irradiation. Specific performance problems encountered during this radiation characterisation, such as dark current non-uniformity under gamma irradiation, random telegraph signals under proton irradiation, and single event effects under heavy ion irradiation are described and analyzed. The X-ray spectroscopic imaging performance of the device is measured and compared to the Ocean Colour Imager APS test array showing progress towards a high frame rate spectroscopic X-ray imager for space science. The implications of these results for using similar devices in space applications are considered. Furthermore, possible novel techniques for measuring inter-pixel responsivity non-uniformity, heavy ion detection and spectroscopy, and measuring the dynamics of radiation-induced trap formation are discussed.
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9

Kim, Hyung-Seuk 1976. "Low voltage CMOS frequency synthesizers for RF applications". Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=82607.

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Frequency synthesizers play an important role in modern communications and timing systems. The output of frequency synthesizers may be used as the local oscillator signal in superheterodyne transceivers, or in frequency modulation/demodulation. Fully integrated CMOS RF synthesizers are currently a major research topic. Several publications demonstrated improvements in a variety of aspects such as phase noise, power consumption, and tuning range. However, very low voltage frequency synthesizers are very challenging, since they usually have a limited tuning range and a relatively high phase noise. This research work demonstrates a new architecture to achieve a wide tuning range and low phase noise from a very low voltage supply. The synthesizer is fully integrated in a 0.18 mum CMOS technology covering the 5 GHz WLAN frequency range, requiring only a 1-V power supply. The second part of this thesis consists of the implementation of a 2.4-GHz fractional-N frequency synthesizer to be compatible with two MEMS resonators that resonate at 20-MHz and 70-MHz.
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10

Esteves, J. "La technologie CMOS-MEMS pour des applications acoustiques". Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-01068940.

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Récemment, des travaux montrant la faisabilité des MEMS à base de la technologie CMOS complétée par un micro-usinage en surface sans masque ont été publiés. A la différence de l'approche plus ancienne où la libération des composants MEMS a été faite par une gravure du silicium, la technologie proposée consiste en la gravure des couches d'oxyde afin de libérer les couches métalliques issues de la technologie CMOS. Ce sujet de thèse propose donc de fabriquer des microsystèmes à vocation acoustique à partir d'une technologie CMOS standard : AMS 0.35 μm. Il sera, pour cela, composé de deux parties. Dans la première partie, il s'agit de développer un procédé technologique (déterminer le type de gravure, les temps de gravure, ainsi que les dimensions extrêmes réalisables pour les structures simples en technologie CMOS). En effet, après avoir étudié les différentes possibilités de la technologie CMOS-MEMS proposées dans la littérature, un procédé CMOSMEMS a été mis au point. Ce procédé consiste à graver une couche sacrificielle d'oxyde afin de libérer des microstructures constituées des couches métalliques issues de la technologie CMOS 0.35 μm d'AMS. Le procédé est premièrement testé sur des échantillons contenant des microstructures telles que des ponts et des poutres. La seconde partie du travail est consacrée à la validation du procédé CMOS-MEMS par un développement de structures MEMS acoustiques représentées par un microphone MEMS capacitif. Dans un premier temps, un microphone MEMS capacitif a été réalisé à partir de la technologie CMOS 0.35 μm d'AMS. Après avoir pris connaissance des différents aspects de la technologie CMOS 0.35 μm d'AMS (matériaux, dimensions, règles de dessin,...), une modélisation de microphone MEMS capacitifs est proposée grâce à la réalisation d'un schéma électrique équivalent basé sur les analogies entre les domaines électrique, mécanique et acoustique. Chaque paramètre de ce circuit est déterminé par l'intermédiaire de relations connues et par des logiciels de simulation utilisant la méthode des éléments finis (ANSYS, CoventorWare). Une fois les performances des microphones estimés à partir de ce circuit équivalent, un layout, représentant les différents microphones conçus, a été créé sous Cadence afin d'être envoyé au fondeur AMS. Dès la réception des échantillons, le procédé CMOSMEMS mise en oeuvre précédemment a été appliqué afin de libérer les structures des différents dispositifs. Ensuite, une série de caractérisations a pu être réalisée sur les premiers échantillons. Ces caractérisations visent à déterminer les performances des différents dispositifs fabriqués, mais aussi à estimer les propriétés mécaniques des différentes couches utilisées pour former la structure des microphones. De cette façon, le circuit équivalent pourra être validé ou être amélioré selon les résultats obtenus.
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11

Sidek, Roslina. "Applications of Si/SiGe heterostructures to CMOS devices". Thesis, University of Southampton, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.286957.

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12

Wu, Tan Mau 1979. "Carbon nanotube applications for CMOS back-end processing". Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/30179.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2005.
Includes bibliographical references (p. 73-75).
Carbon nanotubes are a recently discovered material with excellent mechanical, thermal, and electronic properties. In particular, they are potential ballistic transporters and are theorized to have thermal conductivities greater than any other material currently known. In this thesis, we will examine two possible applications of carbon nanotubes in CMOS back-end processing. The first application is as a replacement for copper interconnects. As interconnect line widths shrink, the electrical resistivity of copper will rise dramatically due to surface scattering effects. Carbon nanotube ballistic transporters may be able to overcome this obstacle, as well as being able to withstand current densities much greater than copper. The second application is an enhanced thermal conductivity dielectric for thermal management purposes. Carbon nanotube-oxide composites demonstrate improved thermal characteristics, and integration into CMOS technology may be able to alleviate some of the heat-removal and distribution problems future integrated circuits will face. We will also examine some of the processing techniques that will be necessary for carbon nanotube commercial deployment. Some of the issues we will discuss are nanotube growth, purification, and separation. In addition, we will consider some of the specific issues that need to be addressed for carbon nanotube integration into CMOS back-end technology, such as in situ growth and self-assembly.
by Tan Mau Wu.
S.M.
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13

Kim, Hong-Sun. "2.4GHz CMOS Receivers for short-range wireless applications /". The Ohio State University, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=osu1486399451959422.

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Domingues, Suzana. "CMOS Terahertz Sensors and Circuits for Imaging Applications". Doctoral thesis, Università degli studi di Trento, 2014. https://hdl.handle.net/11572/368174.

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A low-cost THz sensor, with a broadband high responsivity, low noise equivalent power, and capable of working at room temperature is still a challenge. Moreover, sensor integration with signal processing electronics is required in order to realize compact systems to be used in commercial imaging applications. In this thesis, CMOS FET-based THz detectors and with integrated noise-efficient readout circuits are presented as a solution. In an attempt to improve the THz focal plane arrays state of the art, the use of an imager architecture is proposed, where each sensing element of an array can be addressed individually. This architecture provides better system performance in terms of sensitivity, resolution or speed. A first chip was fabricated in the LFoundry 0.15-µm standard CMOS technology containing a 16 x 16 staring imaging array for terahertz detection in the range of 0.8 THz to 1.5 THz. Each pixel is composed of an antenna, a FET detector, and its readout electronics (a current integrator) so as the whole matrix can be integrated simultaneously. The current integrator employs an amplifier with two offset compensation techniques (chopper and current injection) and an output saturation control by adding and subtracting voltages. A second chip composed of 15 test structures was fabricated in the STMicrolectronics 0.13 µm standard CMOS technology for terahertz detection at 600 GHz, 850 GHz and 1.5 THz. This chip contains different FET detectors (transistor and antenna) and switched-capacitor readout circuits that provide both signal amplification and filtering, improving the system SNR after each operation cycle. A comparative study of their performance is done as a first step towards a future array implementation (THz camera). For both chips, electrical and terahertz characterization results of the designed structures are presented and discussed.
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Domingues, Suzana. "CMOS Terahertz Sensors and Circuits for Imaging Applications". Doctoral thesis, University of Trento, 2014. http://eprints-phd.biblio.unitn.it/1233/1/PhD_thesis_Suzana_Domingues_upload.pdf.

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A low-cost THz sensor, with a broadband high responsivity, low noise equivalent power, and capable of working at room temperature is still a challenge. Moreover, sensor integration with signal processing electronics is required in order to realize compact systems to be used in commercial imaging applications. In this thesis, CMOS FET-based THz detectors and with integrated noise-efficient readout circuits are presented as a solution. In an attempt to improve the THz focal plane arrays state of the art, the use of an imager architecture is proposed, where each sensing element of an array can be addressed individually. This architecture provides better system performance in terms of sensitivity, resolution or speed. A first chip was fabricated in the LFoundry 0.15-µm standard CMOS technology containing a 16 x 16 staring imaging array for terahertz detection in the range of 0.8 THz to 1.5 THz. Each pixel is composed of an antenna, a FET detector, and its readout electronics (a current integrator) so as the whole matrix can be integrated simultaneously. The current integrator employs an amplifier with two offset compensation techniques (chopper and current injection) and an output saturation control by adding and subtracting voltages. A second chip composed of 15 test structures was fabricated in the STMicrolectronics 0.13 µm standard CMOS technology for terahertz detection at 600 GHz, 850 GHz and 1.5 THz. This chip contains different FET detectors (transistor and antenna) and switched-capacitor readout circuits that provide both signal amplification and filtering, improving the system SNR after each operation cycle. A comparative study of their performance is done as a first step towards a future array implementation (THz camera). For both chips, electrical and terahertz characterization results of the designed structures are presented and discussed.
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16

Rathore, Pradeep Kumar. "Cmos compatible mems structures for pressure sensing applications". Thesis, IIT Delhi, 2015. http://localhost:8080/iit/handle/2074/6894.

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Jose, Sajay. "Design of RF CMOS Power Amplifier for UWB Applications". Thesis, Virginia Tech, 2004. http://hdl.handle.net/10919/36391.

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Ever since the FCC allocated 7.5 GHz (from 3.1 GHz to 10.6 GHz) for ultra wideband (UWB) technology, interest has been renewed in both academic and industrial circles to exploit this vast spectrum for short range, high data rate wireless applications. The great potential of UWB lies in the fact that it can co-exist with the already licensed spectrum users and can still pave the way for a wide range of applications. However, this wide bandwidth complicates the circuit level implementation of key RF blocks like the power amplifier (PA), transmit/receive switch, low noise amplifier (LNA) and mixers in an UWB transceiver. Though expensive technologies like SiGe or GaAs have been used for transceiver realizations, the ultimate goal is to have a single-chip, low-cost solution which can only be achieved by using CMOS technology. Nevertheless, some of the inherent limitations of CMOS like lower fT of transistors make the design of UWB circuits in CMOS an extremely challenging task. Two proposals- Multi-Band OFDM and Direct-Sequence CDMA have been put before the IEEE 802.15.3a task group to decide on the industry standard for the commercial deployment of this technology. Though the debate on which standard is better has not been resolved, proponents of both the groups have already begun to develop prototypes of their respective proposals. This thesis describes the design of a key RF block in the UWB transceiver - the Power Amplifier. For the first part of this work, a PA suitable for MB-OFDM specifications was designed and fabricated in TSMC 0.18um CMOS technology. The class-AB PA is able to cover the lower UWB frequency band from 3.1 GHz to 4.75 GHz and delivers an output power of -2 dBm at 4 GHz. Simulated results show a gain of 19±2 dB achieved over the entire band and the PA consumes 36.54 mW from a 1.8V supply. In the second part of this work, a PA that meets the DS-CDMA specifications was designed and fabricated. This PA operates in the class-AB regime, delivering an output power of -4.2 dBm with input-1dB compression point at -22 dBm. Complete design and implementation was done using TSMC 0.18um CMOS technology and it consumes a very low power of 25 mW, while realizing a flat gain of 19±1 dB across the whole band of operation. All the above mentioned results are from simulations in SpectreRF and measurements are yet to be taken. Additional features like power ON/OFF scheme and output impedance control has also been incorporated in the design.
Master of Science
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18

Barbier, R. "Du photon unique aux applications". Habilitation à diriger des recherches, Université Claude Bernard - Lyon I, 2012. http://tel.archives-ouvertes.fr/tel-00748508.

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19

Lau, Ming Cheung. "A wide-band CMOS synthesizer for cable tuner applications /". View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20LAU.

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20

Park, Jongmin. "CMOS analog spectrum processing techniques for cognitive radio applications". Diss., Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/37230.

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The objective of the research is to develop analog spectrum processing techniques for cognitive radio (CR) applications in CMOS technology. CR systems aim to use the unoccupied spectrum allocations without any license when the primary users are not present. Therefore, the successful deployment of CR systems relies on their ability to accurately sense the spectrum usage status over a wide frequency range serving various wireless communication standards. Meanwhile, to maximize the utilization of the available spectrum segments, the bandwidth of the signal has to be highly flexible, so that even a small fraction of spectrum resources can be fully utilized by CR users. One of the key enabling technologies of variable bandwidth communication is a tunable baseband filter. In this research, a reconfigurable CR testbed system is presented as groundwork for the researches related with CR systems. With the feasibility study on the multi-resolution spectrum sensing (MRSS) functionality, a method for determining sensing threshold for MRSS functionality is presented, and a fully integrated MRSS receiver in CMOS technology is demonstrated. On the other hand, a reconfigurable CMOS analog baseband filter which can change its bandwidth, type and order with high resolution for CR applications is presented. In sum, an analog spectrum sensing method as well as a highly flexible analog baseband filter architecture is established and implemented in CMOS technology. Both designs are targeting the utilization of the analog signal processing capability with the aid of the digital circuits.
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21

Musayev, Javid. "Cmos Integrated Sensor Readout Circuitry For Dna Detection Applications". Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12613645/index.pdf.

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This study presents a CMOS integrated sensor chip suitable for sensing biological samples like DNA. The sensing part of the chip consists of a 32 X 32 pixel array with a 15 µ
m pixel pitch. Pixels have 5 µ
m X 5 µ
m detector electrodes implemented with the top metal of the CMOS process, and they are capable of detecting charge transferred or induced on those electrodes with a very high sensitivity. This study also includes development of an external electronics containing ADC for analog to digital data conversion. This external circuitry is implemented on a PCB compatible with the Opal Kelly XM3010 FPGA that provides data storage and transfer to PC. The measured noise of the overall system is 6.7 e- (electrons), which can be shrunk down to even 5.1 e- with an over sampling rate. This kind of sensitivity performance is very suitable for DNA detection, as a single nucleotide of a DNA contains 1 or 2 e- and as 10 to 20 base pair long DNA&rsquo
s are usually used in microarray applications. The measured dynamic range of the system is 71 dB, in other words, at most 24603 e- per frame (20 ms) can be detected. The measured leakage is 31 e-/frame, but this does not have a dramatic effect on the sensitivity of the system, noting that the leakage is a predictable quantity. DNA detection tests are performed with the chip in addition to electronic performance measurements. The surface of the chip is covered with a nitride passivation layer to prevent the pixel crosstalk and is modified with an APTES polymer for suitable DNA immobilization. DNA immobilization and hybridization tests are performed with 5&rsquo
-TCTCACCTTC-3&rsquo
probe and its complementary 3&rsquo
-AGAGTGGAAG-5&rsquo
target sequences. Hybridization performed in 1 pM solution is shown to have a larger steady state leakage than the immobilization in a 13 µ
M solution, implying the ability to differentiate between the full match and full mismatch sequences. To best of our knowledge, the measured pM sensitivity has not yet been reported with any label free CMOS DNA microarrays in literature, and it is comparable with the sensitivity of techniques like QCM or the fluorescence imaging. The 1 pM sensitivity is not a theoretical limit of the sensor, since theoretically the sensitivity level of 6.7 e- can offer much better results, down to the aM level, as far as the noise of electronics is considered, nevertheless the sensitivity is expected to be limited by DNA immobilization and hybridization probabilities which are determined by the surface modification technique and applied protocol. Improving those can lead to much smaller detection limits, such as aM level as stated above.
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22

Ye, Song. "1 V, 1.9 GHz CMOS mixers for wireless applications". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ58802.pdf.

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23

Cappellani, Annalisa. "Metal gate integration in CMOS logic for RF applications". Thesis, University of Newcastle Upon Tyne, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.366569.

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24

Heymes, Julian. "Depletion of CMOS pixel sensors : studies, characterization, and applications". Thesis, Strasbourg, 2018. http://www.theses.fr/2018STRAE010/document.

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Une architecture de capteurs à pixels CMOS permettant la désertion du volume sensible par polarisation via la face avant du circuit est étudiée à travers la caractérisation en laboratoire d’un capteur prototype. Les performances de collection de charge confirment la désertion d‘une grande partie de l’épaisseur sensible. De plus, le bruit de lecture restant modeste, le capteur présente une excellente résolution en énergie pour les photons en dessous de 20 keV à des températures positives. Ces résultats soulignent l’intérêt de cette architecture pour la spectroscopie des rayons X mous et pour la trajectométrie des particules chargées en milieu très radiatif. La profondeur sur laquelle le capteur est déserté est prédite par un modèle analytique simplifié et par des calculs par éléments finis. Une méthode d’évaluation de cette profondeur par mesure indirecte est proposée. Les mesures corroborent les prédictions concernant un substrat fin, très résistif, qui est intégralement déserté et un substrat moins résistif et mesurant 40 micromètres, qui est partiellement déserté sur 18 micromètres mais détecte correctement sur la totalité de l’épaisseur. Deux développements de capteurs destinés à l’imagerie X et à la neuro-imagerie intracérébrale sur des rats éveillés et libres de leurs mouvements sont présentés
An architecture of CMOS pixel sensor allowing the depletion of the sensitive volume through frontside biasing is studied through the characterization in laboratory of a prototype. The charge collection performances confirm the depletion of a large part of the sensitive thickness. In addition, with a modest noise level, the sensor features an excellent energy resolution for photons below 20 keV at positive temperatures. These results demonstrate that such sensors are suited for soft X-ray spectroscopy and for charged particle tracking in highly radiative environment. A simplified analytical model and finite elements calculus are used to predict the depletion depth reached. An indirect measurement method to evaluate this depth is proposed. Measurements confirm predictions for a thin highly resistive epitaxial layer, which is fully depleted, and a 40micrometers thick bulk less resistive substrate, for which depletion reached 18 micrometers but which still offers correct detection over its full depth. Two sensor designs dedicated to X-ray imaging and in-brain neuroimaging on awake and freely moving rats are presented
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25

Neshatvar, N. "A novel wideband CMOS current driver for bioimpedance applications". Thesis, University College London (University of London), 2017. http://discovery.ucl.ac.uk/1546168/.

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The variation of tissue’s electrical properties, both dielectric and conductive characteristics, through a frequency spectrum is characterised as bioimpedance spectroscopy. In electrical impedance spectroscopy (EIS) of biological tissues, the overall impedance measurement is performed by applying AC signals, either a current signal or a voltage signal, to the surface of the tissue or cell via one pair of electrodes and recording the resulting signals via a separate or the same pair, which are then converted to impedance via a demodulation process. Considering current stimulus, a wide band current driver up to 3 MHz is desired so that it can penetrate to the nucleolus of the cell and provide accurate information about the morphology and physiology of the cell. This thesis intended to design a novel wide band current driver with phase compensation scheme for tetra-polar EIS applications. It presented the measurement result and experimental validation of the proposed current driver which provide superior performance to the existing state of the art current drivers in terms of bandwidth, output impedance and phase error. The integrated fully differential non-linear feedback current driver is fabricated in 0.35 μm CMOS technology and occupies a silicon area of 1.2 mm2 . With the introduction of automatic phase compensation circuit, the current driver is able to operate at frequencies close to the pole frequency of the output transconductor with phase errors as low as 3o at 3 MHz Frequency. Another important aspect of the phase compensation is that the output impedance of the current driver remains (largely) constant throughout the entire range of operational frequencies (100 kHz – 3 MHz). The current driver can deliver a maximum output current of 1.8 mAp-p from a supply of ± 2.5 V. For an output current of 1 mAp-p the accuracy is 0.24%, 0.43% at 1 and 2 MHz respectively. With active compensation, the phase error at the output of the current driver reduces to 1o at 1 MHz and 3o at 3MHz. The current driver can be configured to operate with multi-frequency (multi-sine) by connecting in parallel extra current drivers (with their corresponding phase compensation).
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26

Wang, Ching-Chun 1969. "A study of CMOS technologies for image sensor applications". Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/8214.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
Includes bibliographical references (p. 179-183).
CMOS (Complementary Metal-Oxide-Silicon) imager technology, as compared with mature CCD (Charge-Coupled Device) imager technology, has the advantages of higher circuit integration, lower power consumption, and potentially lower price. The advantages make this technology competent for the next-generation solid-state imaging applications. However, CMOS processes are originally developed for high-performance digital circuits. Fabricating high-quality embedded image sensors with CMOS technologies is not a straightforward task. This motivates the study of CMOS technologies for imaging applications presented in this thesis. The major content of this study can be partitioned into four parts: (a) A two-stage characterization methodology is developed for sensor optimization, including the characterization of large-area photodiodes and comparative analyses on small-dimension sensor arrays with various pixel structures, junction types of the sensors, and other process-related conditions. (b) The mechanism of hot-carrier induced excess minority carriers occurred at the in-pixel transistors is identified and investigated. The influence of the excess carriers on imager performance is analyzed. Suggestions on the pixel design are provided. (c) Signal cross-talk between adjacent pixels is quantified and studied using a sensor array with a specially designed metal shield pattern, which exposes the center pixel and covers the others. The influence of cross-talk on color imager performance is analyzed. Process and layout improvements on cross-talk are also proposed. (d) The trend of pixel size reduction is investigated from the perspective of the achievable optical lens resolution. Using the modulation transfer function (MTF) as an index, optical simulations are performed to examine the relation between the lens resolution and the lens complexity.
by Ching-Chun Wang.
Ph.D.
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27

Rushton, Joseph Edward. "Radiation damage in CMOS image sensors for space applications". Thesis, Open University, 2018. http://oro.open.ac.uk/53005/.

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The space radiation environment is damaging to silicon devices, such as Complementary Metal Oxide Semiconductor (CMOS) image sensors, affecting their performance over time or causing total failure. The first part of this work investigates a Charge Coupled Device (CCD) style CMOS image sensor designed for TDI (Time Delay and Integration) mode imaging, a mode commonly used for Earth observation. Damage from high energy protons in the space environment decreases the Charge Transfer Efficiency (CTE) and increases the dark current of such devices. Experimental work on proton damaged devices is presented, showing the effects on CTE and dark current. The results are compared to a standard CCD by a simulation to take into account the different dimensions and operating conditions of the two devices. The second part of this work describes an experimental campaign to determine the effects of process variations (namely the introduction of deep doping wells and the variation of epitaxial silicon thickness) on the rate of Single Event Latchup (SEL) in CMOS Active Pixel Sensor (APS) devices. SEL is a potentially destructive phenomenon which occurs in CMOS technology but not in CCDs. Test devices were subjected to heavy ion bombardement and SEL rates recorded for a range of heavy ions causing varying amounts of ionisation. A simulation using Technology Computer Aided Design (TCAD) was developed to predict the SEL rates due to heavy ions and to understand the characteristic shape of the SEL cross section vs. Linear Energy Transfer (LET) curves produced by SEL experiments. The simuation was carried out for structures representative of each of the design variants.
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28

Caicedo, Jhon Alexander Gomez. "CMOS low-power threshold voltage monitors circuits and applications". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/144080.

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Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap.
A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.
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29

Martins, Mayler Gama Alvarenga. "Applications of functional composition for CMOS and emerging technologies". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/164452.

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Os avanços da indústria de semicondutores nas últimas décadas foram baseados fortemente na contínua redução de tamanho dos dispositivos CMOS fabricados. Os usos de dispositivos CMOS dependem profundamente da lógica de portas E/OU/INV. À medida que os dispositivos CMOS estão atingindo oslimites fisicos, pesquisadores aumento esforço para prolongar a vida útil da tecnologia CMOS. Também é necessário investigar dispositivos alternativos, que em muitos casos implicam no uso de operações lógicas básicas diferentes. Como as ferramentas comerciais de síntese não são capazes de manipular eficientemente estas tecnologias Esta tese de doutorado foca em produzir algoritmos eficientes para projeto de circuitos tanto em CMOS quanto em novas tecnologias, integrando estes algorithmos em fluxos de projeto. Para esta tarefa, aplicamos a técnica da composição functional, para sintetizar eficiente tanto em CMOS quanto em tecnologias emergentes. A composição funcional é uma abordagem de síntese de baixo para cima, provendo flexibilidade para implementar algoritmos com resultados ótimos ou sub-ótimos para diferentes tecnologias. A fim de investigar como a composição funcional se compara às abordagens de síntese estado-da-arte, propomos aplicar esse paradigma de síntese em seis cenários diferentes. Dois deles se concentram em circuitos baseados em CMOS e outros quatro em circuitos baseados em tecnologias emergentes. Em relação a circuitos baseados em CMOS, investigamos a composição funcional para fatoração de funções multi-saídas, aplicadas em um fluxo de resíntese. Também manipulamos funções aproximadas, a fim de sintetizar módulos de redundância tripla aproximada. No que diz respeito as tecnologias emergentes, exploramos a composição funcional através de diodos spintrônicos e outras abordagens promissoras com base em diferentes implementações de lógica: a lógica de limiar, lógica majoritária e lógica de implicação. Resultados apresentam uma melhoria considerável em relação aos métodos estadoda- arte tanto para aplicações CMOS quanto aplicações de tecnologias emergentes, demonstrando a capacidade de lidar com diferentes tecnologias e mostrando a possibilidade de melhorar tecnologias ainda não exploradas.
The advances in semiconductor industry over the last decades have been strongly based on continuous scaling down of dimensions in manufactured CMOS devices. The use of CMOS devices profoundly relies on AND/OR/Inverter logic. As the CMOS scaling is reaching its physical limits, researchers increase the effort to prolong the CMOS life. Also, it is necessary to investigate alternative devices, which in many cases implies the use of different basic logic operations. As the commercial synthesis tools are not able to handle these technologies efficiently, there is an opportunity to research alternative logic implementations better suited for these new devices. This thesis focuses on presenting efficient algorithms to design circuits in both CMOS and new technologies while integrating these algorithms into regular design flows. For this task, we apply the functional composition technique, to efficiently synthesize both CMOS and emerging technologies. The functional composition is a bottom-up synthesis approach, providing flexibility to implement algorithms with optimal or suboptimal results for different technologies. To investigate how the functional composition compares to the state-of-the-art synthesis methods, we propose to apply this synthesis paradigm into six different scenarios. Two of them focus on CMOS-based circuits, and other four are based on emerging technologies. Regarding CMOSbased circuits, we investigate functional composition to investigate multi-output factorization in a circuit resynthesis flow. Also, we manipulate approximate functions to synthesize approximate triple modular redundancy (ATMR) modules. Concerning emerging technologies, we explore functional composition over spin-diode circuits and other promising approaches based on different logic implementations: threshold logic, majority logic, and implication logic. Results present a considerable improvement over the state-of-the-art methods for both CMOS and emerging technologies applications, demonstrating the ability to handle different technologies and showing the possibility to improve technologies not explored yet.
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30

Sanyal, Alarka. "CMOS Phase Shifter for Conformal Phased Array Beamformer Applications". Thesis, North Dakota State University, 2015. https://hdl.handle.net/10365/27697.

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A vector modulator based phase shifter is developed using 0.18um CMOS process at S-band frequency to be integrated into a conformal phased array antenna to recover the desired radiation pattern in the entire 360? range. The phase shifter has a variable gain amplifier integrated into the circuit in order to vary gain along with phase for precise control to correct the degraded radiation pattern due to the conformal shaping. The results show state-of-the-art performances including more than 7dB conversion gain with variable feature, a continuous phase rotation of 360? with steps as low as 11.25? and very low power consumption of 17mW, for the first time to the best of the authors? knowledge. The chip size including all pads is 1.5mm X 0.75mm.
ND NASA EPSCoR (Agreement FAR0020852)
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31

Reidel, Claire-Anne. "Applications for CMOS pixel sensors in ion-beam therapy". Thesis, Strasbourg, 2020. https://publication-theses.unistra.fr/public/theses_doctorat/2020/REIDEL_Claire-Anne_2020_ED182.pdf.

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En hadronthérapie, des mesures de haute précision sont essentielles pour avoir une base de données robuste et délivrer le traitement prescrit au patient. Dans ce travail, un système de trajectométrie, composé de capteurs à pixels MIMOSA-28, a été utilisé pour différentes applications cliniques. Plusieurs améliorations ont été implémentées au niveau matériel et logiciel résultant à une résolution spatiale de trace < 10 μm. Les expériences ont été menées avec succès dans différents centres médicaux et de recherche. Les profils de faisceaux ont été mesurés et la largeur du faisceau le long de l'axe a pu être calculée grâce à un code de transport basé sur la diffusion. Un outil en ligne de suivi de faisceau a été développé pour avoir une information rapide de son profil. D'autre part, les perturbations de la fluence dues à des marqueurs de repères pour un faisceau 12C ont été évaluées. Après reconstruction et extrapolation de chaque trace, une distribution 3D de la fluence a pu être établie et la perturbation maximale de la fluence et sa position ont pu être quantifiées. Les points froids mesurés varient entre moins de 3% à 9.2% pour un marqueur et une énergie de faisceau définis
In ion-beam therapy, high precision measurements are essential for having robust basic data to deliver the prescribed treatment to the patient. In this study, MIMOSA-28 pixel sensors were used as a tracker system for different medical applications. Several hardware and software improvements were implemented leading to a spatial track resolution < 10 μm. The experiments were conducted with success in different medical and research facilities. In this work, beam profiles were measured along the beam axis and the width of the beam along the axis could be calculated with a transportation code based on multiple Coulomb scattering. Moreover, an online beam monitoring was developed in order to have fast information about the beam profile. In another study, the fluence perturbation of 12C ion beams due to small fiducial markers was investigated. After reconstruction and extrapolation of single track, a 3D fluence distribution could be performed and the maximum perturbation and its position along the beam axis could be quantified. In this work, the measured cold spot varied between less than 3% up to 9.2% for a defined marker and a defined primary energy beam
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32

Ho, Ka Wai. "A 1-V CMOS power amplifier for Bluetooth applications /". View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20HO.

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33

CICIOTTI, FULVIO. "Oscillator-Based CMOS Readout Interfaces for Gas Sensing Applications". Doctoral thesis, Università degli Studi di Milano-Bicocca, 2019. http://hdl.handle.net/10281/241089.

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Il rilevamento di gas tossici e pericolosi è sempre stato necessario per motivi di sicurezza. Negli ultimi anni, in particolare, l’attenzione per lo sviluppo di sistemi portatili e a basso costo per il rilevamento dei gas è aumentata notevolmente. Questa tesi presenta circuiti CMOS versatili, veloci, ad alta precisione e basso consumo per applicazioni portatili di rilevamento di gas. I sensori target sono i Metal Oxide Semiconductor (MOX). Questi sensori sono ampiamente utilizzati per la loro intrinseca compatibilità con le tecnologie MEMS integrate. Le tipologie di lettura scelte sono basate su un oscillatore controllato dalla resistenza del sensore stessa, in modo da ottenere una conversione resistenza-tempo. Ciò garantisce un ampio range dinamico, una buona precisione e la capacità di far fronte alle grandi variazioni di resistenza del sensore MOX. Quattro diversi prototipi sono stati sviluppati e testati con successo. Sono state anche eseguite misurazioni chimiche con un vero sensore SnO2 MOX, validando i risultati ottenuti. Le misure hanno mostrato come il sensore e l’interfaccia sia in grado di rilevare fino a 5ppm di CO in aria. Gli ASIC sono in grado di coprire 128 dB di DR a 4Hz di output data rate digitale, o 148 dB a 0.4Hz, garantendo un errore relativo percentuale sempre migliore dello 0,4% (SNDR> 48 dB). Le prestazioni target sono state raggiunte con aggressive strategie di progettazione e ottimizzazione a livello di sistema. È stata utilizzata una tecnologia CMOS a 130nm fornita da Infineon Technologies AG. La scelta di un nodo tecnologico così scalato (rispetto alle tipiche implementazioni in questo settore) ha consentito di ridurre ulteriormente i consumi fino a circa 450 μA. Inoltre, questo lavoro introduce la possibilità di utilizzare la stessa architettura basata su oscillatore per eseguire la lettura di sensori capacitivi. I risultati delle misurazioni con sensori capacitivi MEMS hanno mostrato 116 dB di DR, con un SNR di 74 dB a 10Hz di velocità di trasmissione dati digitale. Le architetture sviluppate in questa tesi sono compatibili con gli standard moderni nel settore del rilevamento del gas per dispositivi portatili.
Detection of toxic and dangerous gases has always been a need for safety purpose and, in recent years, portable and low-cost gas sensing systems are becoming of main interest. This thesis presents fast, high precision, low-power, versatile CMOS interface circuits for portable gas sensing applications. The target sensors are Metal Oxide Semiconductor (MOX) sensors which are widely used due to their inherent compatibility with integrated MEMS technologies. The chosen readout typologies are based on the time-domain Resistor-Controlled Oscillator. This guarantees wide dynamic range, good precision and the ability to cope with the large MOX sensor resistance variations. Four different prototypes have been successfully developed and tested. Chemical measurements with a real SnO2 MOX sensor have also been performed to validate the results, showing a minimum CO detection capability in ambient air of 5 ppm. The ASICs are able to cover 128 dB of DR at 4 Hz of digital output data rate, or 148 dB at 0.4 Hz, while providing a relative error always better than 0.4% (SNDR >48 dB). Target performances have been achieved with aggressive design strategies and system-level optimization, and using a scaled (compared to typical implementations in this field) 130nm CMOS technology provided by Infineon Technologies AG. Power consumption is about 450 μA. Moreover, this work introduces the possibility to use the same oscillator-based architecture to perform capacitive sensors readout. Measurement results with capacitive MEMS sensors have shown 116 dB of DR in CSENS mode, with an SNR of 74 dB at 10 Hz of digital output data rate. The architectures developed in this thesis are compatible with the modern standards in the portable gas sensing industry.
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34

Chen, Jau-Horng. "Wideband Dynamic Biasing of Power Amplifiers for Wireless Handheld Applications". Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11554.

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The objective of the proposed research is to extend the battery life in cellular handsets by improving the transmitter efficiency. Bandwidth efficient modulation formats, such as W-CDMA, encode much of the information in amplitude modulation. Therefore, linear transmitters must be used so as not to increase transmission errors, and cause interference in adjacent bands. Various engineering trade-offs were examined to find a suitable transmitter architecture for W-CDMA. Dynamic biasing of the transmitter power amplifier (PA) provides a simple way to improve efficiency for applications that require highly linear amplification. The envelope elimination and restoration (EER) PA or EER-based polar-modulated PA is an attractive solution since it has potential to achieve very high efficiency with high linearity. However, the major impediment to EER implementation has been the lack of power-efficient dynamic power supply circuits that can operate with sufficient modulation bandwidth, and simultaneously achieve the required modulation linearity. This work proposes several solutions to this problem. First, a dynamic supply circuit using delta modulation was designed and implemented. An open-loop EER PA with 48% peak efficiency was constructed and tested with a cellular band IS-95 CDMA signal with a bandwidth of 1.25 MHz. The low switching loss by using a delta modulator made the implementation of a wideband dynamic biasing circuit possible. Second, a dynamic supply circuit using dual-phase PWM was designed and implemented to achieve wider bandwidth, lower noise, and higher efficiency. An open-loop EER PA was implemented with the dynamic supply IC. A digital gain compensation scheme was developed to further increase bandwidth and linearity. This enables a dynamic supply circuit with lower switching frequency to have larger usable bandwidth with little increased power consumption. A cellular band W-CDMA voice signal was used to evaluate the performance of the overall PA. The PA achieved 50% efficiency while passing all required spectral specifications of W-CDMA standard. To increase the inherent low dynamic range of an EER PA, a dual-mode power amplifier combining an EER PA and power-level tracking PA was proposed. This work will contribute to the development of high efficiency, small-sized multi-mode linear PAs for battery-operated wireless handheld devices.
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35

Mattia, Neto Oscar Elisio. "NanoWatt resistorless CMOS voltage references for Sub-1 V applications". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/107131.

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Referências de tensão integradas sempre foram um bloco fundamental de qualquer sistema eletrônico e um importante tópico de pesquisa que tem sido estudado extensivamente nos últimos 50 anos. Uma tensão de referência é um circuito que provê uma tensão estável com baixa sensibilidade a variações em temperatura, alimentação, carga, características do processo de fabricação e tensões mecânicas de encapsulamento. Elas são normalmente implementadas através da soma ponderada de dois fenômenos físicos diferentes, com comportamentos em temperatura opostos. Normalmente, a tensão térmica, relacionada à constante de Boltzmann e à carga do elétron, fornece uma dependência positiva com temperatura, enquanto que a tensão base-emissor VBE de um transistor bipolar ou a tensão de limiar de um MOSFET fornece o termo complementar. Um bloco auxiliar é às vezes utilizado para fornecer as correntes de polarização do circuito, e outros blocos adicionais implementam a soma ponderada. A evolução da tecnologia de processos é o principal fator para aplicações em baixa tensão, enquanto que a emergência de dispositivos portáteis operados a bateria, circuitos biomédicos implantáveis e dispostivos de captura de energia do ambiente restringem cada circuito a consumir o mínimo possivel. Portanto, alimentações abaixo de 1 V e consumos na ordem de nanoWatts se tornaram características fundamentais de tais circuitos. Contudo, existem diversos desafios ao projetar referências de tensão de alta exatidão em processos CMOS modernos sob essas condições. As topologias tradicionais não são adequadas pois elas provêm uma referência de tensão acima de 1 V, e requerem resistências da ordem de G para atingir tão baixo consumo de potência, ocupando assim uma grande área de silício. Avanços recentes atingiram tais níveis de consumo de potência, porém com limitada exatidão, custosos procedimentos de calibração e grande área ocupada em silício. Nesta dissertação apresentam-se duas novas topologias de circuitos: uma tensão de junção bipolar com compensação de curvatura que não utiliza resistores e é auto-polarizada; e um circuito de referência bandgap sem resistores que opera abaixo de 1 V (também chamado de sub-bandgap). Ambos circuitos operam com consumo na ordem de nanoWatts e ocupam pequenas áreas de silício. Resultados de simulação para dois processos diferentes, 180 nm e 130 nm, e resultados experimentais de uma rodada de fabricação em 130 nm apresentam melhorias sobre tais limitações, mantendo as características desejadas de não conter resistores, ultra baixo consumo, baixa tensão de alimentação e áreas muito pequenas.
Integrated voltage references have always been a fundamental block of any electronic system, and an important research topic that has been extensively studied in the past 50 years. A voltage reference is a circuit that provides a stable voltage with low sensitivity to variations in temperature, supply, load, process characteristics and packaging stresses. They are usually implemented through the weighted sum of two independent physical phenomena with opposite temperature dependencies. Usually the thermal voltage, related to the Boltzmann’s constant and the electron charge, provides a positive temperature dependence, while the silicon bandgap voltage or a MOSFET’s threshold voltage provide the complementary term. An auxiliary biasing block is sometimes necessary to provide the necessary currents for the circuit to work, and additional blocks implement the weighted sum. The scaling of process technologies is the main driving factor for low voltage operation, while the emergence of portable battery-operated, implantable biomedical and energy harvesting devices mandate that every circuit consume as little power as possible. Therefore, sub-1 V supplies and nanoWatt power have become key characteristics for these kind of circuits, but there are several challenges when designing high accuracy voltage references in modern CMOS technologies under these conditions. The traditional topologies are not suitable because they provide a reference voltage above 1 V, and to achieve such power consumption levels would require G resistances, that occupy a huge silicon area. Recent advances have achieved these levels of power consumption but with limited accuracy, expensive calibration procedures and large silicon area.
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36

Dušek, Petr. "Návrh převodníku DA pro nízkonapěťové aplikace v technologii CMOS". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221287.

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This thesis focuses on design of an accurate digital to analog converter (DAC). The thesis provides material to understand the principle of conversion of digital signal to analog signal. Some possible structures of DAC are described in this thesis. The selected structure is used for design of the DAC using the CMOS 07 technology. Functionality of the DAC is verified with simulations using the PSPICE simulation program.
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37

Arreguit, Xavier. "Compatible lateral bipolar transistors in CMOS technology : model and applications /". [S.l.] : [s.n.], 1989. http://library.epfl.ch/theses/?nr=817.

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38

Förster, Fabian Alexander. "Novel CMOS Devices for High Energy Physics and Medical Applications". Doctoral thesis, Universitat Autònoma de Barcelona, 2020. http://hdl.handle.net/10803/670504.

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Els experiments d’alta energia de física (HEP) a col·lisions de partícules demostren la nostra comprensió de l’estructura i la dinàmica de la matèria. Per avançar en el camp, els sistemes d’acceleradors s’actualitzen periòdicament a energies i lluminositats més elevades. Els experiments han de mantenir-se al punt millorant la seva instrumentació de detecció. Els detectors de píxels de silici tenen un paper crític en els experiments HEP. Gràcies a la seva excel·lent resolució de posició, compacitat, velocitat i duresa de la radiació, permeten la reconstrucció de la pista de partícules en entorns d’alta radiació com els col·lisionadors de hadrons. Al seu torn, el seu rendiment permet una excel·lent resolució de paràmetres d’impacte de pista, un ingredient clau per a la identificació de vèrtexs secundaris i l’etiquetatge b del jet. Actualment, el detector estàndard de píxels consisteix en un sensor segmentat, en el qual cada píxel està connectat a un canal de lectura d’un circuit integrat d’aplicacions específiques per a aplicacions (ASIC) mitjançant una tècnica complicada i cara, anomenada enllaç de cop. Un mètode alternatiu per als dispositius de píxels híbrids són els detectors monolítics, que combinen la detecció de partícules i les tasques de processament de senyal al mateix substrat. Aquests tipus de detectors desenvolupats en el procés CMOS han estat utilitzats en el passat, però només recentment es basen en dispositius de radiació durs. sobre aquesta tecnologia s’han proposat. En aquesta tesi s’investiga un primer prototip a mida completa d’un detector monolític desenvolupat en la tecnologia CMOS d’Alta Voltatge (HV-CMOS) com a dispositiu de píxel per a les capes exteriors del futur rastrejador ATLAS actualitzat, que es troba al Gran Col·lisionador d’Hadrons ( LHC) al CERN. A més de l’aplicació d’aquesta tecnologia en experiments HEP, la detecció de fotons de raigs X suaus també s’investiga en una matriu en un dels detectors de píxels HV-CMOS. Per últim, s’explora l’ús de dispositius CMOS per a la detecció de fotons de gairebé infraroig (NIR) amb fotodiode d’Avalanche (APD).
Los experimentos de física de alta energía (HEP) en colisionadores de partículas sondean nuestra comprensión de la estructura y la dinámica de la materia. Para avanzar en el campo, los sistemas de aceleración se actualizan periódicamente a mayores energías y luminosidades. Los experimentos tienen que mantenerse al día, mejorando la instrumentación de su detector. Los detectores de píxeles de silicio desempeñan un papel fundamental en los experimentos con HEP. Gracias a su excelente resolución de posición, compacidad, velocidad y dureza de radiación, permiten la reconstrucción de pistas de partículas en entornos de alta radiación como colisionadores de hadrones. A su vez, su rendimiento permite una excelente resolución de parámetros de impacto en la pista, un ingrediente clave para la identificación secundaria de vértices y el etiquetado de chorro b. Actualmente, el detector de píxeles estándar consta de un sensor segmentado, en el que cada píxel está conectado a un canal de lectura de un circuito integrado de aplicación específica (ASIC) a través de una técnica complicada y costosa llamada unión por golpes. Un enfoque alternativo a los dispositivos de píxeles híbridos son los detectores monolíticos, que combinan la detección de partículas y las tareas de procesamiento de señales en el mismo sustrato. Estos tipos de detectores desarrollados en el proceso CMOS se han utilizado en el pasado, pero solo relativamente recientemente basados ​​en dispositivos de radiación dura sobre esta tecnología se han propuesto. En esta tesis, se investiga un primer prototipo de tamaño completo de un detector monolítico desarrollado en la tecnología CMOS de alto voltaje (HV-CMOS) como un dispositivo de píxeles para las capas externas del rastreador ATLAS de actualización futura, que se encuentra en el Gran Colisionador de Hadrones ( LHC) en el CERN. Además de la aplicación de esta tecnología en experimentos HEP, la detección de fotones de rayos X blandos también se investiga en una matriz en uno de los detectores de píxeles HV-CMOS. Por último, se explora el uso de dispositivos CMOS para la detección de fotones de infrarrojo cercano (NIR) con Avalanche Photodiode (APD).
High Energy Physics (HEP) experiments at particle colliders probe our understanding of the structure and dynamics of matter. In order to advance the field, the accelerator systems are periodically upgraded to higher energies and luminosities. Experiments have to keep up, by improving their detector instrumentation. Silicon pixel detectors play a critical role in HEP experiments. Thanks to their excellent position resolution, compactness, speed and radiation hardness, they enable particle track reconstruction in high radiation environments like hadron colliders. In turn, their performance allows excellent track impact parameter resolution, a key ingredient for secondary vertex identification and jet b-tagging. Currently the standard pixel detector consists of a segmented sensor, in which each pixel is connected to a readout channel of an Application-Specific Integrated Circuit (ASIC) through a complicated, and expensive, technique called bump bonding. An alternative approach to hybrid pixel devices are monolithic detectors, which combine the particle sensing and the signal processing tasks in the same substrate.These kinds of detectors developed in the CMOS process have been used in the past, but only relatively recently radiation hard devices based on this technology have been proposed. In this thesis a first full size prototype of a monolithic detector developed in the High Voltage CMOS (HV-CMOS) technology is investigated as a pixel device for the outer layers of the future upgrade ATLAS tracker, which is located in the Large Hadron Collider (LHC) at CERN. Besides the application of this technology in HEP experiments, the detection of soft X-ray photons is also investigated in one matrix in one of the HV-CMOS pixel detectors. Lastly, the usage of CMOS devices for the detection of Near-Infrared (NIR) photons with Avalanche Photodiode (APD) is explored.
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39

Barsatan, Randy. "CMOS-compatible nonvolatile memories for radio frequency identification (RFID) applications /". View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20BARSAT.

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40

Martin, Lucy Claire. "Characterisation of silicon carbide CMOS devices for high temperature applications". Thesis, University of Newcastle upon Tyne, 2015. http://hdl.handle.net/10443/3030.

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In recent years it has become increasingly apparent that there is a large demand for resilient electronics that can operate within environments that standard silicon electronics cease to function such as high power and high voltage applications, high temperatures, corrosive atmospheres and environments exposed to radiation. This has become even more essential due to increased demands for sustainable energy production and the reduction in carbon emissions worldwide, which has put a large burden on a wide range of industrial sectors who now have a significant demand for electronics to meet these needs including; military, space, aerospace, automotive, energy and nuclear. In extreme environments, where ambient temperatures may well exceed the physical limit of silicon-based technologies, SiC based technology offers a lower cost and a smaller footprint solution for operation in such environments due to its advantageous electrical properties such as a high breakdown electric field, high thermal conductivity and large saturation velocity. High quality material on large area wafers (150 mm) is now commercially available, allowing the fabrication of reliable high temperature, high frequency and high current power electronic devices, improving the already optimised silicon based structures. An important advantage of SiC is that it is the only wide band gap compound semiconductor that can be thermally oxidised to grow insulating, high quality SiO2 layers, which makes it an ideal candidate to replace silicon technologies for metal-oxide-semiconductor applications, which is the main focus of this research. Although the technology has made a number of major steps forward over recent years and the commercial manufacturing process has advanced significantly, there still remains a number of issues that need to be overcome in order to fully realise the potential of the material for electronic applications. This thesis describes the characterisation of 4H-SiC CMOS structures that were designed for high temperature applications and fabricated with varying gate dielectric treatments and process steps. The influence of process techniques on the characteristics of metal-oxide-semiconductor (MOS) devices has been investigated by means of electrical characterisation and the results have been compared to theoretical models. The C-V and I-V characteristics of both MOS capacitor and MOSFET structures with varying gate dielectrics on both n-type and p-type 4H-SiC have been analysed to explore the benefits of the varying process techniques that have been employed in the design of the devices. The results show that the field effect mobility characteristic of 4H-SiC MOSFETs are dominated at low perpendicular electric fields by Coulomb scattering and at high electric fields by low surface roughness mobility, which is due to the rough SiC-SiO2 interface. The findings also show that a thermally grown SiO2 layer at the semiconductor-dielectric interface is a beneficial process step that enhances the interfacial characteristics and increases the channel mobility of the MOSFETs. In addition to this it is also found that this technique provides the most beneficial characteristics on both n-type and p-type 4H-SiC, which suggests that it would be the most suitable treatment for a monolithic CMOS process. The impact of threshold voltage adjust ion implantation on both the MIS capacitor and MOSFET structures is also presented and shows that the increasing doses of nitrogen that are implanted to adjust the threshold voltage act to improve the device performance by acting to modify the charge at the interface or within the gate oxide and therefore increase the field effect mobility of the studied devices.
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41

Lin, Fang. "High-Q high-frequency CMOS bandpass filters for wireless applications". Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/14869.

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42

Carvalho, Carlos Manuel Ferreira. "CMOS indoor light energy harvesting system for wireless sensing applications". Doctoral thesis, Faculdade de Ciências e Tecnologia, 2014. http://hdl.handle.net/10362/13127.

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Dissertação para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores
This research thesis presents a micro-power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched-capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT Fractional Open Circuit Voltage (VOC) technique is implemented by an asynchronous state machine (ASM) that creates and, dynamically, adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point (MPP) condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge reusing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm2 in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm2, is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m2. After starting-up, the system requires an irradiance of only 0.18 W/m2 (18 mW/cm2) to remain in operation. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 mW. These values are, to the best of the authors’ knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3% for an input power of 48 mW, which is comparable with reported values from circuits operating at similar power levels.
Portuguese Foundation for Science and Technology (FCT/MCTES), under project PEst-OE/EEI/UI0066/2011, and to the CTS multiannual funding, through the PIDDAC Program funds. I am also very grateful for the grant SFRH/PROTEC/67683/2010, financially supported by the IPL – Instituto Politécnico de Lisboa.
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43

Jiang, Yu. "CMOS n-dimensional m-level hysteresis circuits and possible applications". College Park, Md.: University of Maryland, 2007. http://hdl.handle.net/1903/7721.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2007.
Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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44

Zhang, Ning. "CMOS millimeter-wave receiver front-end circuits and their applications". [Gainesville, Fla.] : University of Florida, 2009. http://purl.fcla.edu/fcla/etd/UFE0024261.

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45

Aktas, Adem. "Integrated RF CMOS frequency synthesizers and oscillators for wireless applications". Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1078330772.

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Thesis (Ph. D.)--Ohio State University, 2004.
Title from first page of PDF file. Document formatted into pages; contains xix, 217 p.; also includes graphics (some col.). Includes bibliographical references (p. 211-217). Available online via OhioLINK's ETD Center
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46

Tsai, Meng-Hung, i 蔡孟宏. "Applications of CMOS MEMS Process Integration". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/21382880135893151049.

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碩士
國立彰化師範大學
機電工程學系
99
Abstract The most favorite advantages of Complementary Metal-Oxide- Semiconductor (CMOS) are based on its standard material and fabrication and therefore it will make semiconductor manufacturers low costs and high-rate production. Nevertheless MEMS of CMOS fabrication has some drawbacks which limit its applications in sensors and actuators. Comparisons with most of the semiconductor technology, the CMOS fabrication will meet limitations and challenges. The first is that MEMS components need more complicated materials and layers. The second is that designing MEMS structure requires special fabrication processes and these processes are not in the original COMS processes. In this thesis, we propose several advanced fabrication integrating with CMOS-compatible process. It will bring profits of standardized production and has the high performance and reliability of MEMS. We use 0.35μm 2P4M CMOS IC compatible process and propose the new post fabrication for COMS MEMS resonators, infrared absorption sensors and CO gas sensors. Besides we investigate the sacrificial layer of sensors and measure the properties of MEMS resonator, CO gas sensor and so on. Key words： MEMS resonator, CO gas sensor, sacrificial layer
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47

Chang, Cheng Chieh, i 張正杰. "CMOS Exponential Analog Signal Processing Applications". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/40466329229676417086.

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博士
國立臺灣大學
電機工程學研究所
89
This thesis developed some square-law based technologies for exponential applications. It is helpful to take CMOS technologies rather than bipolar technologies in some analog circuits, which were traditionally designed in bipolar technologies and difficult to realize in CMOS process. In the beginning, it is tried to find ways instead of the exponential application about tripler. But exponential functions take overwhelming advantages and conveniences in some analog signal applications, such as variable gain amplifier, translinear based signal processing circuits and gamma corrector, etc. It is promoted to simulate the exponential functions by the square-law of MOSFETs in saturation. A square-law based pseudo-exponential design equation was proposed in chapter 3. Three pseudo-exponential circuits have been implemented and they can be applied to the applications of VGA. However, the circuits with pseudo-exponential characteristics don’t mean that they can implement translinear utilities like bipolar transistors. Pseudo BJTs were proposed in chapter 4 and they have been successfully applied to log-domain lowpass, highpass, bandpass filters and a current-controlled oscillator in a 0.5 um N-well CMOS process. Finally, based on the pseudo-exponential characteristics of the PBJT, a current-mode voltage-controlled root function circuit was proposed in chapter 5. It provides a new possible solution to some root applications by using CMOS technology.
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48

Hsiao, Chun-Fang, i 蕭淳方. "CMOS Analog Multipliers and Their Applications". Thesis, 1989. http://ndltd.ncl.edu.tw/handle/39229038785783307603.

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碩士
國立交通大學
電子研究所
77
Since the first paper reported on a MOS analog multiplier in 1982, there are many principles and structures estiblished for those circuits. Improving the linearity and widening the input range are the most important design objectives to build the analog multipliers. A new analog multiplier circuit without the effect of mobility factor to improve the linearity is proposed first. It is based on the square-law I-V characteristic of the MOS transistor and the operation of the linear current-to-voltage converter. The core of the next multiplier is composed of the four transistors operated in linear region. And there are two versions of buffers realized for widening the input range of these linear region multipliers. The quarter-square technique and the differential source-coupled input pairs have gained favor of large input swing in the third multiplier. At last, a current multiplier which is also without the effect of mobility factor is described. A new self-biasing input section of the current multipli r is proposed for lowering nonideal current mirror effect. All circuits are designed and fabricated in the 3.5μm CMOS double-poly single-metal p-well technology. They have a nonlinearity under one percent. Error analysis and performance evaluation have also performed for each multiplier. PSPICE simulations confirm all results.
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49

Weihsing, Liu. "CMOS Exponential Function Circuits and Their Applications". 2004. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-0107200415142700.

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50

Wang, Min. "Reconfigurable CMOS Mixers for Radio-Frequency Applications". Thesis, 2010. http://hdl.handle.net/1974/5712.

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This thesis focuses on the design of radio-frequency (RF) mixers, including a broadband downconverter mixer, an upconverter mixer and a downconverter mixer with high linearity. The basic mixer topology used in this thesis was the Gilbert cell mixer, which is the most popular mixer topology in modern communication systems. In order to accommodate different applications, the broadband mixer and the upconverter mixer were designed to be reconfigurable. First, a broadband downconverter mixer with variable conversion gain was designed using 0.13-$\mu m$ CMOS technology. The mixer worked from 2 to 10 GHz. By changing the effective transistor size of the transconductor and the load, the mixer was able to work in three different modes with different conversion gain and power consumption. Second, an upconverter mixer with sideband selection was demonstrated in CMOS 0.13-$\mu$m technology. The transmitted sideband could be chosen to be the upper sideband or the lower sideband. The mixer worked at 5 GHz with a 100 MHz IF. The measured voltage conversion gains were 11.2 dB at 4.9 GHz and 12.4 dB at 5.1 GHz. The best sideband rejection was around 30 dB. Third, a modified derivative superposition (DS) technique was used to linearize a Gilbert cell mixer. Simulation results predicted an IIP3 improvement of 12.5 dB at 1 GHz. After linearization, the noise figure of the mixer increased by only 0.7 dB and the conversion gain decreased by 0.3 dB. The power consumption of the mixer increased by 0.96 mW.
Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2010-06-18 14:40:35.062
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