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Yoganathan, Mithuna, Richard Jozsa i Sergii Strelchuk. "Quantum advantage of unitary Clifford circuits with magic state inputs". Proceedings of the Royal Society A: Mathematical, Physical and Engineering Sciences 475, nr 2225 (maj 2019): 20180427. http://dx.doi.org/10.1098/rspa.2018.0427.
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We study the computational power of unitary Clifford circuits with solely magic state inputs (CM circuits), supplemented by classical efficient computation. We show that CM circuits are hard to classically simulate up to multiplicative error (assuming polynomial hierarchy non-collapse), and also up to additive error under plausible average-case hardness conjectures. Unlike other such known classes, a broad variety of possible conjectures apply. Along the way, we give an extension of the Gottesman–Knill theorem that applies to universal computation, showing that for Clifford circuits with joint stabilizer and non-stabilizer inputs, the stabilizer part can be eliminated in favour of classical simulation, leaving a Clifford circuit on only the non-stabilizer part. Finally, we discuss implementational advantages of CM circuits.
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Sai Charishma Pathala, Venkata, i V. Y. Jayasree Pappu. "Elimination of CM Noise from SMPS Circuit using EMI Filter". International journal of electrical and computer engineering systems 14, nr 4 (26.04.2023): 465–71. http://dx.doi.org/10.32985/ijeces.14.4.10.
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The electronic devices are exposed to external electromagnetic signals that produce an unwanted signal called noise in the circuit, which causes electromagnetic interference [EMI] problems. It occurs in two modes: radiated mode and conducted mode. In the radiation mode, the shielding technique is used for radiation mode, in conduction mode filtering technique is used. The design of an EMI filter depends upon the type of noise generated by the Switched Mode Power supply circuit [SMPS]. The SMPS circuit used in this paper is a DC-DC power converter, the Boost converter is a step-up converter and Buck converter is step down converter are considered as equipment for generation of noise, the Line Impedance Stabilization Network [LISN]is used for generating the common output impedance to the power converters, the EMI filters are designed to eliminate noise generated by the circuits. There noise generated by this power converters is Common Mode [CM] noise and Differential Mode [DM] noise. The separation of noise from the equipment is done by using a noise separator. In this paper, CM noise generated by these power converters is eliminated by designing an EMI filter called an inductor filter and a PI filter. The comparison between the LC inductor filter and the PI filter for the boost and buck converters is observed. The PI filter has better performance characteristics when compared to the inductor filter for both SMPS circuits as per the Comité International Special des Perturbations Radioélectriques [CISPR] standards. This standard gives the conducted emission range for different electronic devices.
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YUCE, ERKAN. "VARIOUS CURRENT-MODE AND VOLTAGE-MODE INSTRUMENTATION AMPLIFIER TOPOLOGIES SUITABLE FOR INTEGRATION". Journal of Circuits, Systems and Computers 19, nr 03 (maj 2010): 689–99. http://dx.doi.org/10.1142/s0218126610006372.
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In this paper, four instrumentation amplifier (IA) topologies, one of which is current-mode (CM) while the others are voltage-mode (VM), are presented. Three of the IAs use one to two current feedback operational amplifiers (CFOAs) while the other one employs only a single NMOS transistor. One of the IA circuits, given as an example, is simple while others are novel. The CM IA is composed of only grounded resistors which have some advantages in integrated circuit (IC) process. Non-ideality effects such as non-ideal gain and parasitic impedances on the performance of introduced IAs are discussed. In order to show the performance of the circuits, we perform experimental tests and simulations by using SPICE program.
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Pandey, Neeta, i Sajal K. Paul. "VM and CM Universal Filters Based on Single DVCCTA". Active and Passive Electronic Components 2011 (2011): 1–7. http://dx.doi.org/10.1155/2011/929507.
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A universal voltage-mode filter (VM) and a current-mode filter (CM) based on recently proposed active building block, namely, differential voltage current conveyor transconductance amplifier (DVCCTA) are proposed. Both the circuits use a single DVCCTA, two capacitors, and a single resistor. The filters enjoy low-sensitivity performance and low component spread and exhibit electronic tunability of filter parameters via bias currents of DVCCTA. SPICE simulation using 0.25 μm TSMC CMOS technology parameters is included to show the workability of the proposed circuits.
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Ulansky, Vladimir, Ahmed Raza i Hamza Oun. "Electronic Circuit with Controllable Negative Differential Resistance and its Applications". Electronics 8, nr 4 (8.04.2019): 409. http://dx.doi.org/10.3390/electronics8040409.
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Electronic devices and circuits with negative differential resistance (NDR) are widely used in oscillators, memory devices, frequency multipliers, mixers, etc. Such devices and circuits usually have an N-, S-, or Λ-type current-voltage characteristics. In the known NDR devices and circuits, it is practically impossible to increase the negative resistance without changing the type or the dimensions of transistors. Moreover, some of them have three terminals assuming two power supplies. In this paper, a new NDR circuit that comprises a combination of a field effect transistor (FET) and a simple bipolar junction transistor (BJT) current mirror (CM) with multiple outputs is proposed. A distinctive feature of the proposed circuit is the ability to change the magnitude of the NDR by increasing the number of outputs in the CM. Mathematical expressions are derived to calculate the threshold currents and voltages of the N-type current-voltage characteristics for various types of FET. The calculated current and voltage thresholds are compared with the simulation results. The possible applications of the proposed NDR circuit for designing single-frequency oscillators and voltage-controlled oscillators (VCO) are considered. The designed NDR VCO has a very low level of phase noise and has one of the best values of a standard figure of merit (FOM) among recently published VCOs. The effectiveness of the proposed oscillators is confirmed by the simulation results and the implemented prototype.
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KOKSAL, M., M. SAGBAS i H. SEDEF. "AN ELECTRONICALLY TUNABLE OSCILLATOR USING A SINGLE ACTIVE DEVICE AND TWO CAPACITORS". Journal of Circuits, Systems and Computers 17, nr 05 (październik 2008): 885–91. http://dx.doi.org/10.1142/s0218126608004642.
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A novel resistorless oscillator is presented. The proposed structure enjoys electronic tunability property with minimum number of active and passive components. This oscillator uses a current-mode (CM) active device and has properties of current mode circuits. The validity of the proposed circuit is verified by experimental results.
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Tan, Zhen, Qing-Yuan Lu i Jian-Xin Chen. "A novel balanced-to-balanced power divider based on three-line coupled structure". International Journal of Microwave and Wireless Technologies 11, nr 2 (14.01.2019): 139–42. http://dx.doi.org/10.1017/s1759078718001708.
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AbstractThis paper presents a novel balanced-to-balanced power divider (PD) based on a simple and compact three-line coupled structure for the first time. By bisecting the proposed symmetrical structure, the differential mode (DM) and the common mode (CM) equivalent circuits can be obtained for analysis. The DM equivalent circuit exhibits a three-line in-phase power dividing response, and then a resistor is added between the two outputs for achieving good isolation. Meanwhile, the CM equivalent circuit shows a three-line all-stop response so that the CM suppression in this design does not need to be considered. Accordingly, the detailed design procedure of the DM PD is given. For demonstration, a prototype centered at 1.95 GHz is designed, fabricated, and measured. The simulated and measured results with good agreement are presented, showing low DM loss and wideband CM suppression.
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Rajendran, Selvakumar, Arvind Chakrapani, Srihari Kannan i Abdul Quaiyum Ansari. "A Research Perspective on CMOS Current Mirror Circuits: Configurations and Techniques". Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 14, nr 4 (17.06.2021): 377–97. http://dx.doi.org/10.2174/2352096514666210127140831.
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Background: Immense growth in the field of VLSI technology is fuelled by its feasibility to realize analog circuits in μm and nm technology. The current mirror (CM) is a basic building block used to enhance performance characteristics by constructing complex analog/mixed-signal circuits like amplifier, data converters and voltage level converters. In addition, the current mirror finds diverse applications from biasing to current-mode signal processing. Methods: In this paper, the Complementary Metal Oxide Semiconductor (CMOS) technologybased current mirror (CM) circuits are discussed with their advantages and disadvantages accompanied by the performance analysis of different parameters. It also briefs various techniques which are employed for improvising the current mirror performance like gain boosting and bandwidth extension. Besides, this paper lists the CMs that use different types of MOS devices like Floating Gate MOS, Bulk-driven MOS, and Quasi-Floating Gate MOS. As a result, the paper performs a detailed review of CMOS Current mirrors and their techniques. Results: Basic CM circuits that can act as building blocks in the VLSI circuits are simulated using 0.25 μm, BSIM and Level 1 technology. In addition, various devices based CMs are investigated and compared. Conclusion: The comprehensive discussion shows that the current mirror plays a significant role in analog/mixed-signal circuits design to realize complex systems for low-power biomedical and wireless applications.
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Chen, Minghui, Jianqing Wang, Daisuke Anzai, Georg Fischer i Jens Kirchner. "Common-Mode Noise Reduction in Noncontact Biopotential Acquisition Circuit Based on Imbalance Cancellation of Electrode-Body Impedance". Sensors 20, nr 24 (13.12.2020): 7140. http://dx.doi.org/10.3390/s20247140.
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Biopotential sensing technology with electrodes has a great future in medical treatment and human—machine interface, whereas comfort and longevity are two significant problems during usage. Noncontact electrode is a promising alternative to achieve more comfortable and long term biopotential signal recordings than contact electrode. However, it could pick up a significantly higher level of common-mode (CM) noise, which is hardly solved with passive filtering. The impedance imbalance at the electrode-body interface is a limiting factor of this problem, which reduces the common mode rejection ratio (CMRR) of the amplifier. In this work, we firstly present two novel CM noise reduction circuit designs. The circuit designs are based on electrode-body impedance imbalance cancellation. We perform circuit analysis and circuit simulations to explain the principles of the two circuits, both of which showed effectiveness in CM noise rejection. Secondly, we proposed a practical approach to detect and monitor the electrode-body impedance imbalance change. Compared with the conventional approach, it has certain advantages in interference immunity, and good linearity for capacitance. Lastly, we show experimental evaluation results on one of the designs we proposed. The results indicated the validity and feasibility of the approach.
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Alhalabi, Marah, Mohammed Ghazal, Fasila Haneefa, Jawad Yousaf i Ayman El-Baz. "Smartphone Handwritten Circuits Solver Using Augmented Reality and Capsule Deep Networks for Engineering Education". Education Sciences 11, nr 11 (20.10.2021): 661. http://dx.doi.org/10.3390/educsci11110661.
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Resolving circuit diagrams is a regular part of learning for school and university students from engineering backgrounds. Simulating circuits is usually done manually by creating circuit diagrams on circuit tools, which is a time-consuming and tedious process. We propose an innovative method of simulating circuits from hand-drawn diagrams using smartphones through an image recognition system. This method allows students to use their smartphones to capture images instead of creating circuit diagrams before simulation. Our contribution lies in building a circuit recognition system using a deep learning capsule networks algorithm. The developed system receives an image captured by a smartphone that undergoes preprocessing, region proposal, classification, and node detection to get a Netlist and exports it to a circuit simulator program for simulation. We aim to improve engineering education using smartphones by (1) achieving higher accuracy using less training data with capsule networks and (2) developing a comprehensive system that captures hand-drawn circuit diagrams and produces circuit simulation results. We use 400 samples per class and report an accuracy of 96% for stratified 5-fold cross-validation. Through testing, we identify the optimum distance for taking circuit images to be 10 to 20 cm. Our proposed model can identify components of different scales and rotations.
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Kumar, Ashok, i Sajal K. Paul. "DX-MOCCII Based Fully Cascadable Second Order Current-Mode Universal Filter". Journal of Circuits, Systems and Computers 27, nr 07 (26.03.2018): 1850113. http://dx.doi.org/10.1142/s021812661850113x.
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The paper presents a new second-order single input multiple output (SIMO) type current mode (CM) universal filter. The proposed circuit uses two dual-X second generation multi-output current conveyors (DX-MOCCII), two grounded capacitors and three grounded resistors. The circuit configuration realizes low-pass filter (LPF), high-pass filter (HPF), band-pass filter (BPF), notch filter (NF) and all-pass filter (APF) responses simultaneously at different output terminals. The new circuit enjoys the features of low input impedance and high output impedance, which is desirable and useful for cascadability in CM circuits. For realizing the universal filter responses, the proposed circuit configuration does not require matching constraint of passive components and both active and passive sensitivities are found low. In addition, the extension of the proposed circuit as a resistorless universal filter has also been presented. As an application of the proposed filter, inverting band pass output is connected to a negative unity gain current follower in a close loop to design voltage and CM multiphase sinusoidal oscillators (MSOs). Comparison of the proposed configuration with available literature is given. The PSPICE simulation of the filter and its application as MSO are performed to verify the agreement with the theoretical proposition.
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Tarateeraseth, Vuttipon. "Integrated Magnetic Circuits for Differential-mode and Common-mode Chokes of EMI Filters". ECTI Transactions on Electrical Engineering, Electronics, and Communications 12, nr 1 (6.02.2019): 82–89. http://dx.doi.org/10.37936/ecti-eec.2014121.170801.
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In this paper, two magnetic circuits to integrate common-mode (CM) and differential-mode (DM) chokes of an electromagnetic interference (EMI) filter are proposed. The DM and CM chokes are integrated by using UIU and EI ferrite core shapes. To evaluate the EMI reduction performances of proposed approaches, the conducted EMI reduction performances of proposed integrated DM and CM chokes are compared with the conventional CM choke and traditional separated DM and CM chokes. From the experimental results, it ensures the advantages of the use of proposed approaches. Although some magnetic parts are eliminated by proposed approaches, the amount of DM and CM EMI attenuation rate is comparable to the case of traditional separated DM and CM chokes, except the highest peak is located at different frequencies.
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Kumar, Paipalem Manoj. "Comparison of Piezo Resistive Property of Graphene based Polymer Films and Carbon Nanotube based Polymer Films to Optimize the Conductivity". Revista Gestão Inovação e Tecnologias 11, nr 2 (5.06.2021): 1324–38. http://dx.doi.org/10.47059/revistageintec.v11i2.1760.
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Aim: The piezo resistive property of Graphene PVDF films and Carbon nanotube PVDF films is analyzed and the possibility of replacing solid state resistor (10 ohm) in electronic circuits is explored. Materials and Methods: Embedded hardware interface and Wheatstone bridge circuit is used to analyze the electrical conductivity of Graphene PVDF films (n=10) and Carbon nanotube PVDF films (n=10) of length 2.6 cm and width 1.1 cm. Results: Graphene PVDF films have significantly higher Conductivity (0.082 s/m) (p<0.05) than Carbon nanotube PVDF films (0.0108 s/m). Conclusion: Within the limits of this study Graphene PVDF films offer best Conductivity and can be used as a replacement for solid state resistors.
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Wang, Fengtao, Fuhan Liu, Gee-Kung Chang, Mathew Q. Yao, Ali Adibi i Rao Tummala. "A Real-Time Precision Characterization Technique for Low-Loss Optical Polymeric Waveguide and Lightwave Circuits". Journal of Microelectronics and Electronic Packaging 5, nr 1 (1.01.2008): 26–30. http://dx.doi.org/10.4071/1551-4897-5.1.26.
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An optical polymer waveguide is a key passive component for the optical interconnection. Design, fabrication, and characterization of high-performance waveguides have critical importance for the success of optoelectronic integration. In addition, defect effects, coupling, leakages, crosstalk, etc. are great concerns for the lightwave circuits. We present herein a fast, nondestructive, sensitive, real-time technique for detailed investigation of the propagation properties of planar optical waveguides and lightwave circuits. We use this technique to measure low-loss polymer waveguides on printed circuit board (PCB) substrates, and we have measured propagation losses of 0.065 dB/cm at 850 nm and 0.046 dB/cm at 980 nm. To the best of our knowledge, these are among the lowest losses reported to date for polymer waveguides on PCB substrates. A high-sensitivity CCD camera with a built-in integration function is utilized to observe the light streak in two dimensions through a two-lens imaging system. A few seconds to a few tens of seconds is needed for one complete measurement, compared with the sliding prism method, which requires several hours, and the cutback method, which requires even longer times. This technique can be used to evaluate not only the overall performance of a waveguide but also the local waveguide performance, as well as perform in-situ investigation of propagation properties (defect effect, bending effect, coupling, leakage, etc.). It can be extended to monitor the process of waveguide fabrication and alignment control during assembly for lightwave circuit integration.
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Fareq, M., M. Fitra, Muhamad Irwanto, H. S. Syafruddin, Nair Gomesh, Y. M. Irwan, M. A. Halim, Suwarno, A. Herman i T. Hussain. "50 cm Air Gap Wireless Power Transfer by Magnetic Resonance Coupling". Applied Mechanics and Materials 785 (sierpień 2015): 205–9. http://dx.doi.org/10.4028/www.scientific.net/amm.785.205.
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In this paper, we have developed transmitter, receiver and 2 structure magnetic resonant couplings. Both of the Transmitter and Receiver couplings are made of copper tubing. Transmitter and Receiver circuits were build by using Multisim software. Transmitter in put by DC source 12 Volt, 0.5 Ampere, with 50 cm Air gap wireless power transfer can reach efficiency 25.2 % with DC 3.02 Volt, 50.01 mA, at Frequency 164.76 kHz.
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Tarateeraseth, Vuttipon. "Operational Amplier Gain-Bandwidth Product Enhancement Technique for Common-mode Active EMI Filter Compensation Circuits". ECTI Transactions on Electrical Engineering, Electronics, and Communications 11, nr 2 (4.09.2013): 43–50. http://dx.doi.org/10.37936/ecti-eec.2013112.170668.
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In this paper, the operational amplier (op-amp) gain-bandwidth product (GBP) enhancement technique for common-mode (CM) active EMI lter compensation circuits is proposed. To evaluate the proposed concept, the CM reduction performance of active EMI lters with: voltage canceling, current canceling, and closed-loop techniques, is chosen to be veried. The design procedures of enhanced op-amp GBP of CM active EMI lters are also provided. Finally, the CM reduction performances of the proposed approach are compared and veried experimentally. From the experimental results, it can be concluded that the proposed approach can improve the CM reduction performance of conventional active EMI lters from about 5 dBuV up to 20 dBuV at a certain frequency range.
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Gea, Maria Rosariana, Lazuardi Umar i Rahmondia Nanda Setiadi. "IDENTIFICATION OF WHITE NOISE AND 1/f IN CURRENT MIRROR CONFIGURATION BASED ON VDS MOSFET". JOURNAL ONLINE OF PHYSICS 7, nr 2 (23.06.2022): 40–47. http://dx.doi.org/10.22437/jop.v7i2.18167.
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Identifying noise in the Current Mirror (CM) circuit is essential to locate noise signals in biosensor applications so that measurements become more accurate and precise. There are two dominant types of noise: white noise, which consists of thermal noise and shot noise, and also low-frequency noise (1/f noise). The main component of the CM circuit is the BS250 type MOSFET, which works by varying the width of the charge carrier channelcontrolled by the voltage at the gate. When the drain is given a voltage, electrons will flow from the source to the drain which generates the noise.This study was carried out to identify the noise in the CM configuration by varying the reference voltage of MOSFET using the PCI-6221 card data integrated with the LabVIEW program. The reference voltage values used are 1 mV, 10 mV, and 100 mV to determine the effect of the input voltage on the CM circuit noise signal, while the measurement frequency is varied from 0.1 Hz to 100 kHz with a resolution of 0.1 Hz. The results show that the noise characteristics vary with the applied voltage, which will increase at a higher voltage. Analysis of 1/f noise at frequencies up to 0.2 Hz has a gradient increase of up to 10 times for each given voltage value. Based on the value of the data distribution on the white noise measurement, it shows that a voltage of 100 mV produces the highest noise with an average of 3.62 × 10-7 Vrms/Hz1/2. The results of this study are used in the design of CM circuits with minimal noise.
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Chen, Shun Tong, i Chih Hsien Chang. "Study on Thinning of a Boron-Doped Polycrystalline Diamond Wheel-Tool by Micro Rotary W-EDM Approach". Applied Mechanics and Materials 217-219 (listopad 2012): 2167–70. http://dx.doi.org/10.4028/www.scientific.net/amm.217-219.2167.
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This study presents a novel approach for using a micro rotary wire Electrical Discharge Machining (micro w-EDM) to thin the grinding-edge of a wheel-tool made from boron-doped polycrystalline composite diamond (PCD). For thinning the PCD, two discharge circuits (a Resistance-Capacitance (RC) circuit and a transistor) were used as power sources to obtain a grinding-edge of less than 10 µm in thickness and high surface quality. The wheel-blank is vertically mounted on a spindle and while rotating is thinned by micro w-EDM along a planned computer numerically controlled path. Experimental results verify that boron-doped PCD can be successfully thinned down to 5 µm in edge-thickness. The study shows it is possible to break (cut) diamonds of 10-µm grain size, leaving smooth surface-exposed diamonds at the cutting edge of the wheel tool. The dimensional and geometrical accuracy of the wheel-tool can be exactly controlled. Raman analysis reveals graphitizing of the PCD caused by local high temperature spark erosion at a peak of 1593 cm-1 in RC discharge circuit machining. The peak at 1332 cm-1 for the transistor circuit method indicates diamond sp3 structure. The surface degenerating layer produced by transistor circuit machining gives a suitably thin grinding edge with exposed diamond grains.
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MANA, Hassan. "Simulation of transfer of HF conductive disturbances from the primary to the secondary circuits of inductive current transformers in CM-CM coupling". PRZEGLĄD ELEKTROTECHNICZNY 1, nr 1 (5.01.2020): 95–101. http://dx.doi.org/10.15199/48.2020.01.22.
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Mohd Noor Sam, Muhamad Arif Ihsan, Zhenhu Jin, Mikihiko Oogane i Yasuo Ando. "Investigation of a Magnetic Tunnel Junction Based Sensor for the Detection of Defects in Reinforced Concrete at High Lift-Off". Sensors 19, nr 21 (30.10.2019): 4718. http://dx.doi.org/10.3390/s19214718.
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Magnetic flux leakage (MFL) testing is a method of non-destructive testing (NDT), whereby the material is magnetized, and when a defect is present, the magnetic flux lines break out of the material. The magnitude of the leaked magnetic flux decreases as the lift-off (distance from the material) increases. Therefore, for detection at high lift-off, a sensitive magnetic sensor is required. To increase the output sensitivity, this paper proposes the application of magnetic tunnel junction (MTJ) sensors in a bridge circuit for the NDT of reinforced concrete at high lift-off. MTJ sensors were connected to a full-bridge circuit, where one side of the arm has two MTJ sensors connected in series, and the other contains a resistor and a variable resistor. Their responses towards a bias magnetic field were measured, and, based on the results, the sensor circuit sensitivity was 0.135 mV/mT. Finally, a reinforced concrete specimen with a 1 cm gap in the center was detected. The sensor module (with an amplifier and low pass filter circuits) could determine the gap even at 50 cm, suggesting that MTJ sensors have the potential to detect defects at high lift-off values and have a promising future in the field of NDT.
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Ben Fadhel, Yosra, Sana Ktata, Khaled Sedraoui, Salem Rahmani i Kamal Al-Haddad. "A Modified Wireless Power Transfer System for Medical Implants". Energies 12, nr 10 (17.05.2019): 1890. http://dx.doi.org/10.3390/en12101890.
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Wireless Power Transfer (WPT) is a promising technique, yet still an experimental solution, to replace batteries in existing implants and overcome the related health complications. However, not all techniques are adequate to meet the safety requirements of medical implants for patients. Ensuring a compromise between a small form factor and a high Power Transfer Efficiency (PTE) for transcutaneous applications still remains a challenge. In this work, we have used a resonant inductive coupling for WPT and a coil geometry optimization approach to address constraints related to maintaining a small form factor and the efficiency of power transfer. Thus, we propose a WPT system for medical implants operating at 13.56 MHz using high-efficiency Complementary Metal Oxide-Semiconductor (CMOS) components and an optimized Printed Circuit Coil (PCC). It is divided into two main circuits, a transmitter circuit located outside the human body and a receiver circuit implanted inside the body. The transmitter circuit was designed with an oscillator, driver and a Class-E power amplifier. Experimental results acquired in the air medium show that the proposed system reaches a power transfer efficiency of 75.1% for 0.5 cm and reaches 5 cm as a maximum transfer distance for 10.67% of the efficiency, all of which holds promise for implementing WPT for medical implants that don’t require further medical intervention, and without taking up a lot of space.
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Lake, George, i R. E. Pudritz. "Ultra-High Energy Cosmic Ray Production by Current Disruption in Active Galactic Nuclei". Symposium - International Astronomical Union 107 (1985): 471–73. http://dx.doi.org/10.1017/s0074180900075951.
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Electrodynamic models for the activity of galactic nuclei are shown to be current systems which can be examined in terms of equivalent circuits. The resulting inductive circuit which describes the coupling of the generator (black-hole and accretion disk) to the distant load (jet plasma) is prone to various instabilities. We consider the disruption of this current system and propose that ultra-energetic cosmic rays (E~1019–1021 eV) could be produced during the discharges, which occur at distances of ~1016–1018 cm from the central massive hole (M~108 M). Such discharges will also produce variable γ-ray and X-ray activity and we discuss observations of Cen A in this regard.
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Rawn, OJ, HK Harris, JB Riley, ON Yoda i MM Blackwell. "An Under-Occluded Roller Pump is Less Hemolytic Than a Centrifugal Pump". Journal of ExtraCorporeal Technology 29, nr 1 (marzec 1997): 15–18. http://dx.doi.org/10.1051/ject/199729115.
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The purpose of this study is to measure and compare the hemolysis produced by roller pumps with varied occlusion settings and a centrifugal pump. The null hypothesis is that there is no difference in the Index of Hemolysis (IH=gm Hb/100 L pumped) produced by a roller pump (RP) at four different occlusion settings and a centrifugal pump (CP) at the same blood flow rate (4.5 L/min) and afterload (250 mmHg, ±10 mmHg) over three hours. Five identical closed-loop circuits were assembled and primed with saline. The pumps were then calibrated and occlusions were set. In three circuits, the occlusion for the RP was opened at 5 RPMs to support 150, 225, or 300 mmHg (±10 mmHg) against a clamped line. In one circuit, a RP was adjusted to a barely non-occlusive setting (1 cm drop/30 inch gradient). The fifth circuit employed a CP. Prior to testing, the saline in each circuit was replaced with one liter of fresh bovine blood (Hct=22±2%). The IH for each treatment was compared in six trials yielding a statistical power> 0.80. Analysis of variance with multiple comparison (p≤0.05) demonstrated that compared to the barely non-occlusive setting, the IH in the centrifugal pump was not significantly greater. Under-occluded RP settings yielded IHs significantly less than the CP. It appears that opening the occlusion on a roller pump allows a lower IH compared to traditional RP occlusion setting or centrifugal pumping.
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Satoh, T., K. Hinode, S. Nagasawa, Y. Kitagawa i M. Hidaka. "Improvement of Fabrication Process for 10-${\rm kA/cm}^{2}$ Multi-Layer Nb Integrated Circuits". IEEE Transactions on Applied Superconductivity 17, nr 2 (czerwiec 2007): 169–72. http://dx.doi.org/10.1109/tasc.2007.897871.
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Maksymov, S. Yu, L. S. Shlapak, А. А. Havryliuk, І. М. Semianyk i V. А. Onyskiv. "Regularities of Control of Mechanized Pulse-Arc Welding Process for Ensuring its Stability". Prospecting and Development of Oil and Gas Fields, nr 4(73) (30.12.2019): 65–76. http://dx.doi.org/10.31471/1993-9973-2019-4(73)-65-76.
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Mechanized arc welding in protective gases with short circuits (s.c.) is performed at moderate values of the welding current (up to 180 ... 220 A) and at the relatively low voltage (18 ... 24 V) on the arc. The main disadvantage of the process is spattering when melting an electrode metal and when transferring it to a weld bath. The elimination of disadvantages is possible through the implementation of a controlled transfer of molten electrode metal to a welding bath - due to the pulsed nature of arc burning. At pulse-arc welding (PAW), one of the main methods of increasing the efficiency of the process is to limit the maximum value of the short-circuit current Imax s.c. by increasing the inductive resistance L in the arc-welding circuit. Proceeding from the features of mechanized arc welding, the purpose of the research is to specify the influence of the velocity of the growth of the welding current vс during the s.c. on the arc stability. The implementation of experimental work presupposes surfacing on a plate with the programming of the operating mode of the inverter at different values (9, 12, 15, 18, 21, 24, 27, 30) with the frequency f = 25 Hz and a pulse ratio C = 2. While analyzing oscillograms of welding current and processing their records, it was established that a decrease of the velocity of the welding current growth leads to a significant limitation of the maximum value of the short-circuit current. The statistical processing of the momentary values of the welding current shows that the increase in the velocity of current growth vс starting with vс = 1.23 kA / s to vс = 50 kA / s makes the average short-circuit duration 10 times shorter. At the same time, the average frequency of short circuits grows more than twice. The increase of vс leads to the destabilization of the pulse process and this is reflected in the 30-times increase of the average frequency of arc break. The increase of the energy indexes of the PAW to the Iav. = 220 ... 225 A, Uav. = 24.5 ... 25.9 V, Q ≈ 7.9 ... 8.0 kJ / cm led to the changes in the parameters which characterize the process of pulsed welding with short circuits. There is a sharp decrease in the average frequency of short circuits (2 ... 3 times as rarely) and the average duration of s.c. (twice shorter).
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Rêgo Segundo, Alan Kardek, Érica Silva Pinto, Gabriel Almeida Santos i Paulo Marcos de Barros Monteiro. "Capacitive Impedance Measurement: Dual-frequency Approach". Sensors 19, nr 11 (4.06.2019): 2539. http://dx.doi.org/10.3390/s19112539.
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The most widely used technique for measuring capacitive impedances (or complex electrical permittivity) is to apply a frequency signal to the sensor and measure the amplitude and phase of the output signal. The technique, although efficient, involves high-speed circuits for phase measurement, especially when the medium under test has high conductivity. This paper presents a sensor to measure complex electrical permittivity based on an alternative approach to amplitude and phase measurement: The application of two distinct frequencies using a current-to-voltage converter circuit based in a transimpedance amplifier, and an 8-bit microcontroller. Since there is no need for phase measurement and the applied frequency is lower compared to the standard method, the circuit presents less complexity and cost than the traditional technique. The main advance presented in this work is the use of mathematical modeling of the frequency response of the circuit to make it possible for measuring the dielectric constant using a lower frequency than the higher cut-off frequency of the system, even when the medium under test has high conductivity (tested up to 1220 μS/cm). The proposed system caused a maximum error of 0.6% for the measurement of electrical conductivity and 2% for the relative dielectric constant, considering measurement ranges from 0 to 1220 μS/cm and from 1 to 80, respectively.
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Vygranenko, Yuri, Miguel Fernandes, Paula Louro, Manuela Vieira, Alireza Khosropour, Ruifeng Yang i Andrei Sazonov. "Amorphous Silicon Photovoltaic Modules on Flexible Plastic Substrates". MRS Advances 1, nr 43 (2016): 2923–28. http://dx.doi.org/10.1557/adv.2016.430.
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ABSTRACTThis paper reports on a monolithic 10 cm × 10 cm area PV module integrating an array of 72 a-Si:H n-i-p cells on a 100 μm thick polyethylene-naphtalate substrate. The n-i-p stack is deposited using a PECVD system at 150 °C substrate temperature. The design optimization and device performance analysis are performed using a two-dimensional distributed circuit model of the photovoltaic cell. The circuit simulator SPICE is used to calculate current and potential distributions in a network of sub-cell circuits, and also to map Joule losses in the front TCO electrode and the metal grid. Experimental results show that the shunt leakage is one of the factors reducing the device performance. Current-voltage characteristics of individual a-Si:H p-i-n cells were analyzed to estimate a variation of shunt resistances. Using the LBIC technique, the presence of multiple shunts in the n-i-p cell was detected. To understand the nature of electrical shunts, the change in the surface roughness of all device layers was analyzed throughout fabrication process. It is found that surface defects in plastic foils, which are thermally induced during the device fabrication, form microscopic pinholes filled with highly conductive top electrode material.
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Dong, Mark, David Heim, Alex Witte, Genevieve Clark, Andrew J. Leenheer, Daniel Dominguez, Matthew Zimmermann i in. "Piezo-optomechanical cantilever modulators for VLSI visible photonics". APL Photonics 7, nr 5 (1.05.2022): 051304. http://dx.doi.org/10.1063/5.0088424.
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Visible-wavelength very large-scale integration photonic circuits have a potential to play important roles in quantum information and sensing technologies. The realization of scalable, high-speed, and low-loss photonic mesh circuits depends on reliable and well-engineered visible photonic components. Here, we report a low-voltage optical phase shifter based on piezo-actuated mechanical cantilevers, fabricated on a CMOS compatible, 200 mm wafer-based visible photonics platform. We show linear phase and amplitude modulation with 6 Vπ cm in differential operation, −1.5 to −2 dB insertion loss, and up to 40 dB contrast in the 700–780 nm range. By adjusting selected cantilever parameters, we demonstrate a low-displacement and a high-displacement device, both exhibiting a nearly flat frequency response from DC to a peak mechanical resonance at 23 and 6.8 MHz respectively, which, through resonant enhancement of Q ∼ 40, further decreases the operating voltage down to 0.15 Vπ cm.
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Zhang, Gang, Yang Zhao i Wei Yan. "A Compact Differential-Mode Wide Stopband Bandpass Filter with Good and Wideband Common-Mode Suppression". Wireless Communications and Mobile Computing 2018 (2018): 1–4. http://dx.doi.org/10.1155/2018/4032183.
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This letter presents a microstrip differential-mode (DM) bandpass filter (BPF) with high and wide stopband suppression under both DM and common-mode (CM) operations. A new coupling topology is formed up to realize the DM BPF by integrating a pair of λ/2 microstrip transmission lines and two multimode resonators. The DM and CM equivalent half-circuits are established to explain the operating principal. For validation, a DM BPF operating at 2.2 GHz is implemented. Experimental results indicate that the presented DM BPF exhibits not only sharp DM passband selectivity but also deep and ultrawide stopband suppression of more than 30 dB for both DM and CM.
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Tolpygo, Sergey K., D. Yohannes, R. T. Hunt, J. A. Vivalda, D. Donnelly, D. Amparo i A. F. Kirichenko. "20 ${\hbox{kA/cm}}^{2}$ Process Development for Superconducting Integrated Circuits With 80 GHz Clock Frequency". IEEE Transactions on Applied Superconductivity 17, nr 2 (czerwiec 2007): 946–51. http://dx.doi.org/10.1109/tasc.2007.898571.
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Orda-Zhigulina, M. V. "Evaluation of High-Speed Link Parameters for Highly Reliable Reconfigurable Systems Based on S-Parameters and BER". Proceedings of the Southwest State University 25, nr 3 (29.01.2022): 167–80. http://dx.doi.org/10.21869/2223-1560-2021-25-3-167-180.
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Purpose of research. is to improve signal transmission parameters in high-speed signal transmission lines, including between programmable logic integrated circuits (PLIC). This improvement in signal transmission parameters is necessary to increase throughput of modern highly reliable reconfigurable systems to ensure data transfer rate of up to tens of Gbit/s. It can be done considering the influence of electrical and structural parameters of multi-layer printed circuit boards (MPCB) on them. It is possible to provide such high data rates by using a wider frequency band of transmitted signals. One of the existing approaches to this problem is to increase "physical" frequency of transmitted information signals to 25-300 GHz, which is sufficient to achieve desired rates.Methods. A method for estimating quality of high-speed signal transmission lines based on the definition of standardized methods for analyzing signal transmission parameters, such as JCOM, S-parameters and BER is proposed in the article. This method allows evaluating high-speed communication lines. Thus, the Channel Operating Margin (COM)/JCOM parameter can be used to estimate the quality of a digital communication channel - a standardized method for determining the overall channel quality indicator. Known methods are used to estimate such signal transmission parameters as S11 reflection coefficient and S21 attenuation coefficient (S-Parameters). These methods are used to estimate attenuation and loss of the information signal in the path, when copies of the signal reflected from inhomogeneities affect the original and lead to its distortion. Simulation of such parameter as Bit Error Rate (BER) is carried out according to G.821/G.826/M2100 rationing and quality control methodology.Results. The main metrics were selected to evaluate the quality of high-speed signal transmission lines. It is based on the evaluation of such signal transmission parameters as Channel Operating Margin (COM), S-parameters and Bit Error Rate (BER). Numerical evaluations of signal transmission parameters were obtained and their effect on the design parameters of high-speed signal transmission lines was estimated. It is recommended to use at least 1 transition hole between screening polygons in GND separation layers every 0.5 cm or 0.25 cm2 of WFP area. It is for a data rate of less than 25 Gbit/s, It is recommended to use at least 2 transition holes between screening polygons in GND separation layers every 0.5 cm or 0.25 cm² of PV area, if high-speed signal transmission line passes at a distance of closer than 2.5 cm from the power supply circuits in a projection on the layer where the power supply circuits are located.Conclusion. A method for calculating signal transmission parameters on high-speed signaling lines based on the calculation of Channel Operating Margin (COM), S-parameters and Bit Error Rate (BER) parameters is introduced. As part of introduced method, an analysis of signal transmission parameters was carried out. This analysis shows that when the "reference" values of electrical parameters of the line are met, the transfer holes contribute most to the signal distortion; then the layers in which the signal line is located, the number of screening polygons between the signal layers and the layers; in which the power supply circuits, the design parameters of the transition holes, as well as the length and number of segments of the high-speed line pass. Numerical evaluations of minimum number of transition holes and their diameter, the length of segments of differential pairs are given. These results can be used in pre-layout analysis step of high-speed signal transmission lines for computational modules of highly reliable reconfigurable systems.
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Kaplan, Steven L., i Aderinto Ogunniyi. "Reliability Testing of 4H-SiC Bipolar Junction Transistors in Continuous Switching Applications". Materials Science Forum 600-603 (wrzesień 2008): 1167–70. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1167.
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Continued improvement in silicon carbide (SiC) material processing has allowed development of efficient high temperature devices which are uniquely suited to power electronics circuit designs. The 4H-SiC structure has several intrinsic characteristics that facilitate optimal speed and power handling during high temperature device operation. These characteristics include wide bandgap (3.2 eV), high dielectric breakdown (3.5 MV/cm), and high thermal conductivity (4.9 W/cm-K)[1,2]. By combining these properties, SiC bipolar junction transistors (BJTs) can achieve fast, low impedance switching at high voltages (1.2 kV). New generation devices are being developed with increased current handling capability, as well as improved forward voltage characteristics. The device considered here, along with its on-state DC characteristic, is shown in figure 1. The BJTs are approximately 5mm by 5mm, and are nominally rated for a maximum Ice of 50A. Measurements on the Tektronix 371B curve-tracer indicate current gains over 60 at 25 oC and roughly 40 at 150 oC. These results were obtained at collector currents up to 20A. The base current for BJTs is typically 300 to 800 mA, depending on device temperature and the maximum device current required. In order to meet current handling requirements of up to 80A, as required for power conversion in modern military systems such as the hybrid-electric vehicle (HEV), it is necessary to configure these devices in parallel with minimal external cooling. The resulting switching circuits must therefore be validated for operation at high temperatures (package temperatures of 90 oC, and junction temperatures to 150 oC). Validation includes characterization of the devices in clamped inductive circuits with devices configured both alone and in parallel over time. Figure 4 shows measurement waveforms obtained during continuous clamped inductive switching. The primary focus of this work is to establish the overall performance and reliability of these newer generation SiC BJTs in power conversion circuits. Failure analysis and critical performance issues, such as current sharing, energy loss, and total reverse recovery charge are addressed. The initial results of the experiments indicate that these SiC switches have the potential to perform reliably in high temperature power conversion.
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Sadovenko, Ivan, i Oleksandr Inkin. "JUSTIFICATION OF HYDRODYNAMIC TA ASSESSMENT METHODOLOGY GEOMECHANICAL INFLUENCE OF NEEDLE FILTER INSTALLATIONS". SCIENTIFIC PAPERS OF DONNTU Series: “The Mining and Geology”, nr 1(27)-2(28)2022 (2022): 67–77. http://dx.doi.org/10.31474/2073-9575-2022-1(27)-2(28)-67-77.
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Purpose. The purpose of this work is to develop and test the methodology for determining changes in the level of groundwater over time as a result of the operation of several contours of needle filters of different configurations and the impact of these changes on the subsidence of the earth’s surface. Methods. The proposed comprehensive approach includes the collection, systematization and analysis of data on the existing methods of calculating the subsidence of the earth’s surface at the base of structures in the event of an expected decrease in the level of groundwater. The method of numerical hydrogeological modeling and analytical calculations was used to determine the magnitude of the decrease in the groundwater level and subsidence of the earth’s surface. Findings. According to the results of numerical modeling of geofiltration, it was established that after the second month of operation of the first circuit of needle filters, the groundwater level mark at a distance of 20 m from them is 50.4 m, at 50 m – 51 m, at 100 m – 51.6 m. the main decrease of water occurs in the first 7 m from the drainage circuit and is 6.35 – 3.8 m. After 6 months of operation of the first circuit and 4 months of the second water level mark at a distance of 20 m from the circuit is 46.7 m, at 50 m – 47.8 m, at 100 m – 48.9 m. This, respectively, leads to a decrease in the level at these points by 6.8 m, 5.7 m and 4.6 m. it was established that in the first 100 m from the pit, soil subsidence at the end of operation of the two needle filter circuits will vary from 3.9 cm to 2.6 cm. Originality. The method of determining changes in the groundwater level as a result of the operation of several needle filter circuits and the impact of these changes on the subsidence of the earth’s surface has been substantiated and verified. The developed technique allows to analyze and preliminarily quantitatively assess the hydrodynamic regime and geomechanical state of rocks under the influence of needle filters. Practical implication. The proposed method can be used for engineering forecasts of subsidence of the earth’s surface during water-reduction works with needle filter installations, which is especially relevant in the conditions of built-up areas. Keywords: drainage, needle filters, groundwater, earth’s surface, subsidence.
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Huang, Wei, Jianhua Chen, Yao Yao, Ding Zheng, Xudong Ji, Liang-Wen Feng, David Moore i in. "Vertical organic electrochemical transistors for complementary circuits". Nature 613, nr 7944 (18.01.2023): 496–502. http://dx.doi.org/10.1038/s41586-022-05592-2.
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AbstractOrganic electrochemical transistors (OECTs) and OECT-based circuitry offer great potential in bioelectronics, wearable electronics and artificial neuromorphic electronics because of their exceptionally low driving voltages (<1 V), low power consumption (<1 µW), high transconductances (>10 mS) and biocompatibility1–5. However, the successful realization of critical complementary logic OECTs is currently limited by temporal and/or operational instability, slow redox processes and/or switching, incompatibility with high-density monolithic integration and inferior n-type OECT performance6–8. Here we demonstrate p- and n-type vertical OECTs with balanced and ultra-high performance by blending redox-active semiconducting polymers with a redox-inactive photocurable and/or photopatternable polymer to form an ion-permeable semiconducting channel, implemented in a simple, scalable vertical architecture that has a dense, impermeable top contact. Footprint current densities exceeding 1 kA cm−2 at less than ±0.7 V, transconductances of 0.2–0.4 S, short transient times of less than 1 ms and ultra-stable switching (>50,000 cycles) are achieved in, to our knowledge, the first vertically stacked complementary vertical OECT logic circuits. This architecture opens many possibilities for fundamental studies of organic semiconductor redox chemistry and physics in nanoscopically confined spaces, without macroscopic electrolyte contact, as well as wearable and implantable device applications.
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Singh, S. V., R. S. Tomar i D. S. Chauhan. "Single CFTA Based Current-Mode Universal Biquad Filter". Journal of Engineering Research [TJER] 13, nr 2 (1.12.2016): 172. http://dx.doi.org/10.24200/tjer.vol13iss2pp172-186.
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This paper introduces a new current-mode (CM) universal biquad filter structure with optimum number of active and passive elements. In the design, the proposed circuit uses a single active element namely, current follower trans-conductance amplifier (CFTA) and two grounded capacitors as passive elements. The main feature of the proposed circuit is that it can realize all five standard filtering functions such as low pass (LP), band pass (BP), high pass (HP), band stop (BS) and all pass (AP) responses across an explicit high impedance output terminal through the appropriate selection of three inputs. In addition, the same circuit is also capable to simultaneously realize three filtering functions (LP, BP and HP) by the use of single current input signal. Moreover, the proposed structure is suited for low voltage, low power operations and offers the feature of electronic tunability of pole-frequency and quality factor. Further to extend the utility of the proposed circuit block higher order current-mode filters are also realized through direct cascading. A detailed non-ideal and parasitic study is also included. The performance of the circuits has been examined using standard 0.25 μ m CMOS parameters from TSMC.
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Le-Huu, Martin, Michael Grieb, Frederik F. Schrey, H. Schmitt, Volker Haeublein, Anton J. Bauer, Heiner Ryssel i Lothar Frey. "4H-SiC N-MOSFET Logic Circuits for High Temperature Operation". Materials Science Forum 679-680 (marzec 2011): 734–37. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.734.
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The suitability of normally-off 4H-SiC MOSFETs for high temperature operation in logic gates is investigated. Fowler-Nordheim analysis shows a lowering of the effective tunneling barrier height at elevated temperatures. Trap assisted tunneling induced by carbon interstitials is proposed as the responsible mechanism. Nevertheless, reliability of MOS devices even at 400°C is excellent with an extrapolated critical field of 2.69MV/cm for a 10 year time to dielectric breakdown. The switching behavior of logic gates is also characterized between 25°C and 400°C. Using these logic gates, a fully integrated edge triggered flip-flop is build and high temperature operation is demonstrated.
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SOLIMAN, AHMED M. "ADJOINT NETWORK THEOREM AND FLOATING ELEMENTS IN THE NAM". Journal of Circuits, Systems and Computers 18, nr 03 (maj 2009): 597–616. http://dx.doi.org/10.1142/s0218126609005307.
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Although the adjoint network theorem preserves all the circuit properties it does not, however, guarantee that the floating property of an element is maintained. In other words, the adjoint of a floating element may not be floating and vice-versa a nonfloating element may have an adjoint floating element as will be explained in this paper. An important and new property of the Nodal Admittance Matrix (NAM) is that it can identify any element as a floating or nonfloating. The four floating basic building blocks including the nullor are tabulated. It is shown that the nullor and the Voltage Mirror (VM)–Current Mirror (CM) pair are self adjoint. The other two floating elements namely Nullator–CM pair and the VM–Norator pair are adjoint to each other. The NAM of the Op Amp family and Current Conveyor (CCII) family are also given. Two examples are given demonstrating the generation of two families of CCII filters from two known two-CCII filter circuits with demonstration of the floatation property in each of the two filters. Although the paper has a tutorial nature it also includes new important results.
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Thrasher, Bradley A., Michael A. Skurski, Ken E. Souders i James M. Parisi. "Microwave Characterization of a Thick Film System for Hybrid Packaging Applications". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, CICMT (1.05.2016): 000203–6. http://dx.doi.org/10.4071/2016cicmt-tha24.
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Abstract Thick film material systems for hybrid applications have existed for many years and have provided the ability to create high density interconnects in industries such as consumer, military, telecommunications and automotive electronic devices. Despite their breadth of applications, thick film hybrid circuits are rarely utilized for microwave/millimeter-wave packaging applications. In this work, the DuPont™ QM44 thick film dielectric is characterized up to 40 GHz. Test samples to characterize this thick film system consisted of the screen-printed QM44 multilayer dielectric and QG150 gold thick film conductor and vias on top of a 96% alumina substrate. Three different fabrication methods were used in the fabrication of the test samples to illustrate the effect of processing techniques on material loss properties, with the conductor lines formed through standard screen printing, chemical etching, and laser ablation. Laser ablation is a technique recently utilized to form transmission line features in low temperature cofired ceramic (LTCC) circuits [1] to increase dimensional precision when compared to standard screen printing. S-parameter measurements of microstrip transmission lines demonstrate a system loss at 30 GHz of approximately 0.8 dB/cm for chemical etching, 0.9 dB/cm for laser ablation, and 1.0 dB/cm for screen printing. Through careful design and good processing, acceptable microwave performance of the QM44 thick film system can be achieved up to 40 GHz.
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Izadnegahdar, Alain, Stephanie L. Booth, David J. Spry i Philip G. Neudeck. "Alternative Setup for Long-Duration Low-Duty-Cycle 600°C Ambient Testing of SiC Integrated Circuits". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2021, HiTEC (1.04.2021): 000076–82. http://dx.doi.org/10.4071/2380-4491.2021.hitec.000076.
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Abstract A scalable, compact oven testbed system for simultaneously evaluating a multitude of high temperature integrated circuits (ICs) for prolonged operating times of up to 600 °C has been prototyped. The new testbed system enables long-duration high temperature testing in sufficient statistical quantities consistent with standard aerospace electronics engineering standards. This setup is comprised of multiple compact ovens housing chips or packages mounted to ceramic circuit boards. Each oven is a compact 15.2 cm length by 15.2 cm width by 12.7 cm depth with a maximum 400 Watts of heating power. The custom-made silicon oxide ceramic heating block inside each oven is based on a 3D printed design adapted for the easy insertion of the IC device under test (DUT). This innovative design provides the quick insertion of ICs with or without a ceramic package into a 600 °C environment by utilizing a movable 11.43 cm long ceramic substrate with electrical traces extending from the oven hot zone to external standard plastic-based board connectors. Another key oven design feature is the minimization of the DUT exposure to electromagnetic interference (EMI) by utilizing a filtered DC power source to reduce heating element noise. Additionally, the ovens can be configured in a parallel arrangement allowing global data monitoring over a single industrial RS422 serial port. This feature is important for scaling up to test multiple ICs semi-simultaneously. A USB serial port is provided to independently control the operating parameters of each oven such as the oven target temperature and oven ramp rate. The oven temperature can reach up to 600 °C with a confirmed +/− 4 °C maximum deviation across the test zone region. The ramp rate can be programmed from 1 °C/minute up to 10 °C/minute. Furthermore, a programmable switchboard is used to interface with the DUT. This switchboard comprises a National Instruments Peripheral Component Interconnect eXtension for Instrumentation (NI PXI) system and a breakout board to send and receive power, analog or digital test signals. By using this unique oven testbed system, a variety of ICs can now be tested in parallel using the same test components configured for a diverse set of requirements.
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Roongmuanpha, Natchanai, Worapong Tangsrirat i Tattaya Pukkalanun. "Single VDGA-Based Mixed-Mode Universal Filter and Dual-Mode Quadrature Oscillator". Sensors 22, nr 14 (15.07.2022): 5303. http://dx.doi.org/10.3390/s22145303.
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This article presents the circuit designs for a mixed-mode universal biquadratic filter and a dual-mode quadrature oscillator, both of which use a single voltage differencing gain amplifier (VDGA), one resistor, and two capacitors. The proposed circuit has the following performance characteristics: (i) simultaneous implementation of standard biquadratic filter functions with three inputs and two outputs in all four possible modes, namely, voltage-mode (VM), current-mode (CM), trans-admittance-mode (TAM), and trans-impedance-mode (TIM); (ii) electronic adjustment of the natural angular frequency and independently single-resistance controllable high-quality factor; (iii) performing a dual-mode quadrature oscillator with simultaneous voltage and current output responses; (iv) orthogonal resistive and/or electronic control of the oscillation condition and frequency; (v) employing all grounded passive components in the quadrature oscillator function; and (vi) simpler topology due to the use of a single VDGA. VDGA non-idealities and parasitic elements are also investigated and analyzed in terms of their influence on circuit performance. To prove the study hypotheses, computer simulations with TSMC 0.18 μm CMOS technology and experimental confirmatory testing with off-the-shelf integrated circuits LM13600 have been performed.
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Le-Huu, Martin, Frederik F. Schrey, Michael Grieb, H. Schmitt, Volker Haeublein, Anton J. Bauer, Heiner Ryssel i L. Frey. "NMOS Logic Circuits Using 4H-SiC MOSFETs for High Temperature Applications". Materials Science Forum 645-648 (kwiecień 2010): 1143–46. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1143.
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Normally-off 4H-SiC MOSFETs are used to build NMOS logic gates intended for high temperature operation. The logic gates are characterized between 25°C and 500°C. Stable gate operation for more than 200h at 400°C in air is demonstrated. The excellent MOS reliability is quantified using I-V curves to dielectric breakdown and constant voltage stress to breakdown at 400°C. Although the effective tunneling barrier height B for electrons lowers to 2eV at 400°C, the extrapolated lifetime from constant voltage stress to breakdown measurements is longer than 105h at 400°C for typical logic gate operating field strength of 2MV/cm.
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Ochi, Atsuhiko, Toru Tanimori, Yuji Nishi, Shunsuke Aoki i Yasuro Nishi. "Development of an ultra-fast data-acquisition system for a two-dimensional microstrip gas chamber". Journal of Synchrotron Radiation 5, nr 3 (1.05.1998): 1119–22. http://dx.doi.org/10.1107/s0909049597019018.
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A high-performance data-acquisition system has been developed in order to obtain time-resolved sequential images from a two-dimensional microstrip gas chamber (MSGC). This was achieved using fully digital processing with a synchronized pipeline method. Complex logical circuits for processing large numbers of signals are mounted on a small number of complex programmable logic devices. The system is operated with a 10 MHz synchronous clock, and has the capability of handling more than 3 × 106 counts s−1 for asynchronous events. The system was examined using a 5 × 5 cm MSGC and the recently developed 10 × 10 cm MSGC (1024 outputs); the anticipated performances were achieved.
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Schreve, Michiel A., Eline Huizing, Steven Kum, Jean-Paul P. M. de Vries, Gert J. de Borst i Çağdaş Ünlü. "Volume Flow and Peak Systolic Velocity of the Arteriovenous Circuit in Patients after Percutaneous Deep Venous Arterialization". Diagnostics 10, nr 10 (28.09.2020): 760. http://dx.doi.org/10.3390/diagnostics10100760.
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Percutaneous deep venous arterialization (pDVA) is a developing technique for limb salvage in patients with chronic limb-threatening ischemia by creating an arteriovenous (AV) circuit. After pDVA, patency of the AV circuit is evaluated using duplex ultrasound (DUS) imaging. Peak systolic velocity (PSV) and volume flow (VF) values for maintaining a patent AV circuit are undefined; therefore, guidance about when a reintervention should be performed is lacking. The objective of this study was to interpret post-pDVA PSV and VF values in relation to AV circuit preservation. This was performed by analyzing DUS results of 22 post-pDVA patients. A total of 670 PSV and 623 VF measurements were collected. A PSV value of ≤55 cm/s and a VF value of ≤195 mL/min were found predictive for failure. The reliability of PSV and VF measurements in patent AV-circuits was good (intraclass correlation coefficient; PSV, 0.85; VF, 0.88). In conclusion, this study is the first to analyze DUS measurements in post-pDVA patients and showed that DUS can be used to anticipate for failure. The thresholds found can be used to help interpret DUS measurements in post-pDVA patients. More research in a larger patient population is needed to prospectively validate these thresholds.
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Gfroerer, Tim, Michael Adenew i Ella Williams. "Sunny with a Chance of Servos: Solar-Powered Arduinos". Physics Teacher 60, nr 9 (grudzień 2022): 724–26. http://dx.doi.org/10.1119/5.0065597.
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The Arduino microcontroller is finding its way into labs throughout undergraduate physics curricula, from introductory courses to a variety of beyond-the-first-year laboratory classes. At Davidson College, we use Arduinos in a gateway STEM course for students who are interested in energy and the environment. Students learn to build simple circuits and write the accompanying Arduino code to control the temperature in solar-powered model buildings. To make the models fully solar powered, the Arduino itself must be powered by the Sun—no batteries allowed! Hence, we replace the 9-V battery that is usually used to power an Arduino with a 13.5 cm × 12.5 cm 9-V solar panel (DFRobot part #FIT0330), which can generate a maximum short-circuit current of approximately 200 mA. We find that the solar panel works well for most tasks, including temperature measurements, liquid-crystal display (LCD) illumination, and SD card module operation, but cannot generate enough power to drive a servo motor, which needs several hundred milliamps. For these situations, a 9-V, 1-F capacitor connected in parallel with the solar panel can store energy during the rest period between brief high-current operations and supplement the solar panel when higher power is required.
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ISHIBASHI, T., Y. YAMAUCHI, E. SANO, H. NAKAJIMA i Y. MATSUOKA. "BALLISTIC COLLECTION TRANSISTORS AND THEIR APPLICATIONS". International Journal of High Speed Electronics and Systems 05, nr 03 (wrzesień 1994): 349–79. http://dx.doi.org/10.1142/s0129156494000152.
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We describe the design, fabrication and application of ballistic collection transistors (BCTs) in which electron velocity overshoot is introduced in the collector of a GaAs-based heterojunction bipolar transistor. The guideline for the BCT design is the effective confinement of electrons to the Γ-valley, as simulated by Monte Carlo analysis, and the control of electron energy is accomplished basically with an i-p+-n+ doping profile. Microwave characterization demonstrates the existence of significant overshoot and cutoff frequencies higher than 100 GHz at collector current densities in the mid 104 A/cm 2 range for a typical BCT structure. Some high speed integrated circuits implemented with BCTs include a selector circuit that operates at bit rates up to 40 Gb/s, a dynamic frequency divider with divide-by-four function up to 50 GHz and a broadband preamplifier having an S21 bandwidth as high as 40 GHz.
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KRASILENKO, VLADIMIR, YURCHUK NATALIYA i ALEXANDER LAZAREV. "THE NEW BASIC REALIZATIONS OF OPERATIONS “EQUIVALENCE” OF NEURO-FUZZY AND BIOINSPIRED NEURO-LOGICS TO CREATE HARDWARE ACCELERATORS OF ADVANCED EQUIVALENTAL MODELS OF NEURAL STRUCTURES AND MACHINE VISION SYSTEMS". Herald of Khmelnytskyi National University 303, nr 6 (grudzień 2021): 153–66. http://dx.doi.org/10.31891/2307-5732-2021-303-6-153-166.
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The perspective of neural networks equivalental models (EM) base on vector-matrix procedure with basic operations of continuous and neuro-fuzzy logic (equivalence, absolute difference) are shown. Capacity on base EMs exceeded the amount of neurons in 4-10 times. This is larger than others neural networks paradigms. Amount neurons of this neural networks on base EMs may be 10 – 100 thousand. The base operations in EMs are normalized equivalence operations. The family of new operations “equivalence” and “non-equivalence” of neuro-fuzzy logic’s, which we have elaborated on the based of such generalized operations of fuzzy-logic’s as fuzzy negation, t-norm and s-norm are shown. Generalized rules of construction of new functions (operations) “equivalence” which uses operations of t-norm and s-norm to fuzzy negation are proposed. Despite the wide variety of types of operations on fuzzy sets and fuzzy relations and the related variety of new synthesized equivalence operations based on them, it is possible and necessary to select basic operations, taking into account their functional completeness in the corresponding algebras of continuous logic, as well as their most effective circuitry implementations. Among these elements the following should be underlined: 1) the element which fulfills the operation of limited difference; 2) the element which algebraic product (intensifier with controlled coefficient of transmission or multiplier of analog signals); 3) the element which fulfills a sample summarizing (uniting) of signals (including the one during normalizing). The basic element of pixel cells for the construction of hardware accelerators EM NM is a node on the current-reflecting mirrors (CM), which implements the operation of a limited difference (LD) of continuous logic (CL). Synthesized structures which realize on the basic of these elements the whole spectrum of required operations: t-norm, s-norm and new operations – “equivalence” are shown. These realizations on the basic of CMOS transistors current mirror represent the circuit with analog and time-pulse optical input signals. Possibilities of “equivalence” circuits synthesis by such functions limited difference cells are shown. Such circuits consist of several dozen CMOS transistors, have low power supply voltage (1.8…3.3V), the range of an input photocurrent is 0.1…24 μA, the transformation time is less than 1 μs, low power consumption (microwatts). The circuits and the simulation results of their design with OrCAD are shown.
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Morris, Rhiannon, Holly Warren i Marc in het Panhuis. "Celery Electronics". MRS Advances 5, nr 16 (2020): 847–53. http://dx.doi.org/10.1557/adv.2020.133.
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ABSTRACTPlants produce energy in a sustainable way, they are very effective in converting light energy into a useable form. Utilising certain parts of plants in technology could become an efficient way to enhance energy production and improve sustainability. Integrating plants with technology would offer a ‘green’ way of producing elements for electronic circuits and reduce heavy metal waste. In this paper, we demonstrate that conducting polymers can be incorporated into living system such as celery. Electrical impedance analysis was used to establish the conductivity of celery with a conducting polymer (PEDOT:PSS) into its vascular system. It was demonstrated that electronic celery exhibited conductivity values of up to 0.55 ± 0.03 S/cm. This conductivity value was sufficient to demonstrate the potential of celery electronics where celery stalks are used as electrodes in simple circuits.
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Olivero, Massimo, Davinson Mariano da Silva, Luciana Reyes Pires Kassab i Anderson S. L. Gomes. "Amplification Properties of Femtosecond Laser-Written Er3+/Yb3+ Doped Waveguides in a Tellurium-Zinc Glass". Advances in Optical Technologies 2013 (12.09.2013): 1–5. http://dx.doi.org/10.1155/2013/621018.
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We report on the fabrication and characterization of active waveguides in a TeO2-ZnO glass sample doped with Er3+/Yb3+ fabricated by direct laser writing with a femtosecond laser delivering 150 fs pulses at 1 kHz repetition rate. The waveguides exhibit an internal gain of 0.6 dB/cm at 1535 nm, thus demonstrating the feasibility of active photonics lightwave circuits and lossless components in such a glass composition.
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Maskowitz, J. V., W. E. Rhoden, D. R. Kitchen, R. E. Omlor i P. F. Lloyd. "Preparation of integrated circuits for TEM electromigration in situ studies". Proceedings, annual meeting, Electron Microscopy Society of America 44 (sierpień 1986): 882–83. http://dx.doi.org/10.1017/s0424820100145753.
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The fabrication of the aluminum bridge test vehicle for use in the crystallographic studies of electromigration involves several photolithographic processes, some common, while others quite unique. It is most important to start with a clean wafer of known orientation. The wafers used are 7 mil thick boron doped silicon. The diameter of the wafer is 1.5 inches with a resistivity of 10-20 ohm-cm. The crystallographic orientation is (111).Initial attempts were made to both drill and laser holes in the silicon wafers then back fill with photoresist or mounting wax. A diamond tipped dentist burr was used to successfully drill holes in the wafer. This proved unacceptable in that the perimeter of the hole was cracked and chipped. Additionally, the minimum size hole realizable was > 300 μm. The drilled holes could not be arrayed on the wafer to any extent because the wafer would not stand up to the stress of multiple drilling.
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Schaeberle, Michael D., David D. Tuschel i Patrick J. Treado. "Raman Chemical Imaging of Microcrystallinity in Silicon Semiconductor Devices". Applied Spectroscopy 55, nr 3 (marzec 2001): 257–66. http://dx.doi.org/10.1366/0003702011951867.
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Silicon integrated circuits are fabricated by the creation of complex layered structures. The complexity of these structures provides many opportunities for impurities, improperly annealed dopants, and stress effects to cause device contamination and failure. Nondestructive metrology techniques that rapidly and noninvasively screen for defects and relate silicon device structure to device performance are of value. We describe the first use of a liquid crystal tunable filter (LCTF) Raman chemical imaging microscope to assess the crystallinity of silicon semiconductor integrated circuits in a rapid and nondestructive manner without the need for sample preparation. The instrument has demonstrated lateral spatial resolving power of better than 250 nm and is equipped with a tunable imaging spectrometer having a spectral bandpass of 7.6 cm−1. The instrument rapidly produces high-definition Raman images where each image pixel contains a high-quality Raman spectrum. When combined with powerful processing strategies, the Raman chemical imaging system has demonstrated spectral resolving power of 0.03 cm−1 in a test silicon semiconductor wafer fabricated by using ion implantation. In addition, we have applied Raman chemical imaging for volumetric Raman imaging by analyzing the surface distribution of polycrystalline thin film structures. The approaches described here for the first time are generally applicable to the nondestructive metrology of silicon and compound semiconductor devices.