Rozprawy doktorskie na temat „Charge storage memory”

This thesis presents an investigation into a novel group of GaAs charge storage devices. These devices, which are an integration of bipolar and junction field effect transistor structures were conceived, designed, fabricated, and tested within this study. The purpose was to analyse new types of charge storage devices, which are suitable for fabrication and lead to the development of dynamic and nonvolatile memories in III-V compound semiconductors. Currently, III-V semiconductor storage devices consist only of capacitors, where data is destroyed during reading and electrical erasure is difficult. In this work, four devices types were demonstrated that exhibit nondestructive reading, and three of the prototypes can be electrically erased. All types use the junction field effect transistor (JFET) for charge sensing, with each having different bipolar or epitaxial layer structure controlling the junction gate. The bottom epitaxial layer in each case served as the JFET channel. Two of the device types have three alternately doped layers, while the remaining two have four alternately doped layers. In all cases, removal of majority carriers from the middle layers constitutes stored charge. The missing carriers deplete the current carrying a region of the JFET channel. Drain current of the JFET becomes an indicator of stored charge. The basic function of each JFET memory element type is independent of interchanging n- and p- type doping within the structure type. Some performance advantage can be realized, however, by sensing with an n-type channel as compared to p- type due to increased carrier mobility. All device types exhibit storage time characteristics of order ten seconds. Devices are constructed in epitaxial layers grown by molecular beam epitaxy (MBE) reactors. The design of the epitaxial layers is an intrinsic part, together with the electrical design, of the storage device concept. These concepts are implemented first with photolithography masks which are used in device fabrication. The fabrication methods employ wet chemical etching and ohmic metal liftoff techniques. Electrical dc and charge retention time characteristics along with functionality read/write operations for the memory element group are measured using commercial electronic test equipment.

L'evolution des memoires a semiconducteurs et en particulier de la famille eprom (erasable read only memory) est liee a l'identification des phenomenes determinants du processus de perte de la charge electronique stockee. Les cellules etudiees ici sont toutes proches des points de fonctionnement de filieres industrialisees ou en cours de developpement (de 4 a 256 megabits). On distingue deux mecanismes de perte de charge. Le premier est une fonction de la nature des dielectriques presents dans la structure et des lois qui regissent la conduction qui leur est associee. Le second est lie a la migration des ions alcalins dans la cellule. Partant de l'analyse des proprietes de la tricouche ono (oxyde nitrure oxyde) et en emettant l'hypothese de l'injection d'electrons en fin d'ecriture, un modele de perte de charge est propose. Il est base sur l'emission electronique assistee en temperature et la migration des electrons a travers l'ono. Les mesures de perte de charge montrent qu'il ne faut pas descendre, dans la realisation de l'ono, en deca de l'epaisseur tunnel de chaque couche et que l'obtention de couche d'epaisseur homogene et stchiometrique ameliore la fiabilite du dispositif. Cette analyse conduit, de meme, a la proposition d'un dielectrique adapte aux applications tres avancees. Forme par l'association de nitrure et d'oxyde, le no apparait comme un candidat interessant les generations eprom et flash eprom 256 mb. L'etude des contaminants ioniques a mis en uvre la methode tvs, qui s'avere un outil puissant, permettant l'evaluation rapide et precise de la densite d'ions mobile dans les dielectriques epais. Une solution economiquement viable a ete mise au point pour prevenir les effets d'une eventuelle contamination sur le plan memoire. Il s'agit de la juxtaposition judicieuse d'un verre au phosphore et d'un verre au bore et au phosphore

L'objectif de ces travaux de thèse est d'évaluer les performances en programmation/cyclage/rétention d'une cellule mémoire SONOS basée sur une architecture split gate très innovante développée par STMicroelectronics, l'eSTM (embedded Select in Trench Memory). Dans un premier temps, nous expliquons la réalisation de cette mémoire SONOS qui est basée sur une modification de la mémoire eSTM à grille flottante, cette modification se faisant sans coût supplémentaire. Dans un second temps, nous étudions les mécanismes de programmation et d'effacement les plus performants pour cette mémoire ce qui nous amène aussi à proposer une nouvelle architecture de mémoire SONOS. Dans un troisième temps, nous caractérisons électriquement les phases de programmation de la cellule SONOS eSTM pour les deux architectures disponibles : dual gate et overlap. Pour la mémoire dual gate, les deux cellules mémoires de part et d'autre du transistor de sélection ont chacune leur propre empilement de grille « ONO/grille de contrôle ». Pour la mémoire overlap, la couche ONO est commune aux deux cellules mémoires. Même si cette couche est partagée, la mémorisation de l'information dans l'ONO est localisée uniquement sous la grille de contrôle concernée grâce à la nature discrète du piégeage des charges. Le mécanisme mis en œuvre pour les opérations d'écriture et d'effacement est d'injection de porteurs chauds et nous détaillons l'optimisation des polarisations (différentes pour les deux architectures disponibles) de drain et de grille de sélection qui permettent de définir les tensions de seuil écrite et effacée. Nous effectuons alors des tests d'endurance jusqu'à un million de cycles pour les deux architectures. Finalement, nous menons une étude en rétention et en de pompage de charge pour connaitre la qualité d'oxyde à l'interface de nos cellules. Dans un quatrième temps, nous cherchons à mieux comprendre le fonctionnement du transistor mémoire et la variabilité de l'eSTM à l'aide simulations TCAD et de mesures électriques sur des structures de géométries variées
The aim of this thesis work is to evaluate the performance in programming/cycling/retention of a SONOS memory cell based on a highly innovative split-gate architecture developed by STMicroelectronics, the eSTM™ (embedded Select in Trench Memory). Firstly, we explain the realization of this SONOS memory, which is based on a process step modification of the floating gate eSTM™ memory, with this modification carried out without additional cost.Secondly, we investigate the most efficient program and erase mechanisms for this memory, which also leads us to propose a new SONOS memory architecture. Thirdly, we electrically characterize the P/E activations of the SONOS eSTM™ cell for the two available architectures: dual gate and overlap. For dual gate memory, both memory cells on either side of the selection transistor have their own "ONO/control gate" stack. For overlap memory, the ONO layer is common to both memory cells. Even though this layer is shared, the information storage in ONO is localized only under the relevant control gate due to the discrete nature of charge trapping. The mechanism implemented for write and erase operations is carrier hot injection, and we detail the optimization of biases (different for the two available architectures) of the drain and select gate, which define the written and erased threshold voltages. We then perform endurance tests up to one million cycles for both architectures. Finally, we conduct a study on retention and charge pumping to assess the oxide quality at the interface of our cells. In a fourth phase, we seek to better understand the operation of the memory transistor and the variability of eSTM™ using TCAD simulations and electrical measurements on structures with various geometries

In dieser Arbeit werden Speichertransistoren mit Oxid-Nitrid-Oxid-Speicherschicht und lokaler Ladungsspeicherung untersucht, die zur nichtflüchtigen Speicherung von Informationen genutzt werden. Charakteristisch für diese Transistoren ist, dass an beiden Enden des Transistorkanals innerhalb der Isolationsschicht Informationen in Form von Ladungspaketen unabhängig und getrennt voneinander gespeichert werden. Für das Auslesen, Programmieren und Löschen der Speichertransistoren werden die physikalischen Hintergründe diskutiert und grundlegende Algorithmen zur Implementierung dieser Operationen auf einer typischen Speicherfeldarchitektur aufgezeigt. Für Standard-MOS-Transistoren wird ein Kurzkanal-Schwellspannungsmodell abgeleitet und analytisch gelöst. Anhand dieser Modellgleichung werden die bekannten Kurzkanaleffekte betrachtet. Weiterhin wird ein Modell zur Berechnung des Drainstroms von Kurzkanaltransistoren im Subthreshold-Arbeitsbereich abgeleitet und gezeigt, dass sich die Drain-Source-Leckströme bei Kurzkanaltransistoren vergrößern. Die Erweiterung des Schwellspannungsmodells für Standard-MOS-Transistoren auf den Fall der lokalen Ladungsspeicherung innerhalb der Isolationsschicht erlaubt die Ableitung eines Schwellspannungsmodells für Oxid-Nitrid-Oxid-Transistoren mit lokaler Ladungsspeicherung. Dieses Modell gestattet die qualitative und quantitative Diskussion der Erhöhung der Schwellspannung durch die lokale Injektion von Ladungsträgern beim Programmiervorgang. Weiterhin ist es mit diesem Modell möglich, die Trennung der an beiden Kanalenden des Transistors gespeicherten Informationen beim Auslesevorgang qualitativ zu erklären und diese Bittrennung in Abhängigkeit von der Drainspannung zu berechnen. Für Langkanalspeichertransistoren wird eine analytische Näherungslösung des Schwellspannungsmodells angegeben, während das Kurzkanalverhalten durch die numerische Lösung der Modellgleichung bestimmt werden kann. Für Langkanalspeichertransistoren wird ein Subthreshold-Modell zur Berechnung des Drainstroms abgeleitet. Dieses Modell zeigt, dass sich die Leckströme von programmierten Speichertransistoren im Vergleich zu Standard-MOS-Transistoren gleicher Schwellspannung vergrößern. Die Ursache dieses Effekts, die Verringerung der Subthreshold-Steigung von Transistoren im programmierten Zustand, wird analysiert. Für einige praktische Beispiele wird die Anwendung der hergeleiteten Modellgleichungen beim Entwurf von Flash-Speichern demonstriert.
In this work, memory transistors with an oxide-nitride-oxide trapping-layer and local charge storage, which are used for non-volatile information storage, are examined. Characteristic for these transistors is an independent and separated storage of information by charge packages, located at both sides of the transistor channel, in the insulation layer. The physical backgrounds for reading, programming and erasing the memory transistors are discussed, and basic algorithms are shown for implementing these operations on a typical memory array architecture. For standard MOS-transistors a short channel threshold model is derived and solved analytically. By using these model equations, the known short channel effects are considered. Further, a model for calculating the drain current of short channel transistors in the subthreshold operation region is derived. This model is used to show the increase of drain-source leakage currents in short channel transistors. By extending the standard MOS-transistor threshold voltage model for local charge storage in the insulation layers, the derivation of a threshold voltage model for oxide-nitride-oxide transistors with local charge storage is enabled. This model permits the quantitative and qualitative discussion of the increase in threshold voltage caused by local injection of charges during programming. Furthermore, with this model, the separation of the information, which are stored at both sides of the transistor channel, in the read-out operation is explained qualitatively, and the bit separation is calculated dependent on the drain voltage. For long channel memory transistors an analytical approximation of the threshold voltage model is given, whereas the short channel behaviour can be determined by solving the model equation numerically. For long channel memory transistors, a subthreshold model for calculating the drain current is derived. This model shows the increase in leakage current of programmed memory transistors in comparision to standard MOS-transistors. The root cause of this effect, the reduced subthreshold swing of transistors in the programmed state, is analysed. The application of the derived model equations for the development of flash memories is demonstrated with some practical examples.

In dieser Arbeit werden Speichertransistoren mit Oxid-Nitrid-Oxid-Speicherschicht und lokaler Ladungsspeicherung untersucht, die zur nichtflüchtigen Speicherung von Informationen genutzt werden. Charakteristisch für diese Transistoren ist, dass an beiden Enden des Transistorkanals innerhalb der Isolationsschicht Informationen in Form von Ladungspaketen unabhängig und getrennt voneinander gespeichert werden. Für das Auslesen, Programmieren und Löschen der Speichertransistoren werden die physikalischen Hintergründe diskutiert und grundlegende Algorithmen zur Implementierung dieser Operationen auf einer typischen Speicherfeldarchitektur aufgezeigt. Für Standard-MOS-Transistoren wird ein Kurzkanal-Schwellspannungsmodell abgeleitet und analytisch gelöst. Anhand dieser Modellgleichung werden die bekannten Kurzkanaleffekte betrachtet. Weiterhin wird ein Modell zur Berechnung des Drainstroms von Kurzkanaltransistoren im Subthreshold-Arbeitsbereich abgeleitet und gezeigt, dass sich die Drain-Source-Leckströme bei Kurzkanaltransistoren vergrößern. Die Erweiterung des Schwellspannungsmodells für Standard-MOS-Transistoren auf den Fall der lokalen Ladungsspeicherung innerhalb der Isolationsschicht erlaubt die Ableitung eines Schwellspannungsmodells für Oxid-Nitrid-Oxid-Transistoren mit lokaler Ladungsspeicherung. Dieses Modell gestattet die qualitative und quantitative Diskussion der Erhöhung der Schwellspannung durch die lokale Injektion von Ladungsträgern beim Programmiervorgang. Weiterhin ist es mit diesem Modell möglich, die Trennung der an beiden Kanalenden des Transistors gespeicherten Informationen beim Auslesevorgang qualitativ zu erklären und diese Bittrennung in Abhängigkeit von der Drainspannung zu berechnen. Für Langkanalspeichertransistoren wird eine analytische Näherungslösung des Schwellspannungsmodells angegeben, während das Kurzkanalverhalten durch die numerische Lösung der Modellgleichung bestimmt werden kann. Für Langkanalspeichertransistoren wird ein Subthreshold-Modell zur Berechnung des Drainstroms abgeleitet. Dieses Modell zeigt, dass sich die Leckströme von programmierten Speichertransistoren im Vergleich zu Standard-MOS-Transistoren gleicher Schwellspannung vergrößern. Die Ursache dieses Effekts, die Verringerung der Subthreshold-Steigung von Transistoren im programmierten Zustand, wird analysiert. Für einige praktische Beispiele wird die Anwendung der hergeleiteten Modellgleichungen beim Entwurf von Flash-Speichern demonstriert
In this work, memory transistors with an oxide-nitride-oxide trapping-layer and local charge storage, which are used for non-volatile information storage, are examined. Characteristic for these transistors is an independent and separated storage of information by charge packages, located at both sides of the transistor channel, in the insulation layer. The physical backgrounds for reading, programming and erasing the memory transistors are discussed, and basic algorithms are shown for implementing these operations on a typical memory array architecture. For standard MOS-transistors a short channel threshold model is derived and solved analytically. By using these model equations, the known short channel effects are considered. Further, a model for calculating the drain current of short channel transistors in the subthreshold operation region is derived. This model is used to show the increase of drain-source leakage currents in short channel transistors. By extending the standard MOS-transistor threshold voltage model for local charge storage in the insulation layers, the derivation of a threshold voltage model for oxide-nitride-oxide transistors with local charge storage is enabled. This model permits the quantitative and qualitative discussion of the increase in threshold voltage caused by local injection of charges during programming. Furthermore, with this model, the separation of the information, which are stored at both sides of the transistor channel, in the read-out operation is explained qualitatively, and the bit separation is calculated dependent on the drain voltage. For long channel memory transistors an analytical approximation of the threshold voltage model is given, whereas the short channel behaviour can be determined by solving the model equation numerically. For long channel memory transistors, a subthreshold model for calculating the drain current is derived. This model shows the increase in leakage current of programmed memory transistors in comparision to standard MOS-transistors. The root cause of this effect, the reduced subthreshold swing of transistors in the programmed state, is analysed. The application of the derived model equations for the development of flash memories is demonstrated with some practical examples

The main objective of this research is to provide an efficient and reliable method for using multi-level cell (MLC) phase-change memory (PCM) as a main memory. As DRAM scaling approaches the physical limit, alternative memory technologies are being explored for future computing systems. Among them, PCM is the most mature with announced commercial products for NOR flash replacement. Its fast access latency and scalability have led researchers to investigate PCM as a feasible candidate for DRAM replacement. Moreover, the multi-level potential of PCM cells can enhance the scalability by increasing the number of bits stored in a cell. However, the two major challenges for adopting MLC PCM are the limited write endurance cycle and the resistance drift issue. To alleviate the negative impact of the limited write endurance cycle, this thesis first introduces a secure wear-leveling scheme called Security Refresh. In the study, this thesis argues that a PCM design not only has to consider normal wear-out under normal application behavior, most importantly, it must take the worst-case scenario into account with the presence of malicious exploits and a compromised OS to address the durability and security issues simultaneously. Security Refresh can avoid information leak by constantly migrating their physical locations inside the PCM, obfuscating the actual data placement from users and system software. In addition to the secure wear-leveling scheme, this thesis also proposes SAFER, a hardware-efficient multi-bit stuck-at-fault error recovery scheme which can function in conjunction with existing wear-leveling techniques. The limited write endurance leads to wear-out related permanent failures, and furthermore, technology scaling increases the variation in cell lifetime resulting in early failures of many cells. SAFER exploits the key attribute that a failed cell with a stuck-at value is still readable, making it possible to continue to use the failed cell to store data; thereby reducing the hardware overhead for error recovery. Another approach that this thesis proposes to address the lower write endurance is a hybrid phase-change memory architecture that can dynamically classify, detect, and isolate frequent writes from accessing the phase-change memory. This proposed architecture employs a small SRAM-based Isolation Cache with a detection mechanism based on a multi-dimensional Bloom filter and a binary classifier. The techniques are orthogonal to and can be combined with other wear-out management schemes to obtain a synergistic result. Lastly, this thesis quantitatively studies the current art for MLC PCM in dealing with the resistance drift problem and shows that the previous techniques such as scrubbing or error correction schemes are incapable of providing sufficient level of reliability. Then, this thesis proposes tri-level-cell (3LC) PCM and demonstrates that 3LC PCM can be a viable solution to achieve the soft error rate of DRAM and the performance of single-level-cell PCM.

L’objectif de ces travaux de thèse a été de développer une nouvelle génération de point mémoire de type EEPROM pour les applications à haute fiabilité et à haute densité d’intégration. Dans un premier temps, une cellule mémoire très innovante développée par STMicroelectronics – eSTM (mémoire à stockage de charges de type Splitgate avec transistor de sélection vertical enterré) – a été étudiée comme cellule de référence. Dans une deuxième partie, dans un souci d’améliorer la fiabilité de la cellule eSTM et de permettre une miniaturisation plus agressive de la cellule EEPROM, une nouvelle architecture mémoire a été proposée : la cellule BitErasable. Elle a montré une excellente fiabilité et a permis d’apporter des éléments de compréhension sur les mécanismes de dégradation présents dans ces dispositifs mémoires à transistor de sélection enterré. Cette nouvelle architecture offre de plus la possibilité d’effacer les cellules d’un plan mémoire de façon individuelle : bit à bit. Conscient du grand intérêt que présente l’effacement bit à bit, un nouveau mécanisme d’effacement pour injection de trous chauds a été proposé pour la cellule eSTM. Il a montré des performances et un niveau de fiabilité parfaitement compatible avec les exigences industrielles des applications Flash-NOR
The objective of this thesis was to develop a new generation of EEPROM memory for high reliability and high density applications. First, an innovative memory cell developed by STMicroelectronics - eSTM (Split-gate charge storage memory with buried vertical selection transistor) - was studied as a reference cell. In a second part, to improve the reliability of the eSTM cell and to allow a more aggressive miniaturization of the EEPROM cell, a new memory architecture has been proposed: the BitErasable cell. It showed an excellent reliability and allowed to bring elements of under-standing on the degradation mechanisms present in these memory devices with buried selection transistor. This new architecture also offers the possibility to individually erase cells in a memory array: bit by bit. Aware of the great interest of bit-by-bit erasing, a new erasing mechanism by hot hole injection has been proposed for the eSTM cell. It has shown performances and a level of reliability perfectly compatible with the industrial requirements of Flash-NOR applications

I materiali a cambiamento di fase sono calcogenuri a base di tellurio di notevole interesse tecnologico per la realizzazione di memorie ottiche (DVD) e di memorie elettroniche non volatili di nuova concezione, le memorie a cambiamento di fase o PCM. Questi dispositivi si basano su una veloce (50 ns) e reversibile transizione di fase amorfo-cristallo indotta per riscaldamento. Le due fasi corrispondono ai due stati di memoria che possono essere distinti grazie alla grande differenza tra le proprietà ottiche ed elettroniche dell'amorfo e quelle del cristallo. Nonostante il Ge2Sb2Te5 (GST) sia il materiale attualmente usato nelle PCM, si stanno studiando nuovi materiali con una temperatura di cristallizzazione più alta per aumentare la stabilità termica delle PCM. A questo proposito in questa tesi sono state studiate, attraverso simulazioni di dinamica molecolare ab-initio, diverse leghe ad alta temperatura di cristallizzazione con composizione In3Sb1Te2, In13Sb11Te3 e Ga4Sb6Te3. Queste leghe sono state studiate sperimentalmente e proposte come sostituti del GST, ma le proprietà strutturali e l'origine microscopica dell'elevata temperatura di cristallizzazione della fase amorfa di questi composti non è ancora del tutto chiara. Sono stati, quindi, generati modelli di qualche centinaio di atomi della fase amorfa raffreddando dal liquido in centinaia di ps allo scopo di trovare una relazione tra la struttura dell'amorfo e l'alta temperatura di cristallizzazione di queste leghe. La topologia di legame dei modelli amorfi risulta principalmente tetraedrica, molto diversa dalla geometria della fase cristallina che presenta invece intorni ottaedrici. La presenza di strutture tetraedriche nell'amorfo, assenti invece nella fase cristallina, può quindi costituire un ostacolo alla cristallizzazione con l'effetto di innalzare la temperatura di cristallizzazione rispetto al GST che presenta una geometria di legame prevalentemente ottaedrica sia nell'amorfo che nel cristallo. Nella seconda parte di questo lavoro è stato affrontato il problema del drift, che consiste in un aumento della resistenza elettrica della fase amorfa con il tempo. Questo fenomeno rappresenta un problema nelle celle PCM in quanto modifica le caratteristiche elettriche del dispositivo; tuttavia, manca ancora una spiegazione completa del meccanismo microscopico alla base di questo processo. Il drift sembra però legato al fenomeno del rilassamento strutturale che si verifica nei semiconduttori amorfi e che modifica nel tempo gli stati di difetto in prossimità degli edge delle bande di valenza e di conduzione, da cui dipende la conduzione nella fase amorfa. Per studiare il fenomeno del drift sono stati generati modelli di grandi dimensioni (circa duemila atomi) di GeTe amorfo raffreddando dal liquido in 100 ps attraverso simulazioni di dinamica molecolare classica con un potenziale Neural-Network. Una volta rilassati ab-initio, i modelli presentano diversi stati nel gap localizzati su catene di atomi di Ge. Dopo aver riscaldato i modelli a 500 K in modo da accelerare il processo di drift, si osserva una riduzione del numero di catene di Ge e di legami omopolari Ge-Ge con un conseguente allargamento del gap e riduzione dell'ampiezza delle code di Urbach che possono giustificare un aumento della resistenza. Si propone quindi che il drift sia dovuto al rilassamento strutturale della fase amorfa che porta alla riduzione delle catene di legami omopolari di Ge.
Phase change materials based on chalcogenide alloys are of great technological importance because of their use in optical data storage devices (DVDs) and electronic non-volatile memories of new concept, the Phase Change Memory cell (PCM). These applications rely on a fast (50 ns) and reversible change between the crystalline and the amorphous phases upon heating. The two phases correspond to the two states of the memory that can be discriminated thanks to a large difference in their optical and electronic properties. Although Ge2Sb2Te5 (GST) is the compound presently used as active layer in PCMs, alternative materials with a higher crystallization temperature are under scrutiny in order to increase the thermal stability of the PCM devices. In this respect, we analysed, by means of ab-initio molecular dynamics simulations, different high crystallization temperature alloys with composition In3Sb1Te2, In13Sb11Te3 and Ga4Sb6Te3, which have been experimentally proposed as substitute of GST. However, the structural properties and the microscopical reason of the high thermal stability of the amorphous phases of these compounds is still unclear. We, thus, generated models of the amorphous phase of few hundreds of atoms by quenching from the melt in few hundreds of ps aiming at finding out a relation between the structural properties of the amorphous phase and the high crystallization temperature of these alloys. The topology of our amorphous models turned out to be mostly tetrahedral which differs from the octahedral-like geometry of the crystalline phases. The presence of tetrahedral structures in the amorphous which are absent in the crystalline phase, probably hinders the crystallization process resulting in a higher crystallization temperature with respect to GST which display a mostly octahedral-like structures in both amorphous and the crystalline phase. In the second part of this work we addressed the issue of the resistance drift phenomenon, which consists of an increase of the electrical resistance of the amorphous phase with time. This effect is detrimental in PCMs since it changes the electrical characteristics of the devices. This process is believed to be due to an aging of the amorphous phase which modifies during time the defect states in the proximity of the valence and conduction band edges which control the electrical conductivity. The microscopic origin of the structural relaxations leading to the drift is still unknown. To address this problem, we generated large models (about two thousand atoms) of amorphous GeTe by quenching from the melt in 100 ps with classical molecular dynamics simulations by using a neural-network potential. Once relaxed by first principles, the models showed the presence of several in-gap states localized on chains of Ge atoms. After an annealing at 500 K, performed to accelerate the drift process, Ge chains and homopolar Ge-Ge bonds reduce in number resulting in a band gap widening and a reduction of the Urbach tails at the band edges which can account for the increase of the resistance. We thus propose that the resistance drift originates from structural relaxations leading to the removal of Ge chains.

The search for alternate and renewable energy resources as well as the efficient use of energy and development of such systems that can help to save the energy consumption is needed because of exponential growth in world population, limited conventional fossil fuel resources, and to meet the increasing demand of clean and environment friendly substitutes. Hydrogen being the simplest, most abundant and clean energy carrier has the potential to fulfill some of these requirements provided the development of efficient, safe and durable systems for its production, storage and usage. Chemical hydrides, complex hydrides and nanomaterials, where the hydrogen is either chemically bonded to the metal ions or physiosorbed, are the possible means to overcome the difficulties associated with the storage and usage of hydrogen at favorable conditions. We have studied the structural and electronic properties of some of the chemical hydrides, complex hydrides and functionalized nanostructures to understand the kinetics and thermodynamics of these materials. Another active field relating to energy storage is rechargeable batteries. We have studied the detailed crystal and electronic structures of Li and Mg based cathode materials and calculated the average intercalation voltage of the corresponding batteries. We found that transition metal doped MgH2 nanocluster is a material to use efficiently not only in batteries but also in fuel-cell technologies. MAX phases can be used to develop the systems to save the energy consumption. We have chosen one compound from each of all known types of MAX phases and analyzed the structural, electronic, and mechanical properties using the hybrid functional. We suggest that the proper treatment of correlation effects is important for the correct description of Cr2AlC and Cr2GeC by the good choice of Hubbard 'U' in DFT+U method. Hydrogen is fascinating to physicists due to predicted possibility of metallization and high temperature superconductivity. On the basis of our ab initio molecular dynamics studies, we propose that the recent claim of conductive hydrogen by experiments might be explained by the diffusion of hydrogen at relevant pressure and temperature. In this thesis we also present the studies of phase change memory materials, oxides and amorphization of oxide materials, spintronics and sulfide materials.

Dans le domaine de l'enregistrement reversible sur disque optique, la technologie changement de phase concurrence depuis peu la suprematie de l'enregistrement magneto-optique. Dans cette these sont abordes les aspects cles de l'enregistrement a changement de phase. Les alliages a base de tellure entrant dans l'elaboration de ces disques optiques doivent pouvoir passer de facon reversible d'un etat amorphe a un etat cristallin. L'utilisation de trois types de materiaux a ete envisagee. Il s'agit des alliages ternaires gesbte et insbte ainsi que de l'alliage quaternaire aginsbte. Une etude bibliographique des travaux effectues sur ces materiaux a changement de phase est presentee dans cette these. Diverses experimentations (caracterisation structurale, analyse de la cinetique de cristallisation) ont ete effectuees sur quelques compositions. Les comportements optique et thermique des systemes de couches minces utilises en enregistrement optique a changement de phase sont modelises. Les simulations numeriques se revelent etre un outil indispensable et permettent d'optimiser les proprietes du disque optique en ecriture et en lecture. Des prototypes de disques optiques re-inscriptibles a changement de phase sont realises. Ceux elabores a partir d'un alliage de composition ge#2sb#2te#5 donnent les meilleurs resultats. La derniere partie de cette these aborde la faisabilite de disques optiques a plusieurs niveaux d'information disposes sur un meme substrat. Des solutions sont proposees pour l'elaboration d'un disque comportant un niveau d'information pre-enregistre sur lequel est superpose un niveau d'information re-inscriptible. Le cas d'un disque optique a deux niveaux re-inscriptibles a changement de phase est aussi envisage. Ce document constitue une synthese sur l'enregistrement optique a changement de phase et les resultats obtenus permettent d'envisager des applications industrielles. Il ouvre aussi certaines perspectives sur les futures generations de disques optiques.

碩士
國立臺灣科技大學
工程技術研究所
98
Recently, the conventional floating gate memory faces a challenge of scaling down, such as the thinner tunneling oxide suffers from leakage path generation easily after a long duration operation. Therefore, nanocrystal (NC) structure with distributed storage elements was proposed as the next generation structure for nonvolatile memory devices. The nickel film as a charge storage layer for nanocrystal memory was prepared by sputtering method. Device sample subjected to 900℃ annealing for 3min in N2 atmosphere exhibited a significant hysteresis memory window shift of 2.37V and charge density of 7.36×1011cm-2 after 10V voltage sweep. It was also found a memory window shift about 1.06V and the charge loss about 25.35% in the sample after 104sec retention time at a 5V voltage stress. The leakage current obtained from the I-V measurement was 0.439A/cm2 at the gate voltage of -20V. XPS analysis indicated that annealing induced the nickel diffusion to blockage layer and fromed intermetallic compound of Al3Ni. Tin was the other novel element to be used as the charge storage layer for nonvolatile memory. In this study, the tin layer was deposited by sputtering. Device sample subjected to 140℃ annealing for 30min in Ar atmosphere exhibited a significant hysteresis memory window shift of 1.46V and the charge density of 3.10×1011cm-2 after 8V voltage sweep. Under the retention tests, the memory window became 0.81V and the charge loss rate was 38.17% after suffering a 5V stress for 104sec. The leakage current density obtained from the J-E measurement was 1.11×10-2A/cm2 at the gate voltage of -20V. From the result of XPS, it is evident that tin did not diffuse to the blockage layer and existed as SnO in nanocrystal memory.

博士
國立交通大學
電子工程系所
93
Reliability issues in a trapping nitride, localized charge storage flash memory cell are comprehensively investigated in this dissertation. Though the use of a thick bottom oxide and trapping storage concept provides excellent intrinsic charge retention, data loss is found after program/erase (P/E) cycling. Our study shows that trap generation in the bottom oxide during P/E cycling plays a central role. Vt loss in a program-state cell is due to the escape of trapped electrons in the nitride via Frenkel-Poole emission and subsequent oxide trap-assisted tunneling. Interface state annihilation during high-temperature baking would be another source of the observed Vt loss. Vt drift-up in an erase-state cell is the outcome of the tunnel detrapping of cycling-induced positive oxide charges. Furthermore, these positive oxide charges could enhance channel electron tunnel injection and channel-hot-electron injection into the nitride during read operation and thus cause read disturb. Stress-induced interface state growth and transient substrate current are good indicators of cell’s retentivity. All the above regard the charge transport along the vertical direction. On the other hand, lateral migration of excess holes in the trapping nitride dominates the Vt loss in an over-erased cell. Finally, erase speed degradation is studied. It is found that neighboring junction bias would suppress the hot-hole injection efficiency in a nearly punch-through cell. Besides, a cell is hard-to-erase if more electrons reside in the central channel region. Those far electrons are prone to be injected as its neighboring bit is programmed or after P/E cycling.

碩士
國立交通大學
電子研究所
106
In this work, we look into the nitride trapped charge lateral transport in a SONOS cell using a novel random telegraph noise method. The exponential dependence of the random telegraph noise time constant on the local channel potential change is utilized to probe the nitride trapped charge lateral movement. The electric field and temperature dependence of charge lateral transport are analyzed by applying various drain voltages and different bake temperatures to a SONOS cell. We compare our measurement results to different charge transport mechanisms and find thermally assisted trap-to-band tunneling to be the main mechanism of trapped charge lateral transport. Furthermore, the data pattern effect on nitride trapped charge lateral migration in single SONOS cell is investigated using random telegraph noise method and other monitors. The more evident Vth loss in certain stored data pattern is attributed to trapped hole lateral migration in the shared nitride trapping layer.

博士
國立清華大學
材料科學工程學系
94
The nanocrystals embedded in memory devices as charge storage nodes, instead of typical semiconductor floating gate, can effectively solve the issue of data losing due to the leaky paths present in the tunneling oxide. All stored charges are not easily lost through the few leaky paths, since the charges are stored in discretely distributed nanocrystals. The specific charges stored in the nanocrystals nearby a leaky path will just flow away, but others are maintained in the independent nanocrystals. Thus, memory function can be effectively retained. In this thesis, the Ni, Co, NiSi2 and CoSi2 nanocrystals have been fabricated as the charge storage nodes for nonvolatile memory. The fabrication temperature of the Ni and Co nanocrystals is 500 °C. On the other hand, the NiSi2 and CoSi2 nanocrystals are formed during thermal oxidation of a-Si/Ni and a-Si/Co structures at 900 °C. The most important advantage using the metal nanocrystals over their semiconductor counterparts is that the metal nanocrystals do not bear a voltage drop from gate voltage. The characteristic means that all the voltages provided from control gate are dropped to tunnel oxide and control oxide. The operating voltages of the memory devices with conventional floating gate and semiconductor nanocrystals embedded in SiO2 are about 7 V and 5 V, respectively. The metal nanocrystals embedded in the different dielectrics were also studied. By changing the dielectric, the lower operating voltage can be obtained.

碩士
國立臺灣大學
化學工程學研究所
101
Organic filed-effect transistors (OFETs) type memories are especially attractive recently in organic nonvolatile memory devices, due to their advantages of low cost, flexibility, solution processes, non-destructive read-out and architectural compatibility with integrated circuits composed of OFETs. According to the charge storage mechanisms, OFET memory devices can be classified into three types: (i) floating gate memory, (ii) polymer electrets memory, (iii) ferroelectric memory. Among the OFET memories, the floating-gate type memories can potentially be applied to novel device application areas, owing to the charge storage sites can be easily controlled and tuned by varying the size, density and work functions of nanoparticle or nanocrystal species. In this thesis, we explored the OFET memory with three types of charge trapping sites of (1) metal and semiconductor nanocomposites and (2) small molecules, (3) inorganic materials to realize the influence on the characteristics of the memory devices. Organic Nonvolatile Field-Effect Transistor Memory Devices Based on Hybrid Film Composed of Poly(9,9-dioctyl-fluorene-co-bithiophene) and Gold Nanoparticle/Zinc Oxide Nanorod Composites (Chapter 2): We have prepared the OFET memory based on the hybrid layer which was composed of the active layer, poly (9, 9-dioctylfluorene-co-bithiophene) (F8T2), and the charge trapping sites (gold/zinc oxide nanocomposites, Au/ZnO NCs). The effects of Au/ZnO NCs on the electrical memory characteristics of devices were investigated by varied the additions of Au/ZnO NCs. The Au/ZnO NCs primarily dominated the electrons trapping effect in memory behaviors. Moreover, to evaluate the contributions of gold nanoparticles (Au NPs) and zinc oxide nanorods (ZnO NRs) in the Au/ZnO NCs, we also fabricated the devices with gold Au NPs and ZnO NRs, respectively. In Au/ZnO NCs, the ability of electron trapping was caused from Au NPs, while ZnO NRs preferred to be a role of transmitter which helped electron easily transferred and showed a minor effect on memory property. Thus, the memory window of Au/ZnO NCs devices (67.67 V) was larger than that of Au NPs devices (42.84 V) with one and half times. The retention time test of the devices with F8T2/(Au/ZnO NCs) hybrid layer showed the on/off current ratio (Ion/Ioff) of around 102 at least 104 s and the devices could be operated over than 100 cycles with Ion/Ioff of 102 in write-read-erase-read (WRER) cycles test. This device based on Au/ZnO NCs could have potential for the applications of OFET memories. Organic Nonvolatile Field-Effect Transistor Memory Devices Based on Blending Layer Consisted of Poly (methyl methacrylate) and Small Molecules (Chapter 3): We have demonstrated OFET memory devices based on pentacene with the charge trapping layer consisted of poly (methyl methacrylate) (PMMA) and small molecules. The small molecules served as the charge storage sites (floating gate), including tetracyanoquinodimethane (TCNQ) and 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ) for comparison of the electrical characteristics between them. The devices had significant memory characteristics based on TCNQ, including large memory window of 52.5 V, could be operated over than 100 cycles with high on/off ratio of 103 in WRER cycles test, the retention time test could maintain on/off ratio of 102 at least 104 s. There were no significant memory characteristics of the devices based on F4TCNQ, such as small memory window and the on/off states couldn’t be clearly distinguished. The possible reason for the difference between the two species of small molecules was the energy level. However, the devices based on TCNQ could be potentially applied to OFET memories. Organic Nonvolatile Field-Effect Transistor Memory Devices Based on Blending Layer Consisted of Poly (methacrylic acid) and Zinc Oxide (Chapter 4): We have fabricated OFET memory devices based on pentacene with the charge trapping layer composed of poly (methacrylic acid) (PMAA) and zinc oxide (ZnO). The ZnO was used to as the charge storage sites, including ZnO nanoparticles (NPs) and nanorods (NRs) for comparison of the electrical properties between them. The ZnO NRs were synthesized from ZnO NPs. The devices with ZnO NRs showed larger memory windows (60.26 V) than that with ZnO NPs (49.05 V). In retention time test, the devices showed current on/off ratio of around 103 and 102 for ZnO NPs and NRs at least 104 s, respectively. In WRER cycles test, the devices based on ZnO could be operated over than 100 cycles with on/off ratio of around 103. The possible reason for the difference between ZnO NPs and NRs were the size and configuration of them. The devices based on ZnO showed the potential applications for OFET memories.

A method of synthesizing and controlling the size of germanium nanocrystals is developed. A tri-layer metal-insulator-semiconductor (MIS) memory device structure comprising of a thin (~5nm) silicon dioxide (SiO₂) layer grown using rapid thermal oxidation (RTO), followed by a layer of Ge+SiO₂ of varying thickness (3 - 6 nm) deposited using a radio frequency (rf) co-sputtering technique, and a capping SiO₂ layer (50nm) deposited using rf sputtering is investigated. It was verified that the size of germanium (Ge) nanocrystals in the vertical z-direction in the trilayer memory device was controlled by varying the thickness of the middle (cosputtered Ge+SiO₂) layer. From analyses using transmission electron microscopy and capacitance-voltage measurements, we deduced that both electrons and holes are most likely stored within the nanocrystals in the middle layer of the trilayer structure rather than at the interfaces of the nanocrystals with the oxide matrix.
Singapore-MIT Alliance (SMA)

The effect of germanium (Ge) concentration and the rapid thermal oxide (RTO) layer thickness on the nanocrystal formation and charge storage/retention capability of a trilayer metal-insulator-semiconductor device was studied. We found that the RTO and the capping oxide layers were not totally effective in confining the Ge nanocrystals in the middle layer when a pure Ge middle layer was used for the formation of nanocrystals. From the transmission electron microscopy and secondary ion mass spectroscopy results, a significant diffusion of Ge atoms through the RTO and into the silicon (Si) substrate was observed when the RTO layer thickness was reduced to 2.5 nm. This resulted in no (or very few) nanocrystals formed in the system. For devices with a Ge+SiO₂ co-sputtered middle layer (i.e., lower Ge concentration), a higher charge storage capability was obtained than with devices with a thinner RTO layer, and the charge retention time was found to be less than in devices with a thicker RTO layer.
Singapore-MIT Alliance (SMA)

The trends in virtualization as well as multi-core, multiprocessor environments have translated to a massive increase in the amount of main memory each individual system needs to be fitted with, so as to effectively utilize this growing compute capacity. The increasing demand on main memory implies that the main memory devices and their issues are as important a part of system design as the central processors. The primary issues of modern memory are power, energy, and scaling of capacity. Nearly a third of the system power and energy can be from the memory subsystem. At the same time, modern main memory devices are limited by technology in their future ability to scale and keep pace with the modern program demands thereby requiring exploration of alternatives to main memory storage technology. This dissertation exploits dynamic knowledge of memory state and memory data value to improve memory performance and reduce memory energy consumption. A cross-boundary approach to communicate information about dynamic memory management state (allocated and deallocated memory) between software and hardware viii memory subsystem through a combination of ISA support and hardware structures is proposed in this research. These mechanisms help identify memory operations to regions of memory that have no impact on the correct execution of the program because they were either freshly allocated or deallocated. This inference about the impact stems from the fact that, data in memory regions that have been deallocated are no longer useful to the actual program code and data present in freshly allocated memory is also not useful to the program because the dynamic memory has not been defined by the program. By being cognizant of this, such memory operations are avoided thereby saving energy and improving the usefulness of the main memory. Furthermore, when stores write zeros to memory, the number of stores to the memory is reduced in this research by capturing it as compressed information which is stored along with memory management state information. Using the methods outlined above, this dissertation harnesses memory management state and data value information to achieve significant savings in energy consumption while extending the endurance limit of memory technologies.
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