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Artykuły w czasopismach na temat "Charge storage memory"
Mabrook, M. F., Youngjun Yun, C. Pearson, D. A. Zeze i M. C. Petty. "Charge Storage in Pentacene/Polymethylmethacrylate Memory Devices". IEEE Electron Device Letters 30, nr 6 (czerwiec 2009): 632–34. http://dx.doi.org/10.1109/led.2009.2018128.
Pełny tekst źródłaSpassov, Dencho, i Albena Paskaleva. "Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO2/Al2O3 Nanolaminated Stacks". Nanomaterials 13, nr 17 (30.08.2023): 2456. http://dx.doi.org/10.3390/nano13172456.
Pełny tekst źródłaTsoukalas, Dimitris, S. Kolliopoulou, P. Dimitrakis, P. Normand i M. C. Petty. "Nanoparticles for Charge Storage Using Hybrid Organic Inorganic Devices". Advances in Science and Technology 54 (wrzesień 2008): 451–57. http://dx.doi.org/10.4028/www.scientific.net/ast.54.451.
Pełny tekst źródłaGong, Changjie, Xin Ou, Bo Xu, Xuexin Lan, Yan Lei, Jianxin Lu, Yan Chen i in. "Enhanced charge storage performance in AlTi4Ox/Al2O3multilayer charge trapping memory devices". Japanese Journal of Applied Physics 53, nr 8S3 (7.07.2014): 08NG02. http://dx.doi.org/10.7567/jjap.53.08ng02.
Pełny tekst źródłaTang, Zhen-Jie, Rong Li i Jiang Yin. "The charge storage characteristics of ZrO2nanocrystallite-based charge trap nonvolatile memory". Chinese Physics B 22, nr 6 (czerwiec 2013): 067702. http://dx.doi.org/10.1088/1674-1056/22/6/067702.
Pełny tekst źródłaTsoukalas, Dimitris, i Emanuele Verrelli. "Inorganic Nanoparticles for either Charge Storage or Memristance Modulation". Advances in Science and Technology 77 (wrzesień 2012): 196–204. http://dx.doi.org/10.4028/www.scientific.net/ast.77.196.
Pełny tekst źródłaBandić, Zvonimir Z., Dmitri Litvinov i M. Rooks. "Nanostructured Materials in Information Storage". MRS Bulletin 33, nr 9 (wrzesień 2008): 831–37. http://dx.doi.org/10.1557/mrs2008.178.
Pełny tekst źródłaLee, Meng Chuan, i Hin Yong Wong. "Technical Solutions to Mitigate Reliability Challenges due to Technology Scaling of Charge Storage NVM". Journal of Nanomaterials 2013 (2013): 1–17. http://dx.doi.org/10.1155/2013/195325.
Pełny tekst źródłaWang, Shuai, Jing Pu, Daniel S. H. Chan, Byung Jin Cho i Kian Ping Loh. "Wide memory window in graphene oxide charge storage nodes". Applied Physics Letters 96, nr 14 (5.04.2010): 143109. http://dx.doi.org/10.1063/1.3383234.
Pełny tekst źródłaLee, Gae-Hun, Jung-Min Lee, Yun Heub Song, Ji Chel Bea, Tetsu Tanaka i Mitsumasa Koyanagi. "Multilevel Charge Storage in a Multiple Alloy Nanodot Memory". Japanese Journal of Applied Physics 50, nr 9R (1.09.2011): 095001. http://dx.doi.org/10.7567/jjap.50.095001.
Pełny tekst źródłaRozprawy doktorskie na temat "Charge storage memory"
Lee, Yung-Huei. "Dual-carrier charge transport and damage formation of LPCVD nitride for nonvolatile memory devices /". The Ohio State University, 1986. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487322984316841.
Pełny tekst źródłaHetherington, Dale Laird. "III-V compound semiconductor integrated charge storage structures for dynamic and non-volatile memory elements". Diss., The University of Arizona, 1992. http://hdl.handle.net/10150/186112.
Pełny tekst źródłaMazoyer, Pascale. "Analyse et caractérisation des mécanismes de perte de charge relatifs aux diélectriques multicouches du point mémoire EPROM". Université Joseph Fourier (Grenoble), 1994. http://www.theses.fr/1994GRE10009.
Pełny tekst źródłaHabhab, Radouane. "Optimisation d'architectures mémoires non-volatiles à piégeage de charges pour les applications microcontrôleur et mémoire autonome". Electronic Thesis or Diss., Université Côte d'Azur, 2023. http://www.theses.fr/2023COAZ4102.
Pełny tekst źródłaThe aim of this thesis work is to evaluate the performance in programming/cycling/retention of a SONOS memory cell based on a highly innovative split-gate architecture developed by STMicroelectronics, the eSTM™ (embedded Select in Trench Memory). Firstly, we explain the realization of this SONOS memory, which is based on a process step modification of the floating gate eSTM™ memory, with this modification carried out without additional cost.Secondly, we investigate the most efficient program and erase mechanisms for this memory, which also leads us to propose a new SONOS memory architecture. Thirdly, we electrically characterize the P/E activations of the SONOS eSTM™ cell for the two available architectures: dual gate and overlap. For dual gate memory, both memory cells on either side of the selection transistor have their own "ONO/control gate" stack. For overlap memory, the ONO layer is common to both memory cells. Even though this layer is shared, the information storage in ONO is localized only under the relevant control gate due to the discrete nature of charge trapping. The mechanism implemented for write and erase operations is carrier hot injection, and we detail the optimization of biases (different for the two available architectures) of the drain and select gate, which define the written and erased threshold voltages. We then perform endurance tests up to one million cycles for both architectures. Finally, we conduct a study on retention and charge pumping to assess the oxide quality at the interface of our cells. In a fourth phase, we seek to better understand the operation of the memory transistor and the variability of eSTM™ using TCAD simulations and electrical measurements on structures with various geometries
Srowik, Rico. "Modellierung von Transistoren mit lokaler Ladungsspeicherung für den Entwurf von Flash-Speichern". Doctoral thesis, Technische Universität Dresden, 2007. https://tud.qucosa.de/id/qucosa%3A24067.
Pełny tekst źródłaIn this work, memory transistors with an oxide-nitride-oxide trapping-layer and local charge storage, which are used for non-volatile information storage, are examined. Characteristic for these transistors is an independent and separated storage of information by charge packages, located at both sides of the transistor channel, in the insulation layer. The physical backgrounds for reading, programming and erasing the memory transistors are discussed, and basic algorithms are shown for implementing these operations on a typical memory array architecture. For standard MOS-transistors a short channel threshold model is derived and solved analytically. By using these model equations, the known short channel effects are considered. Further, a model for calculating the drain current of short channel transistors in the subthreshold operation region is derived. This model is used to show the increase of drain-source leakage currents in short channel transistors. By extending the standard MOS-transistor threshold voltage model for local charge storage in the insulation layers, the derivation of a threshold voltage model for oxide-nitride-oxide transistors with local charge storage is enabled. This model permits the quantitative and qualitative discussion of the increase in threshold voltage caused by local injection of charges during programming. Furthermore, with this model, the separation of the information, which are stored at both sides of the transistor channel, in the read-out operation is explained qualitatively, and the bit separation is calculated dependent on the drain voltage. For long channel memory transistors an analytical approximation of the threshold voltage model is given, whereas the short channel behaviour can be determined by solving the model equation numerically. For long channel memory transistors, a subthreshold model for calculating the drain current is derived. This model shows the increase in leakage current of programmed memory transistors in comparision to standard MOS-transistors. The root cause of this effect, the reduced subthreshold swing of transistors in the programmed state, is analysed. The application of the derived model equations for the development of flash memories is demonstrated with some practical examples.
Srowik, Rico. "Modellierung von Transistoren mit lokaler Ladungsspeicherung für den Entwurf von Flash-Speichern". Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2008. http://nbn-resolving.de/urn:nbn:de:bsz:14-ds-1206006642261-96038.
Pełny tekst źródłaIn this work, memory transistors with an oxide-nitride-oxide trapping-layer and local charge storage, which are used for non-volatile information storage, are examined. Characteristic for these transistors is an independent and separated storage of information by charge packages, located at both sides of the transistor channel, in the insulation layer. The physical backgrounds for reading, programming and erasing the memory transistors are discussed, and basic algorithms are shown for implementing these operations on a typical memory array architecture. For standard MOS-transistors a short channel threshold model is derived and solved analytically. By using these model equations, the known short channel effects are considered. Further, a model for calculating the drain current of short channel transistors in the subthreshold operation region is derived. This model is used to show the increase of drain-source leakage currents in short channel transistors. By extending the standard MOS-transistor threshold voltage model for local charge storage in the insulation layers, the derivation of a threshold voltage model for oxide-nitride-oxide transistors with local charge storage is enabled. This model permits the quantitative and qualitative discussion of the increase in threshold voltage caused by local injection of charges during programming. Furthermore, with this model, the separation of the information, which are stored at both sides of the transistor channel, in the read-out operation is explained qualitatively, and the bit separation is calculated dependent on the drain voltage. For long channel memory transistors an analytical approximation of the threshold voltage model is given, whereas the short channel behaviour can be determined by solving the model equation numerically. For long channel memory transistors, a subthreshold model for calculating the drain current is derived. This model shows the increase in leakage current of programmed memory transistors in comparision to standard MOS-transistors. The root cause of this effect, the reduced subthreshold swing of transistors in the programmed state, is analysed. The application of the derived model equations for the development of flash memories is demonstrated with some practical examples
Seong, Nak Hee. "A reliable, secure phase-change memory as a main memory". Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/50123.
Pełny tekst źródłaBarclay, Martin Jared. "Electrical switching properties of ternary and layered chalcogenide phase-change memory devices". [Boise, Idaho] : Boise State University, 2009. http://scholarworks.boisestate.edu/td/67/.
Pełny tekst źródłaGao, Shen. "Transaction logging and recovery on phase-change memory". HKBU Institutional Repository, 2013. http://repository.hkbu.edu.hk/etd_ra/1549.
Pełny tekst źródłaBalasubramanian, Mahesh. "Phase change memory : array development and sensing circuits using delta-sigma modulation /". [Boise, Idaho] : Boise State University, 2009. http://scholarworks.boisestate.edu/td/44/.
Pełny tekst źródłaKsiążki na temat "Charge storage memory"
1976-, Chen Yiran, red. Nonvolatile memory design: Magnetic, resistive, and phase change. Boca Raton, FL: Taylor & Francis, 2012.
Znajdź pełny tekst źródła1969-, Luminet Olivier, i Curci Antonietta 1969-, red. Flashbulb memories: New issues and new perspectives. Hove (UK): Psychology Press, 2009.
Znajdź pełny tekst źródłaChen, Yiran, i Hai Li. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change. Taylor & Francis Group, 2017.
Znajdź pełny tekst źródłaLi, Hai. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change. Taylor & Francis Group, 2011.
Znajdź pełny tekst źródłaChen, Yiran, i Hai Li. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change. Taylor & Francis Group, 2017.
Znajdź pełny tekst źródłaChen, Yiran, i Hai Li. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change. Taylor & Francis Group, 2017.
Znajdź pełny tekst źródłaChen, Yiran, i Hai Li. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change. Taylor & Francis Group, 2017.
Znajdź pełny tekst źródłaChen, Yiran, i Hai Li. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change. Taylor & Francis Group, 2017.
Znajdź pełny tekst źródłaLuminet, Olivier, i Antonietta Curci. Flashbulb Memories: New Challenges and Future Perspectives. Taylor & Francis Group, 2017.
Znajdź pełny tekst źródłaLuminet, Olivier, i Antonietta Curci. Flashbulb Memories: New Challenges and Future Perspectives. Taylor & Francis Group, 2017.
Znajdź pełny tekst źródłaCzęści książek na temat "Charge storage memory"
Shi, Luping, Rong Zhao i Tow C. Chong. "Phase Change Random Access Memory". W Developments in Data Storage, 277–96. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2011. http://dx.doi.org/10.1002/9781118096833.ch13.
Pełny tekst źródłaShen, Xiang, Yimin Chen, Guoxiang Wang i Yegang Lv. "Phase-Change Memory and Optical Data Storage". W Springer Handbook of Glass, 1495–520. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-93728-1_44.
Pełny tekst źródłaRicci, Saverio, Piergiulio Mannocci, Matteo Farronato, Alessandro Milozzi i Daniele Ielmini. "Development of Crosspoint Memory Arrays for Neuromorphic Computing". W Special Topics in Information Technology, 65–74. Cham: Springer Nature Switzerland, 2024. http://dx.doi.org/10.1007/978-3-031-51500-2_6.
Pełny tekst źródłaPolzer, Miriam, i Sergey Goncharov. "Local Local Reasoning: A BI-Hyperdoctrine for Full Ground Store". W Lecture Notes in Computer Science, 542–61. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-45231-5_28.
Pełny tekst źródłaCappelletti, Paolo, i Jon Slaughter. "Embedded memory solutions: Charge storage based, resistive and magnetic". W Semiconductor Memories and Systems, 159–215. Elsevier, 2022. http://dx.doi.org/10.1016/b978-0-12-820758-1.00007-8.
Pełny tekst źródłaMolas, G., L. Masoero, V. Della Marca, G. Gay i B. De Salvo. "Improving embedded Flash memory technology: silicon and metal nanocrystals, engineered charge-trapping layers and split-gate memory architectures". W Advances in Non-volatile Memory and Storage Technology, 120–57. Elsevier, 2014. http://dx.doi.org/10.1533/9780857098092.1.120.
Pełny tekst źródłaRoy, Sourav. "Resistive Memory with Functional Duality-Non Volatile Emerging Memory & Nano Biosensors". W Memristors - the Fourth Fundamental Circuit Element - Theory, Device, and Applications [Working Title]. IntechOpen, 2023. http://dx.doi.org/10.5772/intechopen.1002783.
Pełny tekst źródłaChand Verma, Kuldeep. "Synthesis and Characterization of Multiferroic BiFeO3 for Data Storage". W Bismuth - Fundamentals and Optoelectronic Applications. IntechOpen, 2020. http://dx.doi.org/10.5772/intechopen.94049.
Pełny tekst źródłaWang, Dingchen, Shuhui Shi, Yi Zhang, Dashan Shang, Qing Wang, Hongyu Yu i Zhongrui Wang. "Stochastic Emerging Resistive Memories for Unconventional Computing". W Advanced Memory Technology, 240–69. Royal Society of Chemistry, 2023. http://dx.doi.org/10.1039/bk9781839169946-00240.
Pełny tekst źródła"Phase-Change Random Access Memory". W Data Storage at the Nanoscale, 485–612. Jenny Stanford Publishing, 2015. http://dx.doi.org/10.1201/b18094-13.
Pełny tekst źródłaStreszczenia konferencji na temat "Charge storage memory"
Shinn, Charles E. "Charge Constrained (1,7) Code For Magneto Optic Recording". W Optical Data Storage. Washington, D.C.: Optica Publishing Group, 1987. http://dx.doi.org/10.1364/ods.1987.thb4.
Pełny tekst źródłaLee, Sung-Tae, Suhwan Lim, Nagyong Choi, Jong-Ho Bae, Chul-Heung Kim, Soochang Lee, Dong Hwan Lee i in. "Neuromorphic Technology Based on Charge Storage Memory Devices". W 2018 IEEE Symposium on VLSI Technology. IEEE, 2018. http://dx.doi.org/10.1109/vlsit.2018.8510667.
Pełny tekst źródłaHussein Ali Alabdulqader i Samah Abdulkarim. "MIOS memory devices and their charge storage properties". W 2010 International Conference on Electronic Devices, Systems and Applications (ICEDSA). IEEE, 2010. http://dx.doi.org/10.1109/icedsa.2010.5503056.
Pełny tekst źródłaMolas, G., J. P. Colonna, R. Kies, D. Belhachemi, M. Bocquet, M. Gely, V. Vidal i in. "Investigation of charge-trap memories with AlN based band engineered storage layers". W 2010 IEEE International Memory Workshop. IEEE, 2010. http://dx.doi.org/10.1109/imw.2010.5488309.
Pełny tekst źródłaLee, C. H., C. W. Wu, S. W. Lin, T. H. Yeh, S. H. Gu, K. F. Chen, Y. J. Chen i in. "Numerical Simulation of Programming Transient Behavior in Charge Trapping Storage Memory". W 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design. IEEE, 2008. http://dx.doi.org/10.1109/nvsmw.2008.38.
Pełny tekst źródłaMisra, Abhishek, Hemen Kalita, Mayur Waikar, Amit Gour, Meenakshi Bhaisare, Manali Khare, Mohhamad Aslam i Anil Kottantharayil. "Multilayer Graphene as Charge Storage Layer in Floating Gate Flash Memory". W 2012 4th IEEE International Memory Workshop (IMW). IEEE, 2012. http://dx.doi.org/10.1109/imw.2012.6213626.
Pełny tekst źródłaXiaoxiao Zhu, Qiliang Li, Dimitris E. Ioannou, William A. Kimes, John S. Suehle, James E. Maslar, Hao D. Xiong, Shuo Yang i Curt A. Richter. "Silicon nanowire memory application using hafnium oxide charge storage layer". W 2007 International Semiconductor Device Research Symposium. IEEE, 2007. http://dx.doi.org/10.1109/isdrs.2007.4422492.
Pełny tekst źródłaKaur, Ramneek, i S. K. Tripathi. "Charge storage effects in doped polymer nanocomposite for memory device application". W ADVANCED MATERIALS AND RADIATION PHYSICS (AMRP-2015): 4th National Conference on Advanced Materials and Radiation Physics. AIP Publishing LLC, 2015. http://dx.doi.org/10.1063/1.4929191.
Pełny tekst źródłaYang, Shao-Ming, Jiun-Jia Huang, Chao-Hsin Chien, Pei-Jer Taeng, Lurng-Shehng Lee, Ming-Jinn Tsai i Tan-Fu Lei. "High Charge Storage Characteristics of CeO2 Nanocrystals for Novolatile Memory Applications". W 2008 International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA). IEEE, 2008. http://dx.doi.org/10.1109/vtsa.2008.4530792.
Pełny tekst źródłaLiu, S. H., W. L. Yang, C. W. Chiu i T. S. Chao. "High Efficiency Charge Storage Layer for MLC NAND Non-Volatile Memory". W 2010 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2010. http://dx.doi.org/10.7567/ssdm.2010.p-4-8.
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