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Kanoun, Mehdi. "Caractérisations électriques des structures MOS à nanocristaux de Ge pour des applications mémoires non volatiles". Lyon, INSA, 2004. http://theses.insa-lyon.fr/publication/2004ISAL0069/these.pdf.
Pełny tekst źródłaThe scaling down of the silicon devices predicted by the Moor’s law will cause physical and technological limitations. Indeed, the limit of the MOS transistor’s gate length is situated in the range of 8 nm (2010-2015). For the non volatile memories based on SiO2 insulator, the critical parameter is the tunnel oxide thickness which is situate around 7-8 nm (2008). For thinner oxides, the device loss its retention time characteristic (10 years). For these reasons, other ways must be envisaged. The few electron electronics seem to be a good candidate for this task, in particular for the memory applications. Indeed, Tiwari and collaborators had proposed in 1995, to replace poly-silicon floating gate by Si nanocrystals. The utilization of a granular based silicon nanocrystals floating gate allows the reduction of the tunnel oxide thickness. In order to ameliorate the retention time, it is more interesting to integrate Ge nanocrystals rather than the silicon ones thanks to their smaller band gap. In this context, this work proposes an electrical study of the electronic properties of Ge nanocrystals embedded in the SiO2 matrix for non volatile memory application. The first chapter is devoted to the description of the electronic properties change of the Ge nanocrystals due to the reduction of their size. In addition, the envisaged device is presented with its technological process. In the second chapter, different method analyses are reported for Ge isolation in a SiO2 matrix. The third chapter is dedicated to the transport mechanisms in Ge dots. Finally, in the forth chapter we will present the charge and discharge kinetic studies in Ge islands. These studies have permitted the optimization of the technologic parameters for the non volatile memory device realization as well as demonstrate the potential presented by the Ge dots for P type MOS memories
Lintanf, Amélie. "Dépôts par ESD et ALD et caractérisations physico-chimiques de couches d'oxydes à l'échelle nanométrique pour la microélectronique". Grenoble INPG, 2008. http://www.theses.fr/2008INPG0088.
Pełny tekst źródłaPerat, Olivier. "Méthodologie de caractérisation de paramètres thermomécaniques de matériaux pour la microélectronique". Toulouse, INSA, 2002. http://www.theses.fr/2002ISAT0009.
Pełny tekst źródłaOptimisation of electronic circuits is mandatory to meet performance, reliability and cost requirements. Our investigation, performed in a Motorola, LAAS/CNRS, Région Midi-Pyrénées common laboratory, concerns the thermal fatigue induced failures of components. Our work deals with the development of a characterisation method of two thermomechanical parameters: the Young's modulus and the coefficient of thermal expansion. Starting from an analytical modelling of thermomechanical stresses, the method is based on the thermal deflection of bilayer cantilevers. Using a single experimental set-up, this method allows the determination of the two parameters as a function of temperature, with a fairly good resolution. Bilayer cantilevers, processed in a clean room, have led to the validation of the method and have provided interesting results concerning study of the thermal fatigue behaviour of heterogeneous assemblies
Fossati, Caroline. "Optique pour la Microélectronique : du capteur au traitement de l'image". Habilitation à diriger des recherches, Université Paul Cézanne - Aix-Marseille III, 2008. http://tel.archives-ouvertes.fr/tel-00384815.
Pełny tekst źródłaDeux thématiques de recherche sont abordées :
- La caractérisation optique de défauts submicroniques dans les matériaux, qui a constitué, dans la continuité de ma thèse, la première partie de mes activités : caractérisation de précipités dans le Silicium par le développement d'un microscope infrarouge à balayage ; développement d'un microscope photo thermique pour la détection de nano défauts absorbants précurseurs d'endommagement dans les couches minces optique.
- L'optique pour la microélectronique, thématique initiée en 2000 au laboratoire, qui aborde la modélisation optique de capteurs d'images en technologie CMOS en vue d'adapter leur structure aux contraintes de réflexion et diffraction optique liées à la réduction de taille des pixels imposée par le marché.
Sont aussi concernés les masques avancés pour la photolithographie optique, et l'adaptation de techniques de traitement du signal et des images à la modélisation de corrections optiques de proximité (OPC) qu'il faut appliquer sur les masques pour corriger les effets de la diffraction dans le cadre de la diminution de taille des composants.
Des projets de recherche orientés sur l'application des capteurs et du traitement multidimensionnel du signal pour des applications médicales et de sécurité sont aussi présentés.
Thomas, Maryline. "Caractérisation et développement d'architectures 3 D pour capacités métal-isolant-métal intégrant des électrodes en cuivre et des diélectriques à permittivité élevée". Grenoble INPG, 2007. http://www.theses.fr/2007INPG0150.
Pełny tekst źródłaLaloum, David. "Tomographie par rayons X haute résolution : application à l'intégration 3D pour la microélectronique". Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAY067/document.
Pełny tekst źródłaIn this thesis, an original non-destructive 3D characterization technique has been developed : the X-ray tomography hosted in a scanning electron microscope. This instrument is not widely used in the microelectronics field. This computed tomography (CT) system has been used for the high resolution analysis of metallic interconnections such as copper pillars and through silicon vias (TSVs). These components are widely used in the field of 3D integration to make vertical stacks of interconnected chips.The most significant contributions of this thesis are : (1) the enhancement of the analytical capabilities of the instrument. Many studies – simulations and experiments – have been performed in order to determine and improve the 2D and 3D resolutions of this imaging system. It has been shown that the 2D resolution of this instrument can reach 60 nanometers. The quality of the projections and reconstruction has also been improved through the implementation of iterative reconstruction algorithms and various projections alignment methods. (2) The reduction of the scanning time by a factor 3 through the implementation of constrained reconstruction techniques such as the reconstruction method based on the total variation minimization. (3) The application of effective correction algorithms for removing reconstruction artefacts due to the polychromaticity of the X-ray beam. (4) The application of all these reconstruction methods and algorithms on real cases encountered by materials engineers
Cherkaoui, Karim. "Caractérisation de matériaux semi-isolants par spectroscopie de transitoire de courant photoinduit : matériaux InP dopés Fe pour la micro-optoélectronique et CdZnTe pour la détection nucléaire". Lyon, INSA, 1998. http://www.theses.fr/1998ISAL0104.
Pełny tekst źródłaSemi-insulating materials show an increasing interest in many application fields. For instance high resistivity InP and CdZnTe substrates are very promising for micro-optoelectronic circuits and nuclear detectors respectively. We have characterized both materials by means of Photo-Induced Current Transient Spectroscopy. The aim of the first part of this study is to analyze the defects in annealed InP substrates to understand the compensation phenomena in this material. We have detected two levels at 0. 2 eV and 0. 4 eV induced by the thermal treatment. We have noticed the presence of iron in all samples even in non intentionally doped ones. Therefore, one must take into account the Iron contribution to fully understand the compensation mechanism in the annealed InP substrates. In the second part, we have studied the CdZnTe material grown by the High Pressure Bridgman method to point out the defects which may affect the detector performance. Three levels detected near the midgap seem to affect the performance of the first studied detectors. We have characterized a series of detectors in which we have only detected one midgap level. We explain this by an improved material quality. This level is probably responsible of the semi-insulating character of this material. Finally, we correlate the detection performance of a series of samples with the presence of two electron traps at low temperature
Baudry, Ingwild. "Caractérisation des process de fabrication microélectroniques pour l'éco-conception des futures technologies". Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00957329.
Pełny tekst źródłaGonon, Nathalie. "Procédés thermiques rapides pour la réalisation de diélectriques ultra-minces sur silicium. Caractérisation par spectroellipsométrie". Lyon, INSA, 1993. http://www.theses.fr/1993ISAL0074.
Pełny tekst źródłaThermal oxidation of silicon is the more important process for integrated circuit fabrication. The trend towards even smaller and faster devices has resulted in a demand for gate oxides of thickness of less the 10 nm. More recently, a growth technique at very high temperatures for oxidation times of a few second has been developed with the advent of Rapid Thermal Processing. Very thin oxides films were achieved by rapid thermal oxidation in pure 02 or N2O stagnant atmosphere. RTO films thickness and refractive index were obtained by spectroscopic ellipsometry spectroellipsometiy investigation of RTO films revealed a growth rate enhancement at the initial stage of oxidation and an oxidation refractive index higher than chose of standard Si02. It can be noted that for N 0 kinetics, the growth rate was lower than for 02 kinetics. Complementary analysis (Auger spectroscopy, electrical properties. . . ) confirm the high value of the refractive index and reveal an interfacial problem. These analysis allow to express hypothesis to explain the high refractive index (densified SiO2 films, presence of an interfacial SiOx films, excess of silicon at the interface) and the growth of the RTO oxide (volumetric growth)
Chang, Youjean. "Etude de caractérisation de matériaux diélectriques de grille à forte permittivité pour les technologies CMOS ultimes". Lyon, INSA, 2003. http://theses.insa-lyon.fr/publication/2003ISAL0035/these.pdf.
Pełny tekst źródłaThis thesis presented the study of new gate dielectric materials with high permittivity ("high-k") for their integration into gate insulator of ultimate CMOS technology. Indeed, the aggressive miniaturization of the devices micro-electronics comes up today against the limits of SiO2 and will impose in the term of 2 or 3 years, its replacement by an insulator with higher permittivity, which constitutes a true technological rupture. Among the materials the most promising candidates, Al2O3 ("modeste–k"), HfO2 ("high-k") and SrTiO3 ("very high-k") represent potential solutions with respectively short, medium and long term. The principal problem of this integration is to reach equivalent oxide thickness (EOT) lower than 1 nm while maintaining leakage currents acceptable for the applications considered. The blocking points are in the technological compatibility of these materials, their thermodynamic stability, the control of the interfacial layer and its electrical properties. Thin dielectric films studied in this work has been deposited by two industrial techniques, atomic layer chemical vapour deposition (ALD) for Al2O3 and HfO2 or liquid injection metal organic chemical vapour deposition (MOCVD) for SrTiO3. We proved the very good thermal stability of Al2O3 which preserves an amorphous character up to annealing temperature higher to 800°C. A transition layer, mainly made up of SiO2 or (and) silicate, is observed at the interface between Al2O3 and Si. This layer is formed during the deposition and thermal treatments after deposition and it depends strongly on the preparation of the substrate before deposition. A similar behavior is observed for HfO2. We also show that the electrical properties of these materials (dielectric constant, EOT, flat band voltage, charges in oxide, interface density state) change in function of dielectric film thickness, surface preparation, or of annealing conditions. With comparable EOT, we obtain leakage currents lower than SiO2 for the three types of materials. The detailed analysis of the electrical parameters show that the principal challenges lie in the control of the interfacial layer and the reduction of the charges and interface state density which are proved to be currently one of the principal sources of mobility degradation
Doyen, Lise. "Caractérisation électrique de l'endommagement par électromigration des interconnexions en cuivre pour les technologies avancées de la microélectronique". Grenoble 1, 2009. http://www.theses.fr/2009GRE10036.
Pełny tekst źródłaCopper interconnect degradation due to electromigration is one of the major concern of integrated circuit reliability. New characterization techniques are needed in addition to the standard lifetime tests, in order to increase our knowledge on this degradation phenomenon. In this study, the growth of electromigration induced voids is followed by analyzing evolution of interconnect resistance with time. Effects of, first, the line cross-section and the temperature and, second, of the current density and the line length, have been investigated. It has thus been shown that resistance evolution analysis is a pertinent method to study degradation kinetics and extract characteristic parameters such as the activation energy of mechanism. Moreover, we have highlighted the influence of the void size and shape on the failure time, particularly important on short lines
Hourani, Wael. "Caractérisation des courants de fuite à l'échelle nanométrique dans les couches ultra-minces d'oxydes pour la microélectronique". Phd thesis, INSA de Lyon, 2011. http://tel.archives-ouvertes.fr/tel-00952841.
Pełny tekst źródłaNguyen, Théodore. "Caractérisation, modélisation et fiabilité des diélectriques de grille à base de HfO2 pour les futures technologies CMOS". Lyon, INSA, 2009. http://theses.insa-lyon.fr/publication/2009ISAL0067/these.pdf.
Pełny tekst źródłaThe downscaling of CMOS transistors has yielded better device performances, improved integration densities and driven down the average price of electronic devices. As of today, however, the enduring push toward miniaturization has hit a performance wall, where it becomes necessary to replace the traditional thermal gate oxide with a high-permittivity one. The semiconductor industry has chosen hafnium oxide as the best candidate to replace SiO2. Although hafnium oxide is effective at reducing gate leakage currents, its integration poses new challenges concerning device reliability, which is related to the oxide/channel interface and to the charge injected and trapped in the gate oxide. This work aims to investigate these points. In order to ensure that hafnium oxide-based devices are reliable, this work studies ways to characterize and modeling of defects within the gate stack, as well as the conduction mechanisms through the gate oxide. It also discusses the mechanisms of defects generation by PBTI. The understanding of the physical phenomena that affect device reliability is fundamental for high-k oxide integration
Yao, Wei-Zhen. "Analyses thermomécaniques multi-échelles expérimentale et numérique pour des empilements de couches minces en microélectronique". Thesis, Tours, 2018. http://www.theses.fr/2018TOUR4023.
Pełny tekst źródłaThe aim of this work is to understand and predict the warpage of silicon wafers during the fabrication process of PTIC microelectronic components. The warpages are partially responsible for several productivity problems. This study is done by coupling analytical calculation, finite element modeling and experimentation. The mechanical characterization of thin films constituting the multi-layered stack has been carried out by an experimental method nanoindentation with the help of a finite element model. The intrinsic stress in the thin films has been determined by coupling measurements of the wafer warpage and a finite element model. The obtained Young’s modulus and intrinsic stress are used to feed the database for calculating the wafer warpage by analytical and numerical approaches. The complexity of the structures (thousands of components in the wafer) required the use of homogenized models to calculate the wafer warpage. These results obtained allow the prediction of the wafer-level warpage in order to optimize the fabrication process flow and therefore reduce the risk of the mechanical problem
Soliman, Lélia. "Caractérisation de composants microélectroniques de test pour la technologie ULSI sur silicium". Rouen, 1999. http://www.theses.fr/1999ROUES048.
Pełny tekst źródłaHamioud, Karim. "Élaboration et caractérisation des interconnexions pour les nœuds technologiques CMOS 32 et 22 nm". Lyon, INSA, 2010. http://www.theses.fr/2010ISAL0011.
Pełny tekst źródła[The overall performance of integrated circuits should grow by about 20% at each new technology node. The interconnects have to be involved in increasing the performance and specially the reduction of signal propagation. The use of porous ultra low-k dielectric is necessary for the Sub-45 nm generation. In a first step, a roadmap for the 32 nm BEOL is proposed. The elementary processes developments have demonstrated the functionality of a multi-level demonstrator at minimum design rules of 32 nm technology node. In second step, a mature 45 nm technology has enabled the integration study of porous dielectric k = 2. 3 and k = 2. 2 which are potential candidates, respectively, for the 32 and 22 nm technology nodes. The introduction of these materials in the BEOL architecture scheme improves circuit performance but the dielectric reliability is found damaged from the reference k = 2. 5 material. Consequently, after to have identified the different sources of the dielectric reliability degradation, a response to the reliability standard has allowed the definition of reliable architecture. This reliable architecture used a robust metal barrier TaN/Ta robust and an additional layer in the dielectric stack technology. This reliable and efficient architecture represents a good beginning for the future 32 and 22 nm BEOL technology nodes. ]
Bakouboula, Aldrice Georra. "Conception et caractérisation de filtres optiques et de VCSELs accordables à base de micro système sur substrat InP pour les Réseaux optiques multiplexés en longueur d'onde". Lyon, INSA, 2004. http://theses.insa-lyon.fr/publication/2004ISAL0039/these.pdf.
Pełny tekst źródłaBackbone network bottleneck and the cost killing of future service deployments enforce the telecommunication market operators to envisage low cost high bit rate solutions providing both reconfigurable and scalable dynamic capability to the optical network architectures. This work propose to investigate the 100 GHz ITU grid channel spacing compatibility and microelectromechanical system implementation to the microelectronic batch process fabrication of WDM 1. 55 μm tunable optical devices. Filters and vertical cavity laser diodes based on high refractive index contrast InP/Air Bragg mirors are performed by surface micro machining. Experimental investigations which are carried out to overcome inherent technological breakthoughs of InP/Air tunable filters and electrically pumped MOEMS VCSEL fabrication are presented. In the first instance, we have studied the tunable filters and their modal properties. This studies have permitted to obtain an optimized filter structure which exhibit a 32. 5 GHz (0. 26 nm) selectivity and a WDM fitted side mode suppresion ratio. In the second instance, optically and electrically pumped VCSEL investigations have carried out our first room temperature electrical pumping lasing effect of an hybrid MOEMS VCSEL structure with a 2. 8 kA/cm2 current threshold
Kahn, Maurice. "Elaboration par PE-MOCVD à injection pulsée et caractérisation de matériaux à forte permittivité de type multicouches ou alliées pour des appliations capacités MIM". Grenoble 1, 2008. http://www.theses.fr/2008GRE10091.
Pełny tekst źródłaBecause of increasing number of embedded functions in silicon integrated circuits (ICs), Metal-Insulator-Metal (MIM) capacitors become more and more essential devices in microelectronics. To increasing the integration density of devices, high κ material must be used as dielectric. This insulator has to fulfill several requirements such as a high capacitance density, low leakage currents and minimum variation of capacitance values with the voltage bias (so-call the capacitance linearity). However, none can fulfill all the requirements. Therefore, others way shall be study such as oxides in nanolaminates or mixed structures. Moreover, the voltage linearity is badly controlled and its origin misunderstood. Thus, we studied the role of the electrode material (TiN, Pt, WSi2,3 et WSi2,7) and its interface with the yttrium oxide deposited by MOCVD with or without plasma enhanced on electric properties. We notice that the voltage linearity depends on the electrode material used. A double layer model was suggested to describe the MIM capacitance voltage linearity. Then, different bilayers, multilayers and mixed structures was studied (LaAlO3/Y2O3, structures base on HfO2 and Al2O3, SrTiO3/Y2O3). SrTiO3/Y2O3 bilayer structures allowed to obtain a capacitance density of 10 fF/µm² and to minimize the voltage linearity (a quadratic parameter α of -750 ppm/V²)
Tavernier, Aurélien. "Développement d'un procédé innovant pour le remplissage des tranchées d'isolation entre transistors des technologies CMOS avancées". Phd thesis, Université de Grenoble, 2014. http://tel.archives-ouvertes.fr/tel-00987019.
Pełny tekst źródłaVanypre, Thomas. "Etude et caractérisation du matériau CuAI1% utilisé en tant que couche de germination pour améliorer les performances de fiabilité des interconnexions des technologies 45 nm et ultérieures". Lyon, INSA, 2008. http://theses.insa-lyon.fr/publication/2008ISAL0033/these.pdf.
Pełny tekst źródłaAThe work presented is part of the development of the integration of electronic devices based silicon. Increasing the speed of switching leads to a reduction of the sizes of interconnections that connect these transistors and thus reduces the reliability of integrated circuits. The solutions studied to counteract this trend have the characteristic to reduce the electrical performance of the lines. Copper alloy to one percent of aluminum, as a layer of germination, an alloy is promising to find an optimum between improved reliability and limitation of movements of resistance in the interconnections. The inclusion of this material has served to validate its effect on reliability when electromigration tests. The physical analysis of CuAl1% we have identified several factors that explain these results such as: the best adhesion on materials CuAl barriers, the larger size of grains formed and significant reduction of the diffusion of impurities in interconnections. We also observed that the technological processes for the more advanced, the presence of aluminum slightly degrades the performance of electrical interconnections. CuAl allows the addition, thanks to its performance of adhesion, the use of a barrier ultra-fine and ultra compliant filed by the ALD process. This leads to a volume of copper higher in the lines and significantly reduced the strength of interconnections. Finally, this work has identified a property of the alloy CuAl which had not been assumed in the literature. CuAl shows the influence on the diffusion of copper by significantly reducing the defect and the density of "hillocks" (copper protrusions) observed during the manufacture of microchips. This property may allow a significant reduction of sequencing constraints in the production of integrated circuits
Gorbenko, Viktoriia. "Caractérisation par faisceaux d’ions d’hétérostructures III-V pour les applications micro et optoélectroniques". Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT140/document.
Pełny tekst źródłaThe integration of III-V semiconductor compounds on silicon should lead to the development of new highly efficient micro- and opto-electronic devices. High mobility InGaAs material is a promising candidate for n-channel metal-oxide semiconductor field-effect transistor beyond the 10 nm technology node. Moreover III-V semiconductors are also suitable materials for fabrication of optical (lasers, diodes) and ultra-high frequency analog devices and their integration on a Si platform will add new functionalities for optical network and communication. However the miniaturization of devices and their integration into 3D architectures require the development of advanced characterization methods to provide information on their physico-chemical composition with nanometer scale resolution.In this thesis, the physico-chemical studies of III-As heterostructures directly grown on 300 mm Si wafers by metalorganic vapor phase epitaxy are addressed. Secondary ion mass spectrometry techniques are used and developed in order to study interfaces abruptness, chemical composition and doping of III-V thin layers in 2D and 3D architectures with high depth resolution. The accurate quantitative analysis on InGaAs quantum wells (QWs) in 2D and 3D architectures was performed using magnetic SIMS and Auger techniques. To obtain the chemical profiling of narrow and repetitive III-V structures the averaging profiling method was developed for both techniques. Additionally, 3D reconstruction and depth profiling of individual trenches (less than hundred nanometer in width) containing thin InGaAs QWs selectively grown in silicon dioxide cavities using the aspect ratio trapping method were successfully obtained using Time-of-flight SIMS and atom probe tomography. Finally, the results were correlated with photoluminescence measurements
Bérubé, Benoit-Louis. "Développement d'une technologie NMOS pour la conception de fonctions électroniques avancées". Mémoire, Université de Sherbrooke, 2010. http://savoirs.usherbrooke.ca/handle/11143/1567.
Pełny tekst źródłaRaid, Idir. "Développement de méthodes numériques et de caractérisations expérimentales pour l’étude des contraintes mécaniques et défaillances induites dans les dispositifs microélectroniques avancés". Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALI084.
Pełny tekst źródłaThe trend in the microelectronics industry is towards miniaturisation, from transistors to the integrated circuit package. This constant desire of compactness is certainly motivated by economic reasons, but also by the perspectives to gain in performance, power and ergonomics. In early 90s, 0.8 µm was the transistors gate length at major semiconductor manufacturers. The length has been reduced to 6 nm with a density of integration of 125 million transistors per square millimetre. However, such a transition does not come without consequences, as far as it concerns fracture mechanisms, it is particularly true regarding the low-k dielectrics. This family of materials, although porous and fragile, is essential to ensure the insulation in the circuitry of an increasingly dense Back-End of Line (BEoL), with increasingly fine lithography. Besides, due to its porosity, it also has a hydrophilic behaviour which greatly reduces both its insulation quality and stress strength. For all these reasons, the seal ring, the copper interconnection structure that encircles the chip, was implemented to (i) ensure the mechanical integrity of its interior, containing the electrically active part of the die, and (ii) to protect it from moisture and other chemicals intrusions. Hence the interest of this work to address the thermomechanical stresses and cracking phenomena which are articulated around the BEoL. To do so, various paths revolving around the same line of research, mechanical integrity in microelectronics systems, are proposed. (i) Two ways of evaluating stress fields in active silicon and passive BEoL are investigated: by implementing sensor structures based on the principles of piezoresistance and extensometry respectively. (ii) The Four-Point Bending technique is benchmarked, and readapted to account for the crack length, for cracks advancing is homogeneous (decohesion) and heterogeneous (debonding) thin films structures. (iii) A Finite Elements approach, combined with Cohesive Zone Models under Small-Scale Yielding conditions, is proposed to analyse the influence of the arrangement and plasticity of copper in the interconnections in the resistance to crack advance
Le, Pennec Fabien. "Développement de microcapteurs pour la mesure de dioxyde de carbone (CO2) : application au suivi de la qualité de l’air". Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0148.
Pełny tekst źródłaUnlike outdoor air pollution, indoor air pollution remained relatively understudied until the early 2000s. However, we spend on average 85% of our time in closed environments (home, offices, transport, etc. in which we are exposed to many pollutants. Numerous studies have shown that measuring the concentration of carbon dioxide makes it possible to assess the confinement of indoor air. To measure pollutants, we can distinguish between analyzers and microsensors, each with its advantages and disadvantages. In the case of indoor air quality, resistive type microsensors appear to be the most appropriate solution, due to their low cost, high sensitivity, possible miniaturization and low power consumption. The detection phenomenon is based on the variation of the electrical resistance of the sensitive element in response to a gas adsorption rate. My research work has focused on the study of the sensitive layer. We used the screen-printing deposit method, a simple, fast and inexpensive technique. The crystalline structure and the morphology could be determined as well as the identification of the chemical substances present in our materials according to physico-chemical characterization techniques. Our results showed that the sensors made from La2O2CO3 and BaTiO3, respectively, present good performances, with a high sensitivity to CO2, and a good repeatability rate
Gamez-Cuatzin, Hugo. "Caractérisation électrique et optique d'hétérostructures Si/SiGe/Si pour applications aux transistors à effet de champ à canal p-SiGe à grille isolée ou non isolée". Lyon, INSA, 1998. http://www.theses.fr/1998ISAL0061.
Pełny tekst źródłaWe have studied the optical and electrical properties of Si/SiGe heterostructures for applications to silicon based microelectronics. The behavior of this ki nd of heterostructures as an active region of field effect transistors (FET's) was analyzed. Main characterization of heterostructures was done by photoluminescence and deep level transient spectroscopy (DLTS). The effects of the SiGe layer growth temperature were evidenced: layers deposed at grown temperatures TO close to 610 °c presented a high deep defect concentration. The layers quality is enhanced by the increase of growth temperature (Tc=700 °C). Valence band discontinuity ΔEv between Si and SiGe was deduced from the optical and electrical characterizations of Si/SiGe quantum-well metal-oxide-semiconductor (MOS) capacitors. We have implemented a technology process for elaboration of non insulated (Schottky) gate FET's on modulation doped Si/SiGe structures. The devices were studied by current-voltage measurements, current transient spectroscopy and drain conductance dispersion measurements. On this devices an important gate leakage current was observed. The gate isolation is an alternative to avoid this problem. Therefore, using isolated gate p-channel SiGe field effect transistors (MOSFET's) we successfully measured carrier emission from the Si/SiGe quantum-well. The set of results presented here contributes to the understanding of the physical phenomena involved in Si/SiGe heterostructure based devices
Tran, Dinh Phong. "Synthèse et caractérisation de précurseurs de cuivre, or et iridium et études des dépôts de films métalliques correspondants par CVD pour des applications en microélectronique". Paris 11, 2007. http://www.theses.fr/2007PA112248.
Pełny tekst źródłaA novel series of fluorine free copper (I) precursors, (b-diketonate)Cu(L) (L = BTMSA or TMSP), has been synthesized by acid-base reaction and characterized. Of these precursors, (5-methyl-2,4-hexanedionate)Cu(BTMSA) and (5,5-dimethyl-2,4-hexanedionate)Cu(BTMSA) are the most interested ones. Use of these precursors, the continuous, pure and electrically conducting copper thin films were grown on Ta/TaN from 170°C with high deposition rates (50 nm/min). AuCl(PF3) has been also evaluated for Au thermal CVD in this work. This inorganic precursor was used in solid form (with a conventional bubbler) as well as in a solution with toluene solvent (use of a liquid delivery system). Use of H2 as co-reactant gas, continuous and pure gold metallic thin films were deposited on Ta/TaN from 110°C. The impact of carrier gas nature (N2, H2) and deposition temperature on the precursor deposition reaction as well as on the properties of grown gold films has been investigated. [IrCl(PF3)2]2 has been used, for the first time in this work, as iridium source for Ir CVD. This inorganic precursor is very volatile but unstable. Hence, in this work, we have synthesized this precursor "in-situ" in the CVD reactor from IrCl(PF3) which is more stable and experimental. Under N2 carrier gas, compact, conformal and highly pure iridium thin films were grown on SiO2/Si from 240°C. We have also studied the influence of carrier gas nature (N2, H2, or O2) as well as the deposition temperature on the growth of iridium films
Almoric, Jean. "Développement d'un nouvel instrument couplant FIB/SEM UHV et OTOF-SIMS à haute résolution spatiale pour la microélectronique et ses applications". Electronic Thesis or Diss., Aix-Marseille, 2021. http://www.theses.fr/2021AIXM0368.
Pełny tekst źródłaSecondary Ion Mass Spectrometry (SIMS) is probably the most widely used chemical analysis technique in semiconductor science and metallurgy because of its ultimate sensitivity to all elements, especially the lighter ones. With systems downsizing, high-resolution 3D chemical imaging is becoming a prerequisite for the development of new materials. In this thesis, we report the development and optimization of an innovative SIMS implemented in a scanning electron microscope. The equipment makes it possible to obtain elementary chemical mapping at very high resolution (~25nm). The capacity of the technique is demonstrated with the characterization at the nanometric scale on the one hand of metallic superalloys necessary for the manufacture of aircraft engine parts and on the other hand of chalcogenide alloys used in the latest generation phase change memories developed in microelectronics
Brunet, Laurent. "Caractérisation électrique et fiabilité des transistors intégrant des diélectriques High-k et des grilles métalliques pour les technologies FDSOI sub-32nm". Phd thesis, Aix-Marseille Université, 2012. http://tel.archives-ouvertes.fr/tel-00847881.
Pełny tekst źródłaMbitsi, Hermane. "Synthèse de nanotubes de carbone pour l'obtention de vias d'interconnexions électriques et de drains thermiques". Phd thesis, Université d'Orléans, 2010. http://tel.archives-ouvertes.fr/tel-00637823.
Pełny tekst źródłaReche, Jérôme. "Nouvelle méthodologie hybride pour la mesure de rugosités sub-nanométriques". Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT050.
Pełny tekst źródłaRoughness at Sub-nanometric scale determination becomes a critical issue, especially for patterns with critical dimensions below 10nm. Currently, there is no metrology technique able to provide a result with high precision and accuracy. A way, based on hybrid metrology, is currently explored and dedicated to dimensional measurements. This hybrid metrology uses data fusion algorithms in order to address data coming from different tools. This thesis presents some improvements on line roughness analysis thanks to frequency decomposition and associated model. The current techniques used for roughness determination are explained and a new one SAXS (Small Angle X-rays Scattering) is used to push again limits of extraction of roughness. This technique has a high potential to determine sub nanometrics patterns. Moreover, the design and manufacturing of reference line roughness samples is made, following the state of art with periodic roughness, but also more complex roughness determined by a statistical model usually used for measurement. Finally, this work focus on hybridization methods and more especially on neural network utilization. Thus, the establishment of a neural network is detailed through the multitude of parameters which must be set. In addition, training of the neural network on simulation leads to the capability to generate different metrology
Brunet, Laurent. "Caractérisation électrique et fiabilité des transistors intégrant des dielectriques High-k et des grilles métalliques pour les technologies FDSOI sub-32nm". Thesis, Aix-Marseille, 2012. http://www.theses.fr/2012AIXM4728/document.
Pełny tekst źródłaThe integration of High-k dielectrics in recent CMOS technologies lead to new complex reliability issues. Furthermore new concerns appear with the use of fully depleted silicon on insulator (FDSOI) substrates for future sub-32nm planar technologies. Indeed, the integration of a buried oxide underneath the silicon film changes the electrostatic of the structure and create a new Si/SiO2 interface which may be degraded. This thesis presents different electrical characterization techniques and reliability studies on High-κ/metal gate FDSOI transistors. First, a complete electrostatic study of FDSOI structures is done allowing a better understanding of the effects of backgate biases. Different techniques to characterize interface traps are then presented and adapted to FDSOI devices, where traps at the silicon film/buried oxide interface must be considered. Finally, different reliability studies are presented; from NBTI and PBTI issues on long channel devices to specific concerns related to small gate length transistors such as hot carriers degradation on ultra-thin film FDSOI devices and threshold voltage increase with gate width scaling
Collin, Louis-Michel. "Intégration de microcanaux pour l'évacuation forcée de la chaleur au sein de puces 2D et 3D". Thesis, Lyon, 2016. http://www.theses.fr/2016LYSEI074/document.
Pełny tekst źródłaIn microelectronics, trends such as 3D stacking and die thinning bring major thermal challenges. Those challenges are exacerbated when applied to mobile devices where the available space and power for cooling are limited. This thesis aims at developing design tools and implementation techniques for microchannels cooling on 2D and 3D chips with hot spots for mobile devices. A design technique to optimize the microchannel configuration for chip cooling is developed using numerical experimentation plans. The optimized configuration suggests a cooling configuration reaching a maximum temperature of 89 °C on a 2 W hot spot, using a flow at a pressure drop plus petit que 1 kPa. Prototypes with different stacking and microchannel distributions are fabricated using deep reactive ion etching process and stacked using pick-and-place technique. A characterization bench and a thermal test chip are fabricated for experimental characterization of the cooling prototypes from various configurations. A prototype with microchannel zones limited to the hot spot vicinity and installed on the backside of the test chip reached a thermal resistance of 2.8 °C/W. This performance is achieved using a flow rate of 9.4 ml/min with a pressure drop of 19.2 kPa, representing a hydraulic power of 3 mW. Such cooling removes 7.3 W generated on a single heat source, representing a heat flux of 1 185 W/cm² for a coefficient of performance of 2 430. The optimization results suggest that the heat spreading is better exploited using parallel microchannels, rather than lengthen microchannels. It is both observed experimentally and numerically that the thermal resistance related to the fluid temperature rise is the major contribution to the total thermal resistance. Finally, it appears that the different stacking effects on thermal resistance are more important than the microchannels distributions in the observed ranges
Bernoux, Beatrice. "Caractérisation de MOSFETs de puissance cyclés en avalanche pour des applications automobiles micro-hybrides". Phd thesis, INSA de Toulouse, 2010. http://tel.archives-ouvertes.fr/tel-00509151.
Pełny tekst źródłaAvertin, Sebastien. "Développement et caractérisation de procédés de gravure plasma de T.S.V (Through Silicon Via) pour l'intégration tridimensionnelle de circuits intégrés". Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00771420.
Pełny tekst źródłaHernandez, Stephan. "Conception, réalisation et caractérisation de filtres optiques nanostructurés à bande étroite pour applications spatiales à 0.85 µm". Phd thesis, Université Paul Sabatier - Toulouse III, 2008. http://tel.archives-ouvertes.fr/tel-00339517.
Pełny tekst źródłaSauveplane, Jean-Baptiste. "Caractérisation thermomécanique de films métalliques déposés en couche mince pour la simulation de la fiabilité de composants microélectroniques de puissance". Phd thesis, INSA de Toulouse, 2007. http://tel.archives-ouvertes.fr/tel-00158019.
Pełny tekst źródłaAvertin, Sébastien. "Développement et caractérisation de procédés de gravure plasma de T.S.V (Through Silicon Via) pour l'intégration tridimensionnelle de circuits intégrés". Thesis, Grenoble, 2012. http://www.theses.fr/2012GRENT029/document.
Pełny tekst źródłaThe dictates of miniaturization and increased performance followed by microelectronics manufacturers faces currently physical, technological and economic limitations. An innovative alternative to these problems is the three-dimensional integration of integrated circuits. This technology involves the vertical stacking of different levels of functionality on the various circuits, and thus opens the way for multifunctional or heterogeneous systems, with electrical performance that are much better than those existing in the two-dimensional circuits. The stacking of these chips is achievable through crossing vias named TSV for "Through Silicon Via", which are obtained by the succession of different technological steps,. One of these steps is the realization by plasma etching of deep silicon microcavities. Currently two plasma etch processes are mainly used for the design of TSV or other silicon structures, the Bosch Process and the Cryogenic process, in both cases with different advantages and disadvantages. The purpose of this thesis is to develop an innovative and alternative plasma etching method comparing to those currently used, to minimize their disadvantages (sidewall roughness, lack of profiles control, low temperature ...). In this logic two deep etch processes have been considered, exploiting SF6/O2/HBr and SF6/O2/HBr/SiF4 etching chemistries. All the studies focuses at better understanding of the mechanisms of etching and passivation of high aspect ratio cavities, especially through exploitation of XPS surface analysis
Vavrille, Benjamin. "Développement d'une méthode innovante de mesures des propriétés thermomécaniques de films minces. Application à un dispositif imageur". Electronic Thesis or Diss., Université Grenoble Alpes, 2023. http://www.theses.fr/2023GRALI126.
Pełny tekst źródłaPolymers are very widespread in microelectronics. In addition to their relevant electrical and optical properties for integration, their thermomechanical properties generally exhibit a high contrast with semiconductor substrates, but also with other materials also integrated into microchips, like oxides or metals. This mismatch between materials generally leads to a sharp increase of stresses in the various layers under consideration, which in returns results of a sharp increase in the wafer curvature. Excessive stresses can lead to cracking or delamination, threatening the mechanical integrity of the structure. Knowing the properties of each layer, especially polymer films, enables designers to verify the compatibility of integrated materials and guarantee component reliability. However, to achieve this goal, it is mandatory to develop characterization techniques, especially for thin films deposited on substrates.Thus, the aim of this work is to develop an experimental method to determine the thermomechanical properties of integrated layers, and then to verify the mechanical integrity of microelectronic devices using analytical or numerical simulation tools. This method is based on measuring the variation of curvature during thermal cycles. Then the completion of the polymer cross-linking process can be checked and its temperature of glass transition can be determined. By measuring the thermally induced curvature of two distinct substrates with the same deposited polymer material, the biaxial modulus and the coefficient of thermal expansion of the film are determined. By characterizing a large number of polymers using this technique, we can build up a materials database that can be supplemented with other integrated materials. These data are used in modeling to predict the strain and stress levels of several devices used in microelectronics.In particular, we will study the case of image sensors by performing a predictive calculation of strain and stress distributions of stacks in order to examine the compatibility of different materials. We will also work on the mechanical integrity of these devices, to guarantee their manufacture and reliability over time. We will show that the material selection is eased by structural modeling and a method to study crack initiation and propagation using numerical models
Hernandez, Stephan. "Conception, réalisation et caractérisation de filtres optiques nanostructurés à bande étroite pour applications spatiales à 0. 85 µm". Toulouse 3, 2008. http://thesesups.ups-tlse.fr/368/.
Pełny tekst źródłaNew concepts in nanophonotonics and progress in microelectronic fabrication processes should lead to a new generation of optical components. The goal of this thesis is to propose such innovative optical filters for space application for 0. 85 µm wavelengths in order to overstep the usual filters limitations, particularly in term of bandwidth, polarization sensibility, oblique incidence and tunability. This PhD project is about conception, fabrication and characterization of resonant grating filters, composed by a dielectric multilayer and a bi-dimensional nanostructuration on the top. From the electromagnetic modeling of the devices, a conception methodology is developed leading to the parameters of the photonic lattice. A fabrication process including steps of thin film deposition, e-beam lithography and dry etching is developed. Thickness of the deposited layers and lattice parameters are controlled within nanometer precision. The optical characterization of the fabricated devices demonstrates state of art performances for normal incidence (bandwidth of 0. 4 nm, reflexion higher than 55%. . . ) and for oblique incidence at ~60° (bandwidth <0. 8 nm, polarization independence, tunability. . . ). These results fit well with the performances predicted by the theoretical studies. The generic aspect of the realization process and the achieved performances show that these components are good candidates to replace conventional multi-layer filters. Moreover, their fabrication processes compatibility with those from microelectronics opens the way to further integration of these filters on chips with other advanced functions, leading to new complex optical devices
Delcroix, Pierre. "Etude à l'échelle nanométrique par sonde locale de la fiabilité de diélectriques minces pour l'intégration dans les composants microélectroniques du futur". Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00822926.
Pełny tekst źródłaLafitte, Nicolas. "Caractérisation et commande de micropinces en silicium pour l'amélioration de la sensibilité paramétrique d'expériences biologiques sur des molécules d'ADN". Phd thesis, Université de Franche-Comté, 2012. http://tel.archives-ouvertes.fr/tel-00711961.
Pełny tekst źródłaShen, Zhengyan. "Elaboration, caractérisation et nouvelle architecture de matériaux composites Al/plaquettes de carbone pour des applications thermiques". Thesis, Bordeaux, 2020. http://www.theses.fr/2020BORD0268.
Pełny tekst źródłaIn the microelectronic industry, the ever increase in power density due to miniaturization of electronic components requires heat sink materials with a high thermal conductivity (TC), a low coefficient of thermal expansion (CTE), and specific mechanical properties (MP). Pure metals, such as Al and Cu, have been previously used. However, they have limited TCs (e.g. 240 W/m.K for Al) and their CTEs are too high (e.g. 23 × 10-6/K for Al), being incompatible with those of electronic components (e.g. 4 × 10-6/K for Si), leading to failures in service due to thermal fatigue. Regarding this, metal matrix composites have been proven to be promising material where carbon materials, such as graphite, diamond, and carbon fibres, have been introduced as reinforcements because of their excellent thermal properties (i.e. very high TC and low CTE). In this Ph.D. project, Al matrix composites reinforced with low-cost and easily machinable graphite flakes (hereafter called Al/Gf composite) were developed with the aim to maximize TCs, tailor CTEs close to 6×10-6/K, as well as improve MPs.The intrinsic TCs of Gf are highly anisotropic, i.e. in-plane TC of 1000 W/m.K and out-of-plane TC of 5-10 W/m.K, respectively. It is thus clear that the strong orientation of Gf in the Al matrix ensures the high TCs, along the direction of graphite plane, in the as-produced composite. In this study, a new approach to combining flake powder metallurgy with a step-by-step powder filling process was successfully applied to achieve this conventional 1D arrangement. As such, the highest TC values theoretically predicted can be achieved experimentally. Further, the 2D and 3D arrangements of Gf were made using specifically designed punches in order to tailor the anisotropic CTEs of Gf (i.e. in-plane CTE of -1 × 10−6/K and out-of-plane CTE of 28 × 10−6/K), being unavailable in the 1D arrangement. The 2D arrangement allows to achieve the reduced CTEs being compatible with those of the substrate materials while maintaining a high TCs, demonstrating the strong potential for applications. Finally, the efforts were devoted to strengthen the Al matrix by integrating dispersed (ex-situ) SiC and (in-situ) TiB2 nanoparticles to improve the overall MPs of the Al/Gf composites
Lorrière, Nominoë. "Cellules photovoltaïques pour la récupération d'énergie et la communication de données". Electronic Thesis or Diss., Aix-Marseille, 2019. http://www.theses.fr/2019AIXM0570.
Pełny tekst źródłaThe invention of high-intensity blue LED hit the market and the retail industry in 1993. It even brought a revolution in lighting history. These new devices significantly improved energy efficiency than ever before and led to their massive deployment since the end of the 2000s. Semiconductor materials for LED devices are used in the microelectronics domain to implement high-frequency logic functions.Light fidelity (LiFi) technologies combine illumination and communication capabilities by implanting information transmission function to existing lighting equipment. Information is transmitted by using intensity modulation of optical sources at high frequencies, far beyond the range of visual perception. LiFi is an enabling technology for the Internet of Things (IoT) systems. IoT requires a large number of wireless connections, so it is not compatible with existing radiofrequency networks.This work is based on the reception of light modulation. Photodiodes are the mostly used receivers, however their constraints on lighting and consumption make it difficult to meet the requirements of the IoT. On the ground of this, this research is aimed at studying the possibility of receiving LiFi modulation by photovoltaic cells and modules due to their two main qualities: passive detection and large dimensions (omnidirectional reception and shade resistance)
Mrazkova, Zuzana. "Modélisation et caractérisation de matériaux et nanostructures pour les applications photovoltaïques". Thesis, Université Paris-Saclay (ComUE), 2017. http://www.theses.fr/2017SACLX121/document.
Pełny tekst źródłaResearch in photovoltaics aims at lowering the price per watt of generated electrical power. Substantial efforts aim at searching for new materials and designs which can push the limits of existing solar cells. The recent development of complex materials and nanostructures for solar cells requires more effort to be put into their characterization and modeling. This thesis focuses on optical characterization, modeling, and design optimization of advanced solar cell architectures.Optical measurements are used for fast and non-destructive characterization of textured samples for photovoltaic applications. Surface textures enhance light-trapping and are thus desired to improve the solar cell performance. On the other hand, these textures make optical characterization more challenging and more effort is required for both, the optical measurement itself and subsequent modeling and interpretation of obtained data. In this work, we demonstrate that we are able to use optical methods to study the widely used pyramidal textures as well as very challenging randomly oriented silicon nanowire arrays.At first, we focused on the optical study of various pyramidal surfaces and their impact on the silicon heterojunction solar cell performance. We have found that vertex angles of pyramids prepared using various texturing conditions vary from the theoretical value of 70.52° expected from crystalline silicon. This change of the vertex angle is explained by regular monoatomic terraces, which are present on pyramid facets and are observed by atomic resolution transmission electron microscopy. The impact of a vertex angle variation on the thicknesses of deposited thin films is studied and the consequences for resulting solar cell efficiency are discussed. A developed optical model for calculation of the reflectance and absorptance of thin film multi-layers on pyramidal surfaces enabled a solar cell design optimization, with respect to a given pyramid vertex angle.In-situ Mueller matrix ellipsometry has been applied for monitoring the silicon nanowire growth process by plasma-enhanced vapor-liquid-solid method. We have developed an easy-to-use optical model, which is to our knowledge a first model fitting the experimental ellipsometric data for process control of plasma-assisted vapor-liquid-solid grown nanowires. The observed linear dependence of the silicon material deposition on the deposition time enables us to trace the fabrication process in-situ and to control material quality
Dilhaire, Stephan. "Développement d'un interféromètre laser très haute résolution pour la caractérisation de composants microélectroniques". Bordeaux 1, 1994. http://www.theses.fr/1994BOR10555.
Pełny tekst źródłaLocati, Jordan. "Etude par modélisation et caractérisation d'architectures innovantes de transistors pour les circuits logiques dans un environnement mémoires non volatiles embarquées". Electronic Thesis or Diss., Aix-Marseille, 2021. http://www.theses.fr/2021AIXM0399.
Pełny tekst źródłaThe study conducted in this thesis consists in developing new transistor architectures used in an embedded non-volatile memory environment (e-NVM). The objective was to improve the electricals parameters of a component such as the leakage current (IOFF) and the breakdown voltage (BV) without increasing the total area or adding new steps in the manufacturing process in which the component is made. As a first step, a work has been performed to highlight the weak areas of the device. Being in a dual gate memory environment, a work on the morphology of the gate of this component allowed to improve its electricals characteristics. The second step consists in working on a new type of architecture called non-planar, whose main interest leads in a considerable reduction of the surface up to 30%. This has been possible by the realization of a trench gate, whose etching step is already present in the manufacturing process. Different variants of these devices have been studied showing interesting results with respect to the difference in surface area with the planar device. The presence of parasitic transistors "hump" has been highlighted, assisted by 3D simulation. Finally, a reliability study has been conducted on these different components, the goal being to highlight the degradation mechanisms and thus allow to give improvement axes for the development of these future components
Ménéghin, Grégory. "Intégration en technologie BiCMOS et caractérisation d'un convertisseur de fréquence de réception pour un radar automobile en bande W assurant des communications inter-véhicules". Phd thesis, Université Paul Sabatier - Toulouse III, 2013. http://tel.archives-ouvertes.fr/tel-01067441.
Pełny tekst źródłaRanchon, Hubert. "Développement d'outils analytiques par et pour la microfluidique : caractérisation d'écoulements d'objets dissous et intégration d'un système de séparation sans matrice de biomolécules". Phd thesis, Toulouse 3, 2013. http://thesesups.ups-tlse.fr/2259/.
Pełny tekst źródłaTransport in solution at the nanoscale is of crucial interest for biology or energy conversion. The dynamics of single objects flowing in a liquid, and fluid transport properties are intimately related. Dynamics is mostly associated to the behavior of single object, whereas transport refers to the massive or global dynamics of a set of individuals. The gap in between these two views is very thin, as a global transport can be understood under a scale transformation of the behavior of one single component. This statement constitutes the basis of modern condensed matter physics. In this work we considered the behavior of individual diluted objects transported in solution from two vantages. First the dynamics of single "perfect" objects were investigated toward the characterization of micro-environments. Then, in a second time, we investigated the dynamics of single objects under-controlled environment aiming at elucidating the physical laws describing their behavior. We developed a new method for characterizing sub-micron confined flows. We derived a theoretical model based on nanospheres velocity probability density. This model was validated using in-house Brownian dynamics simulations of particles flowing in laminar Poiseuille flows. These numerical and analytical approaches were confronted to experiments of single nanospheres conveyed in pressure-driven flows in nanofluidic devices. We detected giant lift force, leading to cross-streamline migration away from the wall even at vanishing Reynolds number. These forces are not described in the literature, leading us to characterize their physical properties. We then switched to the study of dynamical properties of DNA molecules in solution in confined environment under an hybrid actuation involving hydrodynamics and electrokinetics. The use of a non-newtonian buffer solution led to observe a non-linear combination of the actuations. Experimental strategies were then developed to map the inhomogeneous transverse probability of density of molecules inside the channels. This specific phenomenon allowed for the design of a new way of resolving biomolecules by size in free solution. Overall, this experimental work at the nexus of fluid physics, micro-fabrication engineering and statistical physics, allowed us for the design of a new nano-velocimetry, and other experimental methods which help us decipher transverse migration of diluted solid and flexible objects in solution. Furthermore, hybrid mode actuation of DNA in non-Newtonian fluids led us to design of new way of separating biomolecules by size. We think that this work is a leap forward for an easy characterization of nanoflows and particle transports at the nanoscale
Abou, Hamad Valdemar. "Elaboration et caractérisation de contacts électriques à base de phases MAX sur SiC pour l'électronique haute température". Thesis, Lyon, 2020. http://www.theses.fr/2020LYSEI079.
Pełny tekst źródłaPower applications in which the ambient temperature is high, cause the increase of temperature in electronic components. Therefore, it is important to develop electronic devices that are able to withstand high current and high-power densities. In this thesis, our objective is to lay the foundations of a new technology for the manufacture of a new generation of Ti3SiC2 MAX phase-based electrical contacts, stable, reliable and reproducible on Silicon Carbide for very high temperature applications (300 - 600ºC). To synthesize Ti3SiC2 on SiC, two elaboration methods were studied in this thesis. The first approach is a reaction method, and the second approach consists on using a Ti3SiC2 target via the Pulsed Laser Deposition (PLD) technique. Our goal is to develop a good quality ohmic contacts. Physico-chemical, electrical (TLM) and mechanical (W-H and RSM) characterizations were performed on the Ti3SiC2 contacts. These samples underwent a thermal aging test at 600°C for 1500 hours under Argon, in order to study the stability and reliability of the electrical contacts at high temperatures. The obtained results showed that the reliability and the chemical stability between Ti3SiC2 and SiC allowed the contacts to keep an ohmic behavior with low electrical resistivity, in addition to a good mechanical behavior, even after 1500 hours of aging at 600ºC. Furthermore, the thermomechanical simulations performed were used to determine the effects of Interfacial Thermal Resistances on the heat dissipation and the mechanical stresses exerted on a high power PN diode. In this thesis, we have shown that an ohmic contact, based on Ti3SiC2, can remain stable and reliable on a 4H-SiC substrate, in temperatures up to 600ºC
Grandfond, Antonin. "Etude de la fiabilité des mesures électriques par la microscopie à force atomique sur couches diélectriques ultra-minces : Développement d'une technique de pompage de charge résolue spatialement pour la caractérisation des défauts d'interface". Thesis, Lyon, INSA, 2014. http://www.theses.fr/2014ISAL0133/document.
Pełny tekst źródłaThe rapid progress of the microelectronic is obtained by the strong reduction of the dimensions of the MOS transistor. In order to reduce the leakage currents SiO2 is nox replaced by HfO2, but new dielectrics with a high permittivity (high-k) will have to be integrated in the future so that the progession continues. The atomic force microscope (AFM) in Conductive-AFM (C-AFM) mode is an ideal tools for the electrical characterization of thin oxide films at the nanometric scale. In our work, we have tried to study the limits of the C-AFM. C-AFM consists in using an AFM tip as a top electrode in order to perform Intensity-Current (I-V) curves or mapping the current. We have tried and identify the phenomenon which lead to the degradation of the dielectric layer during the application of the positive voltage bias on the tip, which results in a deformation of the surface under study. We have shown that it is a thermal effect due to a large density of current, which is different from dielectric induced breakdown epitaxy (DBIE) observed on the devices, and which may even lead to the degradation of the susbstrate at the interface. This phenomon is favored by the presence of water on the surface although it is not its consequence. This confirms that such electrical measurements should be performed in ultra-high vacuum in spite of the consequences in terms of complexity of the measurement setup. As a consequence, the study of the dielectric material are questionned since the degradation process is partly due to the AFM technique itself and does not allow to extrapolate easily the behaviour of the integrated device. Moreover, the statistical study of the degradation of the layer (Weibull), commonly used, is affected by a bias (measurements are interdependent). In the same way, the modeling of the conduction through the layer must be questionned because the surface of the electrical contact between the tip and the dielectric layer remains a very variable parameter. The charge pumping technique, which consists in caracterizing the traps at the semiconductor / dielectric interface by filling/emptying them with the application of an alternating gate voltage. It allows to extract the states density (Dit(E) and the capture cross section (σ(E)) but does not provide any information about their repartition on the interface. So, we have adapted this technique to the scanning probe microscopy with the conducting AFM probe as a gate. Using gate-less transistors fabricated in the frame of this work, we have demonstrated the feasability of this technique with a satisfying agreement with macroscopic measurements. We are able to measure a signal that can be related to charge pumping. However, the signal is distorted compared to macroscopic measurements. Modeling is needed because in our case, minority carriers must travel from source to drain via a non polarised area. As a perspective, an energetically resolved method to map the interfacial defects might be developed