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Pashukov, Artem. "Application of Weight-Based Sum Codes at the Synthesis of Circuits for Built-in Control by Boolean Complement Method". Automation on transport 8, nr 1 (15.03.2022): 101–14. http://dx.doi.org/10.20295/2412-9186-2022-8-1-101-114.
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This work considers the application of Boolean complement method for the organization of self-checking circuits of built-in control for the devices synthesized on being Field-Programmable Gate Arrays. Review is given for the application of Boolean complement method while using various noise-resistant codes. The example is demonstrated for control circuit synthesis with Boolean complement method. Algorithm for control system synthesis by Boolean complement method with the use of weight-based sum codes by module M is formulated. As an example, weighted codes are considered with the summation of weight categories by module M = 3 and M = 4 for these purposes. The given codes have only two control categories that simplifies their application for task solution on the design of functional diagnostics system by Boolean complement method. The comparative analysis of both codes with their use in the systems with Boolean complement has been pursued. The application of Boolean complement method on the basis of weight-based sum codes for synthesis of discrete devices has been suggested.
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Efanov, Dmitriy, i Tat'yana Pogodina. "Self-Dual Functional Gates for the Synthesis of Controllable Digital Systems". Transport automation research 9, nr 2 (13.06.2023): 205–21. http://dx.doi.org/10.20295/2412-9186-2023-9-02-205-221.
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All self-dual analogs of elementary functional gates have been considered, the use of which allows for the synthesis of self-dual circuit implementations of arbitrary Boolean functions. In this case, two synthesis methods can be used, each one based on the property of any Boolean function to be transformed into a self-dual function using one additional variable. The first method involves replacing all non-self-dual functional gates in the device structure with self-dual analogs. The second one involves obtaining a self-dual function from the original formula. The study conducted modeling of self-dual functional gates in pulse mode of operation. It has been shown that all self-dual functional gates, except for those implementing equivalence and nonequivalence functions (modulo-2 addition), are fully self-checkable with respect to stuck-at faults when checking computations based on the belonging of the generated functions to the class of self-dual Boolean functions. However, the gates that implement the mentioned functions require additional monitoring. For them, error masking occurs due to the simultaneous distortion of signals on both combinations in a pair. This feature of these self-dual functional gates should be taken into account when developing controllable self-checking digital computing devices and systems. The article provides an example of using methods for constructing self-dual circuit implementations. The obtained results can be used in the synthesis of controllable self-dual computing devices and systems.
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Rawski, Mariusz. "Application of Indexed Partition Calculus in Logic Synthesis of Boolean Functions for FPGAs". International Journal of Electronics and Telecommunications 57, nr 2 (1.06.2011): 209–16. http://dx.doi.org/10.2478/v10177-011-0029-4.
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Application of Indexed Partition Calculus in Logic Synthesis of Boolean Functions for FPGAsFunctional decomposition of Boolean functions specified by cubes proved to be very efficient. Most popular decom-position methods are based on blanket calculus. However computation complexity of blanket manipulations strongly depends on number of function's variables, which prevents them from being used for large functions of many input and output variables. In this paper a new concept of indexed partition is proposed and basic operations on indexed partitions are defined. Application of this concept to logic synthesis based on functional decomposition is also discussed. The experimental results show that algorithms based on new concept are able to deliver good quality solutions even for large functions and does it many times faster than the algorithms based on blanket calculus.
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Abdollahi, Afshin, Mehdi Saeedi i Massoud Pedram. "Reversible logic synthesis by quantum rotation gates". Quantum Information and Computation 13, nr 9&10 (wrzesień 2013): 771–92. http://dx.doi.org/10.26421/qic13.9-10-3.
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A rotation-based synthesis framework for reversible logic is proposed. We develop a canonical representation based on binary decision diagrams and introduce operators to manipulate the developed representation model. Furthermore, a recursive functional bi-decomposition approach is proposed to automatically synthesize a given function. While Boolean reversible logic is particularly addressed, our framework constructs intermediate quantum states that may be in superposition, hence we combine techniques from reversible Boolean logic and quantum computation. {The proposed approach results in quadratic gate count for multiple-control Toffoli gates without ancillae, linear depth for quantum carry-ripple adder, and $O(n\log^2 n)$ size for quantum multiplexer.
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BRAHA, DAN. "Design-as-satisfiability: A new approach to automated synthesis". Artificial Intelligence for Engineering Design, Analysis and Manufacturing 15, nr 5 (listopad 2001): 385–99. http://dx.doi.org/10.1017/s0890060401155022.
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This article addresses computational synthesis systems that attempt to find a structural description that matches a set of initial functional requirements and design constraints with a finite sequence of production rules. It has been previously shown by the author that it is computationally difficult to identify a sequence of production rules that can lead to a satisficing design solution. As a result, computational synthesis, particularly with large volumes of selection information, requires effective design search procedures. Many computational synthesis systems utilize transformational search strategies. However, such search strategies are inefficient due to the combinatorial nature of the problem. In this article, the problem is approached using a completely different paradigm. The new approach encodes a design search problem as a Boolean (propositional) satisfiability problem, such that from every satisfying Boolean-valued truth assignment to the corresponding Boolean expression we efficiently can derive a solution to the original synthesis problem (along with its finite sequence of production rules). A major advantage of the proposed approach is the possibility of utilizing recently developed powerful randomized search algorithms for solving Boolean satisfiability problems, which considerably outperform the most widely used satisfiability algorithms. The new design-as-satisfiability technique provides a flexible framework for stating a variety of design constraints, and also represents properly the theory behind modern constraint-based design systems.
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Prihozhy, Anatoly A. "Synthesis of quantum circuits based on incompletely specified functions and if-decision diagrams". Journal of the Belarusian State University. Mathematics and Informatics, nr 3 (14.12.2021): 84–97. http://dx.doi.org/10.33581/2520-6508-2021-3-84-97.
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The problem of synthesis and optimisation of logical reversible and quantum circuits from functional descriptions represented as decision diagrams is considered. It is one of the key problems being solved with the aim of creating quantum computing technology and quantum computers. A new method of stepwise transformation of the initial functional specification to a quantum circuit is proposed, which provides for the following project states: reduced ordered binary decision diagram, if-decision diagram, functional if-decision diagram, reversible circuit and quantum circuit. The novelty of the method consists in extending the Shannon and Davio expansions of a Boolean function on a single variable to the expansions of the same Boolean function on another function with obtaining decomposition products that are represented by incompletely defined Boolean functions. Uncertainty in the decomposition products gives remarkable opportunities for minimising the graph representation of the specified function. Instead of two outgoing branches of the binary diagram vertex, three outgoing branches of the if-diagram vertex are generated, which increase the level of parallelism in reversible and quantum circuits. For each transformation step, appropriate mapping rules are proposed that reduce the number of lines, gates and the depth of the reversible and quantum circuit. The comparison of new results with the results given by the known method of mapping the vertices of binary decision diagram into cascades of reversible and quantum gates shows a significant improvement in the quality of quantum circuits that are synthesised by the proposed method.
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Perkowski, Marek A., Malgorzata Chrzanowska-Jeske, Andisheh Sarabi i Ingo Schäfer. "Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions". VLSI Design 3, nr 3-4 (1.01.1995): 301–13. http://dx.doi.org/10.1155/1995/24594.
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This paper introduces several new families of decision diagrams for multi-output Boolean functions. The introduced families include several diagrams known from literature (BDDs, FDDs) as subsets. Due to this property, these diagrams can provide a more compact representation of functions than either of the two decision diagrams. Kronecker Decision Diagrams (KDDs) with negated edges are based on three orthogonal expansions (Shannon, Positive Davio, Negative Davio) and are created here for incompletely specified Boolean functions as well. An improved efficient algorithm for the construction of KDD is presented and applied in a mapping program to ATMEL 6000 fine-grain FPGAs. Four other new families of functional decision diagrams are also presented: Pseudo KDDs, Free KDDs, Boolean Ternary DDs, and Boolean Kronecker Ternary DDs. The last two families introduce nodes with three edges and require AND, OR and EXOR gates for circuit realization. There are two variants of each of the last two families: canonical and non-canonical. While the canonical diagrams can be used as efficient general-purpose Boolean function representations, the non-canonical variants are also applicable to incompletely specified functions and create don't cares in the process of the creation of the diagram.. They lead to even more compact circuits in logic synthesis and technology mapping.
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Stojkovic, Suzana, Milena Stankovic i Claudio Moraga. "Complexity reduction of Toffoli networks based on FDD". Facta universitatis - series: Electronics and Energetics 28, nr 2 (2015): 251–62. http://dx.doi.org/10.2298/fuee1502251s.
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Synthesis of switching functions by Toffoli gates has become a very important research topic in the last years, since Toffoli gates are used in the synthesis of reversible circuits. Early methods based on the truth-table representation of Boolean functions are applicable to functions with a relatively small number of variables. Later on, methods for synthesis by Toffoli gates based on decision diagrams (BDDs, FDDs or OKFDDs) were introduced and applied to the synthesis of both reversible and irreversible functions. This paper presents a method for the reduction of the number of lines and gates in the Toffoli gate realization of Boolean functions based on their Functional Decision Diagram (FDD) representation. Experiments show that, when the proposed reduction is used, the realization of the given function based on FDD will, on the average, be smaller in terms of the number of lines and the number of gates than the realizations based on an OKFDD, an optimal BDD or based on a FDD by using previously defined algorithms.
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Efanov, D. V., i D. V. Pivovarov. "FUNCTIONAL APPROACH TO THE SYNTHESIS OF CONCURRENT ERROR-DETECTION CIRCUIT BASED ON BOOLEAN COMPLEMENT AND USE OF "2-OUT-OF-5" CONSTANT-WEIGHT CODE". Informatika i sistemy upravleniya, nr 4 (2021): 81–94. http://dx.doi.org/10.22250/isu.2021.70.81-94.
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A method for self-checking concurrent error-detection circuit synthesis based on Boolean com-plement and "2-out-of-5" constant-weight code is described. The method is notable for using functional relationship between the signals from the working and control outputs instead of ana-lyzing the unit performance on each input. The functional dependence is established with due account to the requirements for the formation of codewords of the "2-out-of-5" code and a com-plete tester check. In addition, it considers the formation of a complete set of test combinations for transformation elements in the concurrent error-detection circuit. A method for obtaining a functional relationship between the control outputs and the operating outputs of the diagnostic object is presented. One of the options for extending the definition of the control function values is presented, as well as the functional dependence. It is noted that the number of options for ex-tending the definition of the control function values is large, which allows numerous options for synthesizing a concurrent error-detection circuit for any diagnostic object based on the described method. The use of the "2-out-of-5" code for the synthesis of concurrent error-detection circuits applying the Boolean complement method proved its effectiveness for organizing self-checking digital devices in automatics and computer technology.
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SELVARAJ, HENRY, PIOTR SAPIECHA, MARIUSZ RAWSKI i TADEUSZ ŁUBA. "FUNCTIONAL DECOMPOSITION — THE VALUE AND IMPLICATION FOR BOTH NEURAL NETWORKS AND DIGITAL DESIGNING". International Journal of Computational Intelligence and Applications 06, nr 01 (marzec 2006): 123–38. http://dx.doi.org/10.1142/s1469026806001782.
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General functional decomposition is mainly perceived as a logic synthesis method for implementing Boolean functions into FPGA-based architectures. However it also has important applications in many other fields of modern engineering and science. In this paper, advantages of functional decomposition are demonstrated on "real life" examples. Application of decomposition-based methods in other fields of modern engineering is presented. In the case of decision tables, application of decomposition methods leads to significant benefits in the analysis process of data dependencies, especially in cases when the input decision tables are unmanageably large. Experimental results demonstrate that it can help implementing sequential machines using flip-flops or ROM memory. It also can be efficiently used as multilevel logic synthesis method for VLSI technology.
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Cheburakhin, I. F., i O. N. Gavrish. "About One Efficient Method of Synthesis of Boolean Formulas and Circuits of Functional Elements". MEHATRONIKA, AVTOMATIZACIA, UPRAVLENIE 18, nr 6 (15.06.2017): 407–14. http://dx.doi.org/10.17587/mau.18.407-414.
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Bibilo, P. N. "Hardware Implementation of Code Converters Designed to Reduce the Length of Binary Encoded Words". Programmnaya Ingeneria 13, nr 8 (8.09.2022): 363–82. http://dx.doi.org/10.17587/prin.13.363-382.
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The problem of synthesis of combinational circuits of code converters designed to reduce the length of words from a given set of encoded binary words is considered. The encoding assumes that different binary words will be encoded by different binary codes of shorter length. Code converters of this type are designed to reduce the length of binary words transmitted in digital systems over data buses when the bit depth of the transmitted words exceeds the bit depth of the data bus. For example, 18-bit or 17-bit words need to be transmitted over a 16-bit data bus. Each such word can be transmitted in two cycles of operation of a digital system, however, this approach reduces the overall performance of the system. One of the approaches to solve such problems is the development of combinational circuits that convert long binary encoded words into shorter ones. The proposed methods for solving the problem of synthesizing circuits of code converters are based on the compilation and logical minimization of such forms of systems of incompletely specified Boolean functions as disjunctive normal forms (DNF) and binary decision diagrams (BDD). Using BDD to minimize representations of k-valued functions that depend on Boolean variables is also proposed. Technologically independent logical minimization of functional descriptions of the designed code converters is proposed to be performed by programs for minimizing systems of Boolean functions in the DNF class and programs for joint minimization of BDD representations of systems of completely specified Boolean functions. Minimization of functional descriptions is aimed at reducing the hardware complexity of combinational circuits in the basis of library elements or programmable FPGA elements implementing code converters of the class in question.
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CHIANG, TSUNG-HSI, i LAN-RONG DUNG. "VERIFICATION OF DATAFLOW SCHEDULING". International Journal of Software Engineering and Knowledge Engineering 18, nr 06 (wrzesień 2008): 737–58. http://dx.doi.org/10.1142/s0218194008003891.
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This paper presents the formal verification method for high-level synthesis (HLS) to detect design errors of dataflow algorithms by using Petri Net (PN) and symbolic-model-verifier (SMV) techniques. Formal verification in high-level design means architecture verification, which is different from functional verification in register transfer level (RTL). Generally, dataflow algorithms need algorithmic transformations to achieve optimal goals and also need design scheduling to allocate processor resources before mapping on a silicon. However, algorithmic transformations and design scheduling are error-prone. In order to detect high-level faults, high-level verification is applied to verify the synthesis results in HLS. Instead of applying Boolean algebra in traditional verification, this paper adopts both Petri Net theory and SMV model checker to verify the correctness of the synthesis results of the high-level dataflow designs. In the proposed hybrid verification method, a high-level design or DUV (design-under-verification) is first transformed into a Petri Net model. Then, Petri Net theory is applied to check the correctness of its algorithmic transformations of HLS, and the SMV model checker is used to verify the correctness of the design scheduling. We presented two approaches to realize the proposed verification method and concluded the best one who outperforms the other in terms of processing speed and resource usage.
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PEDRYCZ, WITOLD, i ADAM GACEK. "LEARNING OF FUZZY AUTOMATA". International Journal of Computational Intelligence and Applications 01, nr 01 (marzec 2001): 19–33. http://dx.doi.org/10.1142/s1469026801000068.
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In this study, we revisit the well-known notion of fuzzy state machines and discuss their development through learning. The systematic development of fuzzy state machines has not been pursued as intensively as it could have been expected from the breadth of the possible usage of them as various modelling platforms. We concentrate on the generalization of the well known architectures exploited in Boolean system synthesis, namely Moore and Mealy machines and show how these can be implemented in terms of generic functional modules such as fuzzy JK flip-flops and fuzzy logic neurons (AND and OR neurons) organized in the form of logic processors. It is shown that the design of the fuzzy state machines can be accomplished through their learning. The detailed learning algorithm is presented and illustrated with a series of numeric examples. The study reveals an interesting option of constructing digital systems through learning: the original problem is solved in the setting of fuzzy state machines and afterwards "binarised" into the two-valued format realized via the standard digital hardware.
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Das, Apangshu, i Sambhu Nath Pradhan. "Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits". VLSI Design 2016 (27.04.2016): 1–14. http://dx.doi.org/10.1155/2016/3191286.
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The increased number of complex functional units exerts high power-density within a very-large-scale integration (VLSI) chip which results in overheating. Power-densities directly converge into temperature which reduces the yield of the circuit. An adverse effect of power-density reduction is the increase in area. So, there is a trade-off between area and power-density. In this paper, we introduce a Shared Reed-Muller Decision Diagram (SRMDD) based on fixed polarity AND-XOR decomposition to represent multioutput Boolean functions. By recursively applying transformations and reductions, we obtained a compact SRMDD. A heuristic based on Genetic Algorithm (GA) increases the sharing of product terms by judicious choice of polarity of input variables in SRMDD expansion and a suitable area and power-density trade-off has been enumerated. This is the first effort ever to incorporate the power-density as a measure of temperature estimation in AND-XOR expansion process. The results of logic synthesis are incorporated with physical design in CADENCE digital synthesis tool to obtain the floor-plan silicon area and power profile. The proposed thermal-aware synthesis has been validated by obtaining absolute temperature of the synthesized circuits using HotSpot tool. We have experimented with 29 benchmark circuits. The minimized AND-XOR circuit realization shows average savings up to 15.23% improvement in silicon area and up to 17.02% improvement in temperature over the sum-of-product (SOP) based logic minimization.
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Akshay, S., Supratik Chakraborty, Shubham Goel, Sumith Kulal i Shetal Shah. "Boolean functional synthesis: hardness and practical algorithms". Formal Methods in System Design, 21.10.2020. http://dx.doi.org/10.1007/s10703-020-00352-2.
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Tupkalo, Viltalii, i Serhii Cherepkov. "Systems engineering of cybersecured digital and information measuring systems based on the signature Boolean-polynomial algebra synthesis apparatus". Measurements infrastructure 5 (5.05.2023). http://dx.doi.org/10.33955/v5(2023)-024.
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Development of DIMSCC models with cyber-controllability of their apparatus and software for computing function (operations) in real time becomes the primary task since the problem relevance of the cyber security of digital information and measuring systems of control complexes (DIMSCC) for critical infrastructure objects is increasing. Based on an analysis of known digital systems functional control methods new term «functional cyber-controllability of the digital informational and measuring system» was defined in the article. New approach to operational functional control of hardware redundancy is proposed. This is the synthesis of DIMSCC computing operations. Hardware redundancy is a synthesized control node chosen for functional control of various DIMSCC basic arithmetic and logical functions (operations) which should be reduced to simple procedure of corresponding switching functionally complete combinational structures from a finite set (standard set). Concerning this, the synthesis task is as follows. Only inputs and outputs of specified object are available for functional control of arithmetic and logical operations on binary operands under external hacker influence. Combination type functional control node structure (operational compositional adaptation) should be developed depending on the type of controlled computing operation being performed. The result of the synthesis task solving is a system of formulae determination (signature control equations) of the signature functional control of all DIMSCC basic arithmetic and logical functions (operations) on a single basis of a single equivalent representation of their known formulaic expression by corresponding (adequate) descriptions in infix notation (infix models). Apparatus of Boolean-polynomial algebra is used aiming to realize infix notation. The practical advantage of the proposed approach to the synthesis of hardware redundancy of operational functional signature control of computing operations is the transition possibility from signature control equations formulae to their realization implementation in the form of a signature control node directly without additional interpreting and minimizing procedures use by simple logical composition (switching) functionally complete combinational structures from a finite set (standard set).
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Bhunia, Kousik, Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh i Rolf Drechsler. "ReSG: A Data Structure for Verification of Majority based In-Memory Computing on ReRAM Crossbars". ACM Transactions on Embedded Computing Systems, 9.08.2023. http://dx.doi.org/10.1145/3615358.
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Recent advancements in the fabrication of Resistive Random Access Memory (ReRAM) devices have led to the development of large scale crossbar structures. In-memory computing architectures relying on ReRAM crossbars aim to mitigate the processor-memory bottleneck that exists with current CMOS technology. With this motivation, several synthesis and mapping approaches focusing on the realizations of Boolean functions in the ReRAM crossbars have been proposed earlier. Thus far, the verification of the designs realized on ReRAM crossbars is done either through manual inspection or using simulation based approaches. Since manual inspections and simulation based approaches are limited to smaller designs, they cannot be applied to the verification of complex designs on large-scale ReRAM crossbars. Motivated by this, we propose, for the first time, an automatic equivalence checking flow that determines the equivalence between the original function specification (e.g., Majority Inverter Graph (MIG) ) and the crossbar micro-operations file formats. We consider two crossbar structures, zero-transistor, one-memristor (0T1R) and one-transistor, one-memristor (1T1R) to implement the micro-operations. While the micro-operations file format exists for 0T1R crossbar structures, no representations for micro-operations to be executed in 1T1R crossbars exist till date. In this work, we introduce the micro-operation file format for 1T1R crossbar structures to efficiently represent the micro-operations as ReRAM crossbar netlists. Afterwards, we introduce two intermediate data structures, ReRAM Sequence Graph for 0T1R crossbars (ReSG-0T1R) and for 1T1R crossbars (ReSG-1T1R) , that are derived from the 0T1R and 1T1R crossbar micro-operations file formats, respectively. These ReSGs are then translated into Boolean Satisfiability (SAT) formula, and then the verification is done by checking the generated SAT formulae against the golden functional specification (represented in Verilog) using Z3 Satisfiability solver. Experimental evaluations confirm the effectiveness of the proposed verification methodology on MCNC and ISCAS benchmarks.
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Benyo, Sarah, Robert A. Saadi, Scott Walen i Jessyka G. Lighthall. "A Systematic Review of Surgical Techniques for Management of Severe Rhinophyma". Craniomaxillofacial Trauma & Reconstruction, 6.01.2021, 194338752098311. http://dx.doi.org/10.1177/1943387520983117.
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Study Design: Systematic review of the literature. Objective: The goal of this study is to review the current literature on severe rhinophyma requiring operative management for significant cosmetic deformity or nasal obstruction. We aim to provide a treatment algorithm for the various surgical techniques employed in the treatment of severe rhinophyma. Methods: Independent searches of the PubMed and MEDLINE databases were performed. Articles from the period of 2010 to 2020 were collected. All studies which described surgical treatment of severe rhinophyma using the Boolean method and relevant search term combinations, including “rhinophyma,” “severe,” “operative” and “surgery” were collected. Results: A total of 111 relevant unique articles met criteria for eligibility analysis. Of these, 85 articles were deemed inappropriate for the literature review due to exclusion criteria. The remaining 26 articles were included in the literature review. Due to variability in study design and outcome measures, formal synthesis of data in the form of a meta-analysis was not possible. Conclusions: Severe rhinophyma may present a reconstructive challenge to reestablish normal contour and patent nasal airway. Significant deformity necessitates surgical correction. The present article reviews the current literature and provides a summary and stepwise explanation of established surgical techniques for addressing the cosmetic and functional deficits these patients encounter.
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Ramsay, Jennifer, Christopher Sandom, Thomas Ings i Helen C. Wheeler. "What evidence exists on the impacts of large herbivores on climate change? A systematic map protocol". Environmental Evidence 11, nr 1 (19.04.2022). http://dx.doi.org/10.1186/s13750-022-00270-2.
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Abstract Background In recent years there has been an increased focus on the role of large herbivores in ecosystem restoration and climate change mitigation. There are multiple processes by which large herbivores could potentially influence climate feedback and forcing effects, but the evidence has not yet been synthesised in a systematic and accessible format. Grazing, browsing, trampling, defecation, and seed dispersal by large herbivores can influence vegetation and soils in ways that may directly or indirectly contribute to climate change or mitigation. For example, changes in vegetation could impact wildfire regimes, carbon storage, and albedo, with ultimate impacts on climate. These processes may be influenced by herbivore species composition, density, and functional traits. The main aim of this systematic map is to synthesise the range of research on climate feedback and forcing effects from large herbivores (≥ 10 kg) in terrestrial ecosystems. We also aim to identify knowledge clusters and gaps in the research base, as well as assessing the potential for quantitative analyses. Methods A search of peer-reviewed and grey literature will be conducted using a range of bibliographic databases, search engines and websites. The search strategy will involve using a pre-defined search string with Boolean operators. All search results will be screened for relevance according to specific eligibility criteria. Screening will be conducted in two stages: all articles will initially be screened by title and abstract, then those that meet the eligibility criteria will be screened by full text. At both stages, articles will be excluded if they don’t meet all eligibility criteria or if they meet any exclusion criteria. All articles included as eligible after full text screening will be coded. At each stage (of screening and coding) a proportion of articles will be processed independently by two reviewers to assess inter-reviewer reliability and resolve differences. The evidence will be presented in a searchable database with accompanying visual outputs. A narrative synthesis will be provided outlining the range and distribution of evidence, knowledge gaps and clusters, potential bias, and areas for further research.