Rozprawy doktorskie na temat „Block turbo codes”
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Martin, Philippa Anne. "Adaptive iterative decoding : block turbo codes and multilevel codes". Thesis, University of Canterbury. Electrical and Electronic Engineering, 2001. http://hdl.handle.net/10092/7853.
Pełny tekst źródłaSholiyi, Abiodun Olugbenga. "Irregular block turbo codes for communication systems". Thesis, Swansea University, 2011. https://cronfa.swan.ac.uk/Record/cronfa43150.
Pełny tekst źródłaHirst, Simon. "Iterative decoding techniques for block based error correction codes". Thesis, Lancaster University, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.289060.
Pełny tekst źródłaWang, Charles C., i Tien M. Nguyen. "USING SHORT-BLOCK TURBO CODES FOR TELEMETRY AND COMMAND". International Foundation for Telemetering, 1999. http://hdl.handle.net/10150/608708.
Pełny tekst źródłaThe turbo code is a block code even though a convolutional encoder is used to construct codewords. Its performance depends on the code word length. Since the invention of the turbo code in 1993, most of the bit error rate (BER) evaluations have been performed using large block sizes, i.e., sizes greater than 1000, or even 10,000. However, for telemetry and command, a relatively short message (<500 bits) may be used. This paper investigates the turbo-coded BER performance for short packets. Fading channel is also considered. In addition, biased channel side information is adopted to improve the performance.
Šedý, Jakub. "Turbo konvoluční a turbo blokové kódy". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219287.
Pełny tekst źródłaGanti, Kamalakar. "Interleaver design for modified circular simplex turbo block coded modulator". Ohio : Ohio University, 2004. http://www.ohiolink.edu/etd/view.cgi?ohiou1107805760.
Pełny tekst źródłaPirestani, Shervin. "Source-controlled block turbo coding". Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 69 p, 2008. http://proquest.umi.com/pqdlink?did=994238721&sid=2&Fmt=2&clientId=8331&RQT=309&VName=PQD.
Pełny tekst źródłaChapalain-Le, Floc'h Nadine. "Application des Turbo Codes en blocs pour les réseaux locaux sans fil à haut débit". Brest, 2002. http://www.theses.fr/2002BRES2033.
Pełny tekst źródłaThis thesis deals with digital wireless communication and is divided in two parts. In the first part, the performance of block turbo codes (BTC) is evaluated and analysed in the HIPERLAN/2 (HIgh PERformance Local Area Network type 2) radio mobile environment. In this part, two soft-input soft-output decoding algorithms are studied, the sub-optimal Chase-Pyndiah algorithm of reasonable complexity that minimises the elementary code word error probability, and the optimal Nazarov algorithm that minimises the symbol error probability but is much more complex. This work shows that for channels with highly correlated atténuation (i. E. HIPERLAN/2 type channels), the distribution of the corrélation at the input of the turbo decoder has a big impact on the performance and that an interleaver should be defined in order to spread uniformly the correlated samples in the code matrix. The second part focuses on the study and optimisation of the implementation of the Chase-Pyndiah turbo decoding algorithm on the fixed point DSP TMS320C6201 (1600 Mips à 200MHz) provided by Texas Instrument. This work intends to demonstrate the feasibility of the implementation of block turbo codes on DSP while providing increasing data rates. The algorithm was implemented in C language in order to enable the code portability for other applications and on other DSP. With this implementation, a data rate of 394 Kb/s can be reached for the turbo decoding of the BTC(1024, 676) with 4 itérations
Chinchilla, Rigoberto. "Interleaver design for the circular simplex turbo block coded modulator". Ohio : Ohio University, 2003. http://www.ohiolink.edu/etd/view.cgi?ohiou1178129287.
Pełny tekst źródłaShaheem, Asri. "Iterative detection for wireless communications". University of Western Australia. School of Electrical, Electronic and Computer Engineering, 2008. http://theses.library.uwa.edu.au/adt-WU2008.0223.
Pełny tekst źródłaZhou, Rong. "Etude des Turbo codes en blocs Reed-Solomon et leurs applications". Rennes 1, 2005. http://www.theses.fr/2005REN1S027.
Pełny tekst źródłaMartins, João Paulo Trierveiler. "Turbo decodificadores de bloco de baixa potência para comunicação digital sem fio". Universidade de São Paulo, 2004. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-27092004-161308/.
Pełny tekst źródłaTurbo codes have become an important branch on channel coding research and have been adopted as standard in the third generation of mobile communication systems. Due to their high coding gain, turbo codes are expected to be part of the next generations of wireless networks standards. This coding scheme is based on iterative decoding, as soft input/soft output decoders produce an information refinement in each iteration. This dissertation shows the results of a comparative performance study of two different turbo coding schemes: block turbo codes and convolutional turbo codes. The results obtained show that the two schemes have complementary performance. It is necessary to specify a target in terms of bit error rate or signal/noise ratio. With the same C model an exploration aiming at reducing power consumption was done. Part of this exploration was done following a systematic methodology of data transfer and storage exploration (DTSE). With this exploration, a reduction of 34% on power consumption was estimated.
Gunnam, Kiran Kumar. "Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation". [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1049.
Pełny tekst źródłaNordmark, Oskar. "Turbo Code Performance Analysis Using Hardware Acceleration". Thesis, Linköpings universitet, Datorteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-137666.
Pełny tekst źródłaTa, Thomas. "Implémentation sur FPGA d'un turbo codeur-décodeur en blocs à haut débit avec une faible complexité". Rennes 1, 2003. http://www.theses.fr/2003REN1S145.
Pełny tekst źródłaDiatta, Ibrahima. "Étude de turbo codes blocs de Reed-Solomon appliqués à la boucle locale filaire haut débit". Paris 12, 2004. http://www.theses.fr/2004PA120036.
Pełny tekst źródłaThe increasing request for the flow of applications combined with the success of the ADSL (Asynchronous Digital Subscriber Line) pushed in the search of a new generation of technologies xDSL using the two-wire pair as a physical support of transmission. The importance of the flows aimed (up to 52 Mbits/s) by this new system called VDSL (Very high bit rate Digital Subscriber Line) requires sophisticated treatments of the signal and information to approach the capacity offered by the local loop. The objective of this thesis is the study of the performances of the block turbo codes Reed-Solomon in order to apply them to the VDSL system. After recalling the local loop principle in the network context, we describe the characteristics of the two-wire pair, which is the principal physical media of transmission used by the VDSL, before detailing the principal characteristics of the VDSL system. The last part of this thesis is devoted to the study of the block turbo codes and their application to the VDSL system. The turbo codes, whose principle of decoding is based on the algorithm of Pyndiah, made it possible to obtain very appreciable performances in terms of coding gain and bit rate, in spite of very constraining conditions of the channel. It is shown in particular that the appreciable ranging gain can be obtained for strong bit rates
Diatta, Ibrahima Geller Benoît Lemoine Jacques. "Étude de turbo codes blocs de Reed-Solomon appliqués à la boucle locale filaire haut débit". Créteil : Université de Paris-Val-de-Marne, 2004. http://doxa.scd.univ-paris12.fr:80/theses/th0214120.pdf.
Pełny tekst źródłaWavegedara, Kapila Chandika B. "Advanced receivers for space-time block-coded single-carrier transmissions over frequency-selective fading channels". Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/620.
Pełny tekst źródłaPiriou, Erwan. "Apport de la modélisation et de la synthèse haut niveau dans la conception d'architecture flexible dédiée aux turbocodes en blocs". Télécom Bretagne, 2007. http://www.theses.fr/2007TELB0029.
Pełny tekst źródłaThis thesis’ work continues previous research undertaken at the electronics department of the ENST Bretagne on the implementation of a turbo decoding architecture for product codes. The first research area studies the implementation of a flexible turbo decoding architecture. The second concerns the evolution of design flow, description languages and their applications. The results are validated by prototyping a platform. The proposed architecture includes two main design blocks. The first is a hardware module performing the decoding process. The second is a software based control unit. A study of system complexity was carried out to identify the various parameters of the application. The innovative aspect of our architecture is the flexibility in the choice of a component code (BCH or Reed Solomon) and its error correcting power. This is the first architecture known to date implementing Reed-Solomon block turbo codes. This work benefited from the knowledge of ENST Bretagne on turbocodes. Within the context of this thesis, a high level design flow was used, and the method was divided into two steps. First, a digital communication chain was developped with the help of the SystemC description language and System Studio design tool. Then, netlist descriptions were obtained by performing logic synthesis with SystemC compiler tool from Synopsys. The usage of a high level synthesis on sub-modules of the architecture allows us to quantify the benefits of this approach. The architecture was mapped to an Altera Stratix FPGA on a NIOS II development board. In fact, our choice of solutions from Altera was motivated by the fact that at the beginning of this work, Altera offered the best solution concerning software processors when compared to Xilinx. In our design, the control task is achieved by the NIOS II embedded processor. An avalon system bus binds the hardware decoding part and the processor. The turbo decoding process concerns BCH(32,26) (resp. (32,21)) and Reed Solomon (31,29) (resp. (31,27)) codes with t=1 (resp. T=2) as error correcting power. Many potential applications such as mobile communications, optical transmission, data storage and xDSL can benefit from flexible architectures dedicated to block turbo codes
Kwak, Yongjun. "Near Shannon Limit and Reduced Peak to Average Power Ratio Channel Coded OFDM". Thesis, Harvard University, 2012. http://dissertations.umi.com/gsas.harvard:10176.
Pełny tekst źródłaEngineering and Applied Sciences
Jacq, Sylvie. "Décodage itératif des codes produits : "turbo-codes en blocs", et évaluations de leurs performances pour des modulations MDP et MAQ sur canal de Gauss et de Rayleigh". Limoges, 1996. http://www.theses.fr/1996LIMO0056.
Pełny tekst źródłaHuang, Hsian-Cheng, i 黃憲政. "Investigate block turbo codes and performance analysis". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/17888468956101319955.
Pełny tekst źródła中華大學
電機工程學系碩士班
98
In the last ten years, the wireless communication techniques have been developed rapidly. In the future, the wireless communication systems will be requested to have higher data transmission rate. The transmitted signal will be seriously disturbed by the interference and noise. And then the system performance will be important. The block turbo codes have more excellent decoding performance and low complexity. Thus the decoding algorithm of block turbo codes will be investigated. Finally, for the IEEE 802.16 system, the performance of block turbo codes will be analyzed.
Li, Ssu-Hsien, i 李思賢. "Concatenation of Turbo Product Codes and Space Time Block Codes". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/42h364.
Pełny tekst źródła中原大學
電機工程研究所
92
Abstract The multipath wireless channel suffers severe attenuation. The Effective techniques to mitigate multipath fading are time and frequency diversity. Foschini,Gans and Telatar proved that multiple input multiple output can introduce spatial diversity and increased information capacity. These results have motivated a new area in error correcting codes . Space-Time Coding (STC) schemes can combine the channel code design and the use of multiple transmit antennas . The Space Time Trellis Codes (STTC) proposed by Tarkoh combine the trellis coding with symbol mapping into multiple transmit antennas . The Coding scheme expansion is done in antenna space. The Turbo Codes proposed by Berrou have powerful error correcting abilities. It would be benefit to design turbo codes for multiple antenna systems. To design space-time turbo codes with maximum space diversity and outstanding performance is still an open question. The Turbo Codes exhibited a troublesome error floor. Besides, the MAP algorithm which performs maximum likelihood bit estimation has a very large computation complexity . Recently turbo product codes (TPC) have been proposed . It can proved the performance of turbo codes. It is expected that TPC for multiple antenna systems would be powerful coding schemes with maximum diversity gain and large coding gain.
Yin, Bo. "Trellis decoding of 3-D block turbo codes". Thesis, 2002. http://spectrum.library.concordia.ca/1815/1/MQ72917.pdf.
Pełny tekst źródłaWang, Chin Tai, i 王璟玳. "A Novel Hybrid Decoder for Block Turbo Codes". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/02803500974514200902.
Pełny tekst źródła長庚大學
電機工程學系
98
This thesis proposes extrinsic-information-based decoding algorithms for original block turbo codes (BTCs) and hybrid block turbo codes. Since the number of algebraic decodings dominates the complexity of BTC decoding, it is important for BTC research to reduce the number of algebraic decodings without noticeable loss of bit-error rate performance. In each iterative decoding process, the algorithm compares the extrinsic information of the mth iteration and the (m-1)th iteration to determine when the HIHO decoding starts. Additionally, in BTC decoding, the decoder can use the other proposed algorithm to determine the rows/columns that are decoded using HIHO decoding to achieve the reduction of the number of algebraic decodings.
Lee, Jia-Jhan, i 李佳展. "Design Scheme of Space-Time Block Codes Concatenated with Turbo Codes". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/65108082199099493675.
Pełny tekst źródła中興大學
電機工程學系所
95
The wireless channel suffers severe attenuation caused by multipath fading. The effective technique to mitigate multipath fading is to use the time or frequency diversity. The communication system with multiple input multiple output can combat the channel attenuation by spatial diversity and increase the channel information capacity. The principle of space-time coding schemes is to combine the concept of channel coding design and multiple transmit antennas, which are then effectively applied to multipath wireless channel. Since the amount of data transfer of the modern digital or mobile communication is increasing, the reliability of the data transfer has become more and more important. Therefore, the error correction coding has played a very important role in wireless communication channel. The turbo code is one of the most popular error correction codes at present due to its good error correction ability. Besides, the turbo code is adopted in the 3G mobile communication standard. In this thesis, we present the application of several important concepts of wireless digital communications, i.e., serial concatenation, turbo coding, and temporal and antenna diversity . We combine the turbo code and the space-time block code and use the LogMAP algorithm to implement the soft in/soft out decoding algorithms of turbo code. Finally, we present our simulation results under different encoding scheme of the space time block code. Furthermore, we also present the comparison of the simulation result under different rate of space-time block codes but the same number of transmit antennas.
Chow, William. "Concatenated space-time block codes and turbo codes with unstructured interference". 2004. http://hdl.handle.net/1828/452.
Pełny tekst źródłaHuei-Min, Huang, i 黃暉閔. "Performance Evaluation of Space-Time Block Codes Concatenated with Turbo Codes and LDPC Codes". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/96876167066577233975.
Pełny tekst źródła國立中興大學
電機工程學系所
96
The multi-input-multi-output (MINO) technique is one in the breakthroughs of wireless communications. Space time block code (STBC) with maximal ratio receive combining (MRRC) is one of the systems using MIMO to reduce error rate by increasing the numbers of antennas in transmitter and receiver. The system performance can be greatly improved by applying error correcting coding, such as turbo codes and low density party check (LDPC) codes which are known because of performance approaching their to Shannon limits. In this thesis, we first introduce the traditional MRRC with 1 transmitter antenna and multi receiver antennas. Then we describe the property of STBC with multi transmitter antennas and multi receiver antennas. For error correcting codes, we use turbo codes and LDPC codes. In turbo codes, we use two parallel concatenated convolution codes for encoding and BCJR algorithm for decoding. For LDPC codes, we use IEEE 802.16e standard for encoding and sum-product algorithm for decoding. Finally, we combine turbo codes and LDPC codes with MIMO system and discuss the bandwidth efficiency of these combinations.
Chou, Chih Lin, i 周志霖. "Study on Improving the Performance for Block Turbo Codes". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/82122774067019421024.
Pełny tekst źródła長庚大學
電機工程學系
98
In a general decoding algorithm of block turbo codes(BTCs), the weighting factor α and reliability factors β are fixed in each decoding iteration. However, for time-variant channels predefined α and β are not appropriate in BTC decoding. The thesis proposes a method to set the values of α and β dynamically based on input and output values of the decoder. BTC decoding algorithms use an iterative decoding procedure to achieve high bit error rate performance typically with eight half decoding iterations. However, the requirement of the number of decoding iterations is related to the channel;i.e., the larger the noise is, the more number of iterations is required. Three novel stopping criterions are proposed in the thesis. Simulation results demonstrate that these proposed stopping criterions substantially reduce the number of decoding iterations. For example, about 64% iterations can be saved (on average) at Eb/No=5dB without the noticeable loss of BER performance.
Zheng, Yan-Xiu, i 鄭延修. "Inter-block permutation interleaver design for high throughput turbo codes". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/80119601906015718864.
Pełny tekst źródła國立交通大學
電信工程系所
96
With all its remarkable performance, the classic turbo code (TC) suffers from prolonged latency due to the relatively large iteration number and the lengthy interleaving delay required to ensure the desired error rate performance. We present a systematic approach that solves the dilemma between decoding latency and error rate performance. Our approach takes both algebraic and hardware constraints into account. From the algebraic point of view, we try to build large interleavers out of small interleavers. The structure of classic TC implies that we are constructing long classic TCs from short classic TCs in the spirit of R. M. Tanner. However, we go far beyond just presenting a new class of interleavers for classic TCs. The proposed inter-block permutation (IBP) interleavers meet all the implementation requirements for the parallel turbo decoding such as memory contention-free, low routing complexity and simple memory addressing circuitry. The IBP interleaver has simple algebraic form; it also allows flexible degrees of arallelism and is easily adaptable to variable interleaving lengths. Even without high throughput demand, the IBP design is capable of improving the distance property with increased equivalent interleaving length but not the decoding delay except for the initial blocks. We classify the IBP interleavers into block and stream ones. For both classes we derive codeword weight bounds for weight-2 input sequences that give us important guidelines for designing good IBP interleavers. We prove that the algebraic properties required to guarantee good distance properties satisfying the memory contention-free requirement as well. For block IBP interleavers, we propose memory mapping functions for flexible parallelism degrees and high-radix decoding units. A network-oriented design concept is introduced to reduce the routing complexity in the parallel decoding architectures. We suggest efficient interleaver design flows that offer a wide range of choices in the interleaving length. A VLSI design example is given to demonstrate that the proposed interleavers do yield high throughput/low complexity architecture and, at the same time, give excellent error rate performance. The stream-oriented IBP interleavers are designed for the pipeline decoding architecture which is suitable for high throughput applications but has to pay the price of large hardware complexity. In order to achieve optimal trade-off between hardware complexity and decoding throughput, a dynamic decoder architecture is proposed. We address the issues of decoding schedule and memory management and introduce the novel stopping mechanisms that incorporate both CRC code and sign check. With a proper decoding schedule, memory manager and early-stopping rule, we are able to reduce the hardware complexity and achieve improved error rate performance with a shorter average latency. In order to describe various parallel and pipeline iterative decoding schedules and analyze their behaviors, we develop a graphic tool called multi-stage factor graphs. Based on this new tool we derive a new decoding schedule which gives compatible error rate performance with less memory storage. For completeness, we show some irregular puncturing patterns that yield good error rate performance.
Lu, Pen Yao, i 呂本堯. "The Study of the Decoding Algorithms for Reed-Solomon Codes and Block Turbo Codes". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/75477674722052582492.
Pełny tekst źródłaBotha, P. R. (Philippus Rudolph). "Iterative decoding of space-time-frequency block coded mimo concatenated with LDPH codes". Diss., 2013. http://hdl.handle.net/2263/33344.
Pełny tekst źródłaDissertation (MEng)--University of Pretoria, 2013.
gm2014
Electrical, Electronic and Computer Engineering
unrestricted
Le, Nong. "A new distance-based algorithm for block turbo codes : from concept to implementation". Thesis, 2005. http://spectrum.library.concordia.ca/8469/1/MR10240.pdf.
Pełny tekst źródłaHuang, Kai Jie, i 黃楷傑. "An Improved Chase II Algorithm and the Application of Decoding Block Turbo Codes". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/70454072362999022385.
Pełny tekst źródła長庚大學
電機工程學研究所
97
This paper proposes a low-complex Chase-2 decoding algorithm and the decoding of block turbo codes (BTCs). In addition, we study the trend of extrinsic information to promote the bit-error-rate (BER) performance of BTCs. Chase proposed Chase-2 algorithm to reduce decoding complexity of soft-decision decoding for linear block codes. According to channel measurements, we can find a set of candidate codewords. From the set, we select the minimum squared Euclidean distance codeword D as the optimum decision, which reduces the complexity of the soft-decision decoding. This paper proposes a method to form a smaller candidate set to reduce the complexity of the traditional Chase algorithm. Simulation results show, the performance of threshold Chase-2 is almost the same as Chase-2. In [17], R. M. Pyndiah uses the maximum a posteriori (MAP) theorem to compute the extrinsic information of block turbo codes. We use Chase-2 to find the optimum decision D and the competing codeword. Then, we compute the soft outputs which are used to compute the extrinsic information. This paper proposes an improved Chase II algorithm and the application of decoding block turbo codes. By computer simulation, we set threshold equal to 1. The performance is almost the same as Chase-2, but we reduce the computation about 30.48%.
Chen, Hui Cheng, i 陳惠禎. "A Reliability-Based Soft-input Soft-output Decoding Algorithm for Block Turbo Codes". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/25225241013050853015.
Pełny tekst źródła長庚大學
電機工程學系
98
Block turbo codes (BTCs) was proposed by Pyndiah in 1998 and it have be shown the performance of BTCs close to the Shannnon limit. In order to achieve a reasonable decoding complexity, generally the number of the least reliable bits is set four in most of decoding process. However, the soft outputs in some ambiguous sequences are unreliable that will cause causing the loss of BER. This thesis proposes a decoding algorithm for improving the performance of BTCs. The algorithm utilizes the average reliability to increase the number of the least reliable bits for those ambiguous sequences to obtain more accurate soft outputs. Compared with Pyndiah’s algorithm, the proposed algorithm offers a substantial BER performance improvement in the fifth iteration with a neglect cost of the decoding complexity.
CHI, CHIA-HUNG, i 紀佳宏. "Study on Improving the Performance for Block Turbo Codes by Dynamically Estimating Weighting Factors Based on Mutual Information". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/d5775k.
Pełny tekst źródła明志科技大學
電子工程系碩士班
102
In a general decoding algorithm of block turbo codes(BTCs), the weighting factor α and reliability factor β are fixed in each static decoding iteration with increasing times. It’s difficult to decode codes under poor channel environment. However, the time-variant channels predefined α and β are not appropriate in BTC decoding because they are not easily being controlled. The thesis proposes a method to set the values of α and β dynamically based on input and output values of the decoder. BTC decoding algorithms use an iterative decoding procedure to achieve low bit error rate performance typically with eight half decoding iterations. However, the requirement for the number of decoding iterations is related to the channel; i.e. , the larger the noise is, the more the number of iterations is required. So in the traditional BTC decoders, we practically measure the input and output values of decoders, then establish entropy and mutual information concepts to make the decoding process work smoothly.
Liao, Jimmy J. M., i 廖俊閔. "Design and Implementation of Block Turbo Code Codec". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/pnsada.
Pełny tekst źródła國立交通大學
電子工程系所
96
In this thesis, a block turbo code of 802.16e is proposed. Unlike the conventional decoding algorithm requiring empirically derived parameters, the proposed geometric-like algorithm uses hamming distance to compensate the information. Not only improving the error performance, the proposed algorithm also facilitates hardware implementation. Moreover, a design methodology for parallel architecture is presented to meet various throughputs. The memory accessing hazard in parallel architecture can be overcome by the proposed multi-bank-array algorithm. The proposed algorithm is a partition and scheduling technique without extra memory. By the proposed algorithm and parallel design methodology, the block turbo code encoder and decoder defined in WiMAX(802.16e) is implemented. Note that, a design flow from algorithm level (in C language) to hardware level (in Verilog ) is presented. A systemC model is also built to provide a more efficient verification strategy and allows electronic system level design.
Vlok, Jacobus David. "Sparse graph codes on a multi-dimensional WCDMA platform". Diss., 2007. http://upetd.up.ac.za/thesis/available/etd-07042007-155428.
Pełny tekst źródłaChen, Zhi-Feng, i 陳志峰. "Turbo Block Coded Modulation with Interblock Memory". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/7na8nm.
Pełny tekst źródła中原大學
電機工程研究所
92
Turbo-codes are very powerful codes for power limited AWGN channels. The turbo-codes invented by Berrou et al. use two parallel-concatenated recursive systematic convolutional codes. The iterative decoding algorithm is good to operate at only a fraction of a dB from the Shannon limit. The discovery of turbo-codes does not put an end to the story of error control coding. On the contrary, it has resulted in a renaissance of coding research. By using the ‘turbo’ principle, many related codes have been discovering. The application of turbo-codes in bandwidth-efficient coded modulation techniques is one of the important issues. The coded modulation technique uses combined coding and modulation to achieve appreciable coding gains without sacrificing the bandwidth. Block coded modulation (BCM) is based on a block by block manner while trellis coded modulation (TCM) is based on a trellis code. We can easily construct BCM schemes with good error correcting abilities by choosing proper binary block codes. However, the huge decoding complexities for long block codes limit the practical usage of BCM with long block design. Block coded modulation with interblock memory (BCMIM) is an improved BCM scheme. Compared to BCM for which each block is independent of the others, the introduction of interblock coding can increase the coding rates and coding gains. The associated multi-stage decoding algorithm is optimum in each stage and has low decoding complexity. We’ll improve the bit error rate performance of BCMIM by introducing the concept of concatenated coding and iterative decoding. It is expected that further coding gains will be obtained.
Ku, Hsien-Chun, i 顧賢俊. "An Architecture of Decoder for Reed-Solomon Block Turbo Code". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/82810967468479543019.
Pełny tekst źródła中華大學
電機工程學系碩士班
98
In the last few years, error correcting codes have been investigated because of the rapid development of wireless communications. Reed-Solomon code is one of error correcting codes with a wide range of applications in digital communications and storage. Recently, block turbo codes using Reed-Solomon component codes have been investigated. This was motivated by the higher code rate property of Reed-Solomon codes and their efficiency for burst error correction. For the next generation wireless technologies, Reed-Solomon block turbo codes can offer a good trade-off between complexity and performance for ultra-high throughputs. In fact, the main advantage of Reed-Solomon block turbo codes is for high code rate application. In this thesis, Reed-Solomon block turbo codes will be investigated and a decoder architecture for (31,29)2 Reed-Solomon block turbo codes using step-by-step Reed-Solomon decoder will be proposed.
Chang, Wang-Yueh, i 張汪鉞. "Design and Implementation of high-speed step-by-step Reed-Solomon Block Turbo Code Decoder". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/82203425220273650664.
Pełny tekst źródła國立彰化師範大學
電信工程研究所
100
It is well known that the wireless communication technology has been developed towards broadband services. However, to keep the high quality and high throughput for wireless communication systems over wireless channel environment with noise and interferences is a real challenge. The forward error correction techniques can be employed to improve the performance and widely used in wireless communication systems. The concept of iterative decoding turbo code makes decoding performance close to the Shannon limit. Turbo code has established its future status in the wireless communication system. However, it has very high complexity and long latency delay. In this paper, based on the step-by-step decoding algorithm in RS codes, it has the properties of low-complexity and high-speed. A modified step-by-step decoding procedure for single-error-correcting RS codes is proposed. Moreover, a modified decoding procedure for Chase RS-BTC decoding with step-by-step RS decoding algorithm has also been proposed. The simulation result shows that the modified decoding procedure we proposed is improved for RS-BTC. This paper also proposed a high-speed step-by-step RS-BTC decoder architecture with low decoding complexity and short latency delay. The Verilog HDL is used here to construct RS-BTC decoder hardware and used to FPGA board to complete the decoder circuit design. This RS-BTC has a good balance between performance and complexity suitable to apply to the broadband wireless communication systems with high transmission speed and high bandwidth efficiency trends in the future.
Yin, Yizhi. "Le codage distribué pour un réseau de capteurs sans-fil basé sur les turbo codes en bloc". Phd thesis, 2012. http://tel.archives-ouvertes.fr/tel-00777396.
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