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Masgana, Delphine. "Injection de fautes et de logiciels sur les implémentations cryptographiques". Paris 7, 2012. http://www.theses.fr/2012PA077215.
Pełny tekst źródłaThe cryptography is very widespread inside smartcards or secure devices. These embedded cryptoSystems are proved theoretically secure. Nevertheless, they infère in far or near environment. So active perturbations, named fault analysis, or passive eavesdropping, called side-channel analysis, constitute real threats against hardware and software implementations. This thesis dealts with fault and software injections on cryptographie protocols. The fault analysis and side-channnel analysis give some more information on hardware and software implementations. The internai state of cryptographic computations, secret or private keys or private algorithms are all potential targets of this kind of analysis. In this thesis, a statistical analysis based on fault attack on the carry of Schnorr scheme operations gives access to private key in asymmetric signature or ciphering. Then, code injection in order to monitor memory cache of computer allows one to retrieve secret permutation table for stream cipher RC4, due to timing analysis on cache lines. Then, two differential analysis on internai rounds of AES enable to obtain secret key for the three different AES variants. Finally, a new consequence of fault model, which bypasses one instruction, allows one to take over a host. It is proved that it is important to protect cryptographic implémentations with proper countermeasures against fault analysis and side-channel analysis
Dumont, Mathieu. "Modélisation de l’injection de faute électromagnétique sur circuits intégrés sécurisés et contre-mesures". Thesis, Montpellier, 2020. http://www.theses.fr/2020MONTS031.
Pełny tekst źródłaThis thesis is devoted to the study of electromagnetic fault injection attack on se-cure integrated circuits. Electrical modeling permits to simulate the coupling between an EM probe injection and the circuit supply and ground grids in order to understand the effect of the EM pulse. This modeling is then applied on a logic circuit simulation with a D flip-flop and its components. The simulation results were used to determine the various faults that could be induced by this attack and to explain their formation. Measurements on a test circuit revealed the appearance of timing and sampling faults and validated ex-perimentally the proposed model. Finally, some countermeasures based on the model are proposed in order to increase the robustness of a circuit against electromagnetic fault in-jection
Mirbaha, Amir-Pasha. "Etude de la vulnérabilité des circuits cryptographiques l'injection de fautes par laser". Phd thesis, Ecole Nationale Supérieure des Mines de Saint-Etienne, 2011. http://tel.archives-ouvertes.fr/tel-00844751.
Pełny tekst źródłaTrabelsi, Oualid. "Méthodes pour la modélisation des injections de fautes électromagnétiques". Electronic Thesis or Diss., Institut polytechnique de Paris, 2021. http://www.theses.fr/2021IPPAT021.
Pełny tekst źródłaFault injection attacks represent a considerable threat to cyber-physical systems.Therefore, protection against these attacks is required to ensure a high level of security in sensitive applications such as the Internet of Things, smart devices or connected cars.Developing protection requires a good understanding of the attack mechanisms in order to propose effective countermeasures.In terms of fault injection methods, electromagnetic interference has proven to be an effective source of disruption, being less intrusive and with a low cost setup.Besides the adjustment of the injection parameters, the effectiveness of this attack mean lies in the choice of the probe that generates the electromagnetic radiation.The state of the art already proposes many works related to the design and characterization of this type of injector.However, the corresponding results point out to some difference between those from simulation and those from experimental tests.The first part of the thesis addresses the question of the efficiency of magnetic probes, with a focus on their properties.In order to compare the probes, we propose to observe the impact of electromagnetic pulses at the logic level, on particular targets such as FPGA.The characterization is also established according to the variation of the injection parameters such as the amplitude and the polarity of the pulse, the number of pulses or the injection time.These results allowed to converge on the optimal parameters that maximize the effect of the magnetic probes.The characterization is then extended to the architecture level on microcontroller targets.The purpose of the second contribution is to present an analysis approach, based on three generic methods, which are used to determine the vulnerabilities of microcontrollers with respect to instructions or data.These methods concern the identification of vulnerable elements at the architecture level, the analysis of fault models at the bit level, and finally the definition of the temporal fault status, i.e. transient or semi-persistent.Establishing the fault patterns, as well as the number of the impacted instructions or data, is an important milestone for the design of more robust countermeasures.Regarding the latter, instruction-level countermeasures have been proposed against software fault models.Currently, the most common mechanism is to apply a redundant execution of the program to be protected.However, this type of countermeasure is based on the assumption that a fault injection imply a single instruction jump.With respect to our observations, these countermeasures based on instruction-level duplication present vulnerabilities, which we identify and then correct
Le, Bouder Hélène. "UN FORMALISME UNIFIANT LES ATTAQUES PHYSIQUES SUR CIRCUITS CRYTOGRAPHIQUES ET SON EXPLOITATION AFIN DE COMPARER ET RECHERCHER DE NOUVELLES ATTAQUES". Thesis, Saint-Etienne, EMSE, 2014. http://www.theses.fr/2014EMSE0759/document.
Pełny tekst źródłaThe main subject of this work is the physical cryptanalysis of blocks ciphers. Even if cryptographic algorithms are properly designed mathematically, they may be vulnerable to physical attacks. Physical attacks are mainly divided in two families: the side channel attacks which are based on the observation of the circuit behaviour during the computation, and the fault injection attacks which consist in disturbing the computation in order to alter the correct progress of the algorithm. These attacks are used to target the cipher key or to reverse engineer the algorithm. A formalism is proposed in order to describe the two families in a unified way. Unifying the different attacks under a same formalism allows to deal with them with common mathematical tools. Additionally, it allows a comparison between different attacks. Using this framework, a generic method to assess the vulnerabilities of generalized Feistel networks to differential fault analysis is presented. This work is furthermore extended to improve a FIRE attack on DES-like cryptosystems with customized s-boxes
Moro, Nicolas. "Sécurisation de programmes assembleur face aux attaques visant les processeurs embarqués". Thesis, Paris 6, 2014. http://www.theses.fr/2014PA066616/document.
Pełny tekst źródłaThis thesis focuses on the security of embedded programs against fault injection attacks. Due to the spreadings of embedded systems in our common life, development of countermeasures is important.First, a fault model based on practical experiments with a pulsed electromagnetic fault injection technique has been built. The experimental results show that the injected faults were due to the corruption of the bus transfers between the Flash memory and the processor’s pipeline. Such faults enable to perform instruction replacements, instruction skips or to corrupt some data transfers from the Flash memory.Although replacing an instruction with another very specific one is very difficult to control, skipping an instruction seems much easier to perform in practice and has been observed very frequently. Furthermore many simple attacks can carried out with an instruction skip. A countermeasure that prevents such instruction skip attacks has been designed and formally verified with model-checking tool. The countermeasure replaces each instruction by a sequence of instructions. However, this countermeasure does not protect the data loads from the Flash memory. To do this, it can be combined with another assembly-level countermeasure that performs a fault detection. A first experimental test of these two countermeasures has been achieved, both on isolated instructions and complex codes from a FreeRTOS implementation. The proposed countermeasure appears to be a good complement for this detection countermeasure and allows to correct some of its flaws
Monnet, Yannick. "Étude et modélisation de circuits résistants aux attaques non intrusives par injection de fautes". Grenoble INPG, 2007. https://tel.archives-ouvertes.fr/tel-00163817.
Pełny tekst źródłaNew hardware cryptanalysis methods such as fault-based attacks have shown their efficiency to break cryptosystems. This work is focused on the development of new techniques and tools that enable the design of robust circuits against fault injection attacks (Differential Fault Analysis: DFA). The study and the design of resistant asynchronous circuits against these attacks are particularly addressed. We first specify a faults sensitivity evaluation of asynchronous circuits. Then, hardening techniques are proposed in order to improve circuits resistance and tolerance. Practical results are evaluated on asynchronous cryptographic circuits using a laser beam fault injection system. These results validate both the theoretical analysis and the hardening techniques, and confirm that asynchronous technology is an efficient solution to design secure systems
Moro, Nicolas. "Sécurisation de programmes assembleur face aux attaques visant les processeurs embarqués". Electronic Thesis or Diss., Paris 6, 2014. http://www.theses.fr/2014PA066616.
Pełny tekst źródłaThis thesis focuses on the security of embedded programs against fault injection attacks. Due to the spreadings of embedded systems in our common life, development of countermeasures is important.First, a fault model based on practical experiments with a pulsed electromagnetic fault injection technique has been built. The experimental results show that the injected faults were due to the corruption of the bus transfers between the Flash memory and the processor’s pipeline. Such faults enable to perform instruction replacements, instruction skips or to corrupt some data transfers from the Flash memory.Although replacing an instruction with another very specific one is very difficult to control, skipping an instruction seems much easier to perform in practice and has been observed very frequently. Furthermore many simple attacks can carried out with an instruction skip. A countermeasure that prevents such instruction skip attacks has been designed and formally verified with model-checking tool. The countermeasure replaces each instruction by a sequence of instructions. However, this countermeasure does not protect the data loads from the Flash memory. To do this, it can be combined with another assembly-level countermeasure that performs a fault detection. A first experimental test of these two countermeasures has been achieved, both on isolated instructions and complex codes from a FreeRTOS implementation. The proposed countermeasure appears to be a good complement for this detection countermeasure and allows to correct some of its flaws
Chamelot, Thomas. "Sécurisation de l’exécution des applications contre les attaques par injection de fautes par une contre-mesure intégrée au processeur". Electronic Thesis or Diss., Sorbonne université, 2022. http://www.theses.fr/2022SORUS417.
Pełny tekst źródłaEmbedded systems are ubiquitous in our everyday life. Those embedded systems, by their nomadic nature, are particularly sensitive to the so-called fault injection attacks. For example, an attacker might inject a physical perturbation in an integrated circuit to compromise the security features of the system. Originally used to compromise cryptographic systems, those attacks can now target any kind of system. Notably, those attacks enable to compromise the execution of a program. In this manuscript, we introduce a new security property to protect the execution of instructions in the microarchitecture: execution integrity. From this property, we describe the concept of SCI-FI, a counter-measure that ensures the protection of the whole instruction path thanks to code, control-flow and execution integrity properties. We build SCI-FI around a bit vector that we call pipeline state and that is composed of microarchitecture control signals. Two modules interact around the pipeline state to ensure the security properties. The first module computes a signature from the pipeline state to ensure code and control-flow integrity and partially execution integrity. The second module completes the execution integrity support in the microarchitecture thanks to a redundancy mechanism. We also propose a solution for indirect branches and interrupts that are required to design embedded systems. We implement two versions of SCI-FI, one built around a cryptographic primitive which provides the best security level and another lighter one built around a CRC to maximize the performances. We integrate SCI-FI into a 32 bits RISC-V processor, and we modify the LLVM compiler. We analyze the security provided by our two implementations and we show that SCI-FI, even with the lightweight implementation, is robust against state-of-the-art attacker. Finally, we evaluate the performances of our implementations through an ASIC synthesis and through the execution of the benchmark suite Embench-IoT. We show that SCI-FI has comparable performances to state-of-the-art counter-measures while ensuring a new security property: execution integrity
Faurax, Olivier. "Évaluation par simulation de la sécurité des circuits face aux attaques par faute". Phd thesis, Université de la Méditerranée - Aix-Marseille II, 2008. http://tel.archives-ouvertes.fr/tel-00368222.
Pełny tekst źródłaRécemment, des attaques sur les algorithmes de cryptographie basées sur l'utilisation de fautes ont fait leur apparition. L'ajout d'une faute lors d'un calcul du circuit permet d'obtenir un résultat faux. À partir d'un certain nombre de résultats corrects et de résultats faux correspondants, il est possible d'obtenir des informations secrètes et dans certains cas des clés cryptographiques complètes.
Cependant, les perturbations physiques utilisées en pratique (impulsion laser, radiations, changement rapide de la tension d'alimentation) correspondent rarement aux types de fautes nécessaires pour réaliser ces attaques théoriques.
Dans ce travail, nous proposons une méthodologie pour tester les circuits face aux attaques par faute en utilisant de la simulation. L'utilisation de la simulation permet de tester le circuit avant la réalisation physique mais nécessite beaucoup de
temps. C'est pour cela que notre méthodologie aide l'utilisateur à choisir les fautes les plus importantes pour réduire significativement le temps de simulation.
L'outil et la méthodologie associée ont été testés sur un circuit cryptographique (AES) en utilisant un modèle de faute utilisant des délais. Nous avons notamment montré que l'utilisation de délais pour réaliser des fautes permet de générer des fautes correspondantes à des attaques connues.
Lacruche, Marc. "Caractérisation sécuritaire de circuits basse-consommation face aux attaques par laser". Thesis, Aix-Marseille, 2016. http://www.theses.fr/2016AIXM4331/document.
Pełny tekst źródłaThe increasing complexity of integrated circuits and the explosion of the number of mobile devices today makes power consumption minimisation a priority in circuit design. However, it is necessary to make sure that it does not compromise the security of sensitive circuits. In this regard, physical attacks are a particular concern, as mobile devices are ideal targets for these attacks.This work aims at evaluating the impact of body-biasing on circuit vulnerability to laser attacks. These methods allow to dynamically adjust the performance/consumption ratio of a circuit by modifying the bias voltage of the body. It is divided in four chapters. It begins by introducing cryptography, physical attacks and low power design methods. Then the test bench used during this thesis is described, as well as the developpement work done in order to allow its automation. Then an initial study of the impact of short duration laser pulses on SRAM memories is presented. The third chapter reports the results of a laser fault injection campaign on memories subjected to Forward Body-Biasing. The results show a sensitivy increase of the circuits when supply voltage is lowered and FBB is activated. Based on these results, the last chapter introduces a method using the body-biasing and voltage scaling capabilities of a microcontroller to harden a hardware AES embedded on the latter.In conclusion, this works shows that low-power design methods can induce additional security risks if they are not carefully taken into account. However the additional capabilities of the circuits intended for power consumption reduction can be used in a different way to enhance device resillience to attacks
Bukasa, Sébanjila Kevin. "Analyse de vulnérabilité des systèmes embarqués face aux attaques physiques". Thesis, Rennes 1, 2019. http://www.theses.fr/2019REN1S042/document.
Pełny tekst źródłaDuring this thesis, we focused on the security of mobile devices. To do this, we explored physical attacks by perturbation (fault injections) as well as by observation, both based on electromagnetic emissions. We selected two types of targets representing two categories of mobile devices. On the one hand, the microcontrollers that equip IoT devices. And on the other hand the System-on-Chip (SoC) that can be found on smartphones. We focused on the chips designed by ARM. Through physical attacks we wanted to show that it was possible to affect the microarchitecture on which the entire functioning of these systems is based. All the protections that can be implemented later at the software level are based on the microarchitecture and therefore become ineffective when it is attacked. For IoT devices, we have highlighted the possibility of obtaining information or total control of the device by means of a fault injection. In this case, fault injections are used as software attack triggers. They also allow software protection to be bypassed. For smartphone devices, we were initially able to extract information contained within a SoC, using electromagnetic listening and characterization of its behavior. In a second step, we were able to show that in the event of a fault, random behaviours can occur, we characterized and proposed explanations for these behaviours. Demonstrating and on systems more advanced than IoT, it is still possible to use physical attacks. Finally, we proposed possible improvements in relation to our various findings during this work
Lacruche, Marc. "Caractérisation sécuritaire de circuits basse-consommation face aux attaques par laser". Electronic Thesis or Diss., Aix-Marseille, 2016. http://www.theses.fr/2016AIXM4331.
Pełny tekst źródłaThe increasing complexity of integrated circuits and the explosion of the number of mobile devices today makes power consumption minimisation a priority in circuit design. However, it is necessary to make sure that it does not compromise the security of sensitive circuits. In this regard, physical attacks are a particular concern, as mobile devices are ideal targets for these attacks.This work aims at evaluating the impact of body-biasing on circuit vulnerability to laser attacks. These methods allow to dynamically adjust the performance/consumption ratio of a circuit by modifying the bias voltage of the body. It is divided in four chapters. It begins by introducing cryptography, physical attacks and low power design methods. Then the test bench used during this thesis is described, as well as the developpement work done in order to allow its automation. Then an initial study of the impact of short duration laser pulses on SRAM memories is presented. The third chapter reports the results of a laser fault injection campaign on memories subjected to Forward Body-Biasing. The results show a sensitivy increase of the circuits when supply voltage is lowered and FBB is activated. Based on these results, the last chapter introduces a method using the body-biasing and voltage scaling capabilities of a microcontroller to harden a hardware AES embedded on the latter.In conclusion, this works shows that low-power design methods can induce additional security risks if they are not carefully taken into account. However the additional capabilities of the circuits intended for power consumption reduction can be used in a different way to enhance device resillience to attacks
Leroy, Damien. "Étude des modes de perturbation et susceptibilité des circuits numériques aux collisions de particules et aux attaques laser". Metz, 2006. http://docnum.univ-lorraine.fr/public/UPV-M/Theses/2006/Leroy.Damien.SMZ0628.pdf.
Pełny tekst źródłaMore and more sensitive data are stored inside smart cards, like bank account or car access codes. Recently, these security circuits have become a target for hackers who try to abuse these data. To achieve this goal, these attackers use the state of the art technologies like fault injection. To comply with the smart card market requirements, designers have to build protections against these attacks while keeping design costs as low as possible. These constraints should lead to a cost-efficient design and benefit from dedicated automatic protection methodologies. In this thesis we first study radiation sources able to tamper with silicon circuit behavior, and then we reveal similarities between laser attacks and radiation effects on a circuit. Then we show the specificities of secure circuit design and the spectrum of attacks used by hackers. The third part characterizes Single Event Transients (SET). A design methodology is proposed and implemented in two circuits, one dedicated to measuring laser-induced SET duration in logic gates, the other dedicated to measuring gate sensitivity to neutrons. This work concludes the review of results obtained after a laser shooting experiment campaign
Carré, Sébastien. "Attaques exploitant le temps de calcul : modélisation et protections". Electronic Thesis or Diss., Institut polytechnique de Paris, 2020. http://www.theses.fr/2020IPPAT045.
Pełny tekst źródłaA particularly efficient attack class is the class of cache timing attacks, that exploit the difference of time between cache memories and main memory, and are considered in this thesis with a cryptographic point of view. One aim of this thesis is to understand better such attacks.In other hand, the Rowhammer attack that induces perturbations in the capacitors of the DRAM modules in order to create an error called a fault that are also considered in this thesis with a cryptographic point of view.This thesis explores different microarchitectures features before exploring cache timing attacks and fault attack with the Rowhammer attack in mind. Based on the knowledge about these features, the thesis is split in two parts.The first part is about cache timing attacks. It gathers useful hardware and software features that should be considered to perform precise timing measurements. Those considerations were used to improve an existing attack on ECDSA on a known vulnerability.One result of this thesis will fill the gap between the general techniques used for the attacks and the exploitation of a vulnerability by searching such vulnerability in a binary by using dynamic analysis.In the second part of this thesis, fault attacks closed of the Rowhammer attack are considered. Like the first part, a way to perform software analysis is given.Eventually, in the second part a result about a so called persistent fault attack is improved.This thesis mainly focuses on improving existing attacks and on new ways to perform software analysis of cache timing attacks and attacks related to the Rowhammer attack in order to fill the needs of manufacturers to protect theirs products against those attacks
Gomina, Kamil. "Méthodologie et développement de solutions pour la sécurisation des circuits numériques face aux attaques en tensions". Thesis, Saint-Etienne, EMSE, 2014. http://www.theses.fr/2014EMSE0751.
Pełny tekst źródłaGeneral use products as mobile phones or smartcards manipulate confidential data. As such, the circuits composing them are more and more prone to physical attacks, which involve a threat for their security. As a result, SoC designers have to develop efficient countermeasures without increasing overall cost and complexity of the final application. The analysis of existing attacks on digital circuits leads to consider power attacks, in advanced technology nodes.First of all, the power signature of a circuit was determined at design time. To do so, an electrical model was suggested based on the current consumption and the overall power grid capacitance. The methodology to extract these parameters, as well as the evaluation of the model are presented. This model allows designers to anticipate information leakage at design time and to quantify the protection of countermeasures, as the use of integrated decoupling capacitors. Then, the study was dedicated to power glitch attacks. The different fault injection mechanisms were analyzed in details. From then on, a set of detection circuits were suggested and evaluated at design time and on silicon by electrical tests. Both the theoretical analysis and the given methodology were confirmed by the test campaigns.This work demonstrated that the design of low-cost solutions against passive and active power attacks can be achieved, and used in a large scale product development
Sauvanaud, Carla. "Monitoring et détection d'anomalie par apprentissage dans les infrastructures virtualisées". Thesis, Toulouse, INSA, 2016. http://www.theses.fr/2016ISAT0043/document.
Pełny tekst źródłaNowadays, the development of virtualization technologies as well as the development of the Internet contributed to the rise of the cloud computing model. A cloud computing enables the delivery of configurable computing resources while enabling convenient, on-demand network access to these resources. Resources hosted by a provider can be applications, development platforms or infrastructures. Over the past few years, computing systems are characterized by high development speed, parallelism, and the diversity of task to be handled by applications and services. In order to satisfy their Service Level Agreements (SLA) drawn up with users, cloud providers have to handle stringent dependability demands. Ensuring these demands while delivering various services makes clouds dependability a challenging task, especially because providers need to make their services available on demand. This task is all the more challenging that users expect cloud services to be at least as dependable as traditional computing systems. In this manuscript, we address the problem of anomaly detection in cloud services. A detection strategy for clouds should rely on several principal criteria. In particular it should adapt to workload changes and reconfigurations, and at the same time require short configurations durations and adapt to several types of services. Also, it should be performed online and automatic. Finally, such a strategy needs to tackle the detection of different types of anomalies namely errors, preliminary symptoms of SLA violation and SLA violations. We propose a new detection strategy based on system monitoring data. The data is collected online either from the service, or the underlying hypervisor(s) hosting the service. The strategy makes use of machine learning algorithms to classify anomalous behaviors of the service. Three techniques are used, using respectively algorithms with supervised learning, unsupervised learning or using a technique exploiting both types of learning. A new anomaly detection technique is developed based on online clustering, and allowing to handle possible changes in a service behavior. A cloud platform was deployed so as to evaluate the detection performances of our strategy. Moreover a fault injection tool was developed for the sake of two goals : the collection of service observations with anomalies so as to train detection models, and the evaluation of the strategy in presence of anomalies. The evaluation was applied to two case studies : a database management system and a virtual network function. Sensitivity analyzes show that detection performances of our strategy are high for the three anomaly types. The context for the generalization of the results is also discussed
Camponogara, Viera Raphael. "Simulating and modeling the effects of laser fault injection on integrated circuits". Thesis, Montpellier, 2018. http://www.theses.fr/2018MONTS072/document.
Pełny tekst źródłaLaser fault injections induce transient faults into ICs by locally generating transient currents that temporarily flip the outputs of the illuminated gates. Laser fault injection can be anticipated or studied by using simulation tools at different abstraction levels: physical, electrical or logical. At the electrical level, the classical laser-fault injection model is based on the addition of current sources to the various sensitive nodes of MOS transistors. However, this model does not take into account the large transient current components also induced between the VDD and GND of ICs designed with advanced CMOS technologies. These short-circuit currents provoke a significant IR drop that contribute to the fault injection process. This thesis describes our research on the assessment of this contribution. It shows by simulation and experiments that during laser fault injection campaigns, laser-induced IR drop is always present when considering circuits designed in deep submicron technologies. It introduces an enhanced electrical fault model taking the laser-induced IR-drop into account. It also proposes a methodology that uses standard CAD tools to allow the use of the enhanced electrical model to simulate laser-induced faults at the electrical level in large-scale circuits. On the basis of further simulations and experimental results, we found that, depending on the laser pulse characteristics, the number of injected faults may be underestimated by a factor as large as 3 if the laser-induced IR-drop is ignored. This could lead to incorrect estimations of the fault injection threshold, which is especially relevant to the design of countermeasure techniques for secure integrated systems. Furthermore, experimental and simulation results show that even though laser fault injection is a very local and accurate fault injection technique, the induced IR drops have a global effect spreading through the supply network. This gives experimental evidence that the effect of laser illumination is not as local as usually considered
Eynard, Julien. "Approche arithmétique RNS de la cryptographie asymétrique". Thesis, Paris 6, 2015. http://www.theses.fr/2015PA066107/document.
Pełny tekst źródłaThis thesis is at the crossroads between cryptography and computer arithmetic. It deals with enhancement of cryptographic primitives with regard to computation acceleration and protection against fault injections through the use of residue number systems (RNS) and their associated arithmetic. So as to contribute to secure the modular multiplication, which is a core operation for many asymmetric cryptographic primitives, a new modular reduction algorithm supplied with fault detection capability is presented. A formal proof guarantees that faults affecting one or more residues during a modular reduction are well detected. Furthermore, this approach is generalized to an arithmetic dedicated to non-prime finite fields Fps . Afterwards, RNS are used in lattice-based cryptography area. The aim is to exploit acceleration properties enabled by RNS, as it is widely done for finite field arithmetic. As first result, a new version of Babai’s round-off algorithm based on hybrid RNS-MRS representation is presented. Then, a new and specific acceleration technique enables to create a full RNS algorithm computing a close lattice vector
Zussa, Loic. "Étude des techniques d'injection de fautes par violation de contraintes temporelles permettant la cryptanalyse physique de circuits sécurisés". Thesis, Saint-Etienne, EMSE, 2014. http://www.theses.fr/2014EMSE0757/document.
Pełny tekst źródłaEven if a cryptographic algortihm could be mathematically secure, its physical implementation could be targeted by several attacks. This thesis focus on time-based fault injection mechanisms used for physical cryptanalysis of secure circuits.First, practical fault injections have been performed on a hardware AES implementation using non-invasive attacks : static and dynamic variations of the power supply voltage, frequency, temperature and electromagnetic environement. Then a comparison of these obtained faults led us to conclude that these different injection means share a common injection mecanism : timing constraints violations.An on-chip voltmeter has been designed and implemented to observe internal disturbences due to voltage glitchs. These observations led to a better understanding of the fault injection mecanism and to a better temporal accuracy.Then, a contermeasure has been designed and its effectiveness against electromagnetic attacks has been studied. Because of the electromagnetic pulses local effects, the aera effectively protected by the countermeasure is limited. The implementation of several countermeasures has been considered in order to extend the protected aera.Finally, a new attack path using the countermeasure detection threshold variations has been proposed and experimentaly validated. This attack exploit the electrical coupling between the AES and the coutnermeasure. Because of this coupling the countermeasure sensitivity variations are related to data handled by the AES
Daran, Muriel. "Modélisation des comportements erronés du logiciel et application à la validation des tests par injection de fautes". Phd thesis, Institut National Polytechnique de Toulouse - INPT, 1996. http://tel.archives-ouvertes.fr/tel-00142552.
Pełny tekst źródłaEynard, Julien. "Approche arithmétique RNS de la cryptographie asymétrique". Electronic Thesis or Diss., Paris 6, 2015. http://www.theses.fr/2015PA066107.
Pełny tekst źródłaThis thesis is at the crossroads between cryptography and computer arithmetic. It deals with enhancement of cryptographic primitives with regard to computation acceleration and protection against fault injections through the use of residue number systems (RNS) and their associated arithmetic. So as to contribute to secure the modular multiplication, which is a core operation for many asymmetric cryptographic primitives, a new modular reduction algorithm supplied with fault detection capability is presented. A formal proof guarantees that faults affecting one or more residues during a modular reduction are well detected. Furthermore, this approach is generalized to an arithmetic dedicated to non-prime finite fields Fps . Afterwards, RNS are used in lattice-based cryptography area. The aim is to exploit acceleration properties enabled by RNS, as it is widely done for finite field arithmetic. As first result, a new version of Babai’s round-off algorithm based on hybrid RNS-MRS representation is presented. Then, a new and specific acceleration technique enables to create a full RNS algorithm computing a close lattice vector
Monnet, Y. "Etude et modélisation de circuits résistants aux attaques non intrusives par injection de fautes". Phd thesis, 2007. http://tel.archives-ouvertes.fr/tel-00163817.
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