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Masgana, Delphine. "Injection de fautes et de logiciels sur les implémentations cryptographiques". Paris 7, 2012. http://www.theses.fr/2012PA077215.
Pełny tekst źródłaThe cryptography is very widespread inside smartcards or secure devices. These embedded cryptoSystems are proved theoretically secure. Nevertheless, they infère in far or near environment. So active perturbations, named fault analysis, or passive eavesdropping, called side-channel analysis, constitute real threats against hardware and software implementations. This thesis dealts with fault and software injections on cryptographie protocols. The fault analysis and side-channnel analysis give some more information on hardware and software implementations. The internai state of cryptographic computations, secret or private keys or private algorithms are all potential targets of this kind of analysis. In this thesis, a statistical analysis based on fault attack on the carry of Schnorr scheme operations gives access to private key in asymmetric signature or ciphering. Then, code injection in order to monitor memory cache of computer allows one to retrieve secret permutation table for stream cipher RC4, due to timing analysis on cache lines. Then, two differential analysis on internai rounds of AES enable to obtain secret key for the three different AES variants. Finally, a new consequence of fault model, which bypasses one instruction, allows one to take over a host. It is proved that it is important to protect cryptographic implémentations with proper countermeasures against fault analysis and side-channel analysis
Dumont, Mathieu. "Modélisation de l’injection de faute électromagnétique sur circuits intégrés sécurisés et contre-mesures". Thesis, Montpellier, 2020. http://www.theses.fr/2020MONTS031.
Pełny tekst źródłaThis thesis is devoted to the study of electromagnetic fault injection attack on se-cure integrated circuits. Electrical modeling permits to simulate the coupling between an EM probe injection and the circuit supply and ground grids in order to understand the effect of the EM pulse. This modeling is then applied on a logic circuit simulation with a D flip-flop and its components. The simulation results were used to determine the various faults that could be induced by this attack and to explain their formation. Measurements on a test circuit revealed the appearance of timing and sampling faults and validated ex-perimentally the proposed model. Finally, some countermeasures based on the model are proposed in order to increase the robustness of a circuit against electromagnetic fault in-jection
Mirbaha, Amir-Pasha. "Etude de la vulnérabilité des circuits cryptographiques l'injection de fautes par laser". Phd thesis, Ecole Nationale Supérieure des Mines de Saint-Etienne, 2011. http://tel.archives-ouvertes.fr/tel-00844751.
Pełny tekst źródłaTrabelsi, Oualid. "Méthodes pour la modélisation des injections de fautes électromagnétiques". Electronic Thesis or Diss., Institut polytechnique de Paris, 2021. http://www.theses.fr/2021IPPAT021.
Pełny tekst źródłaFault injection attacks represent a considerable threat to cyber-physical systems.Therefore, protection against these attacks is required to ensure a high level of security in sensitive applications such as the Internet of Things, smart devices or connected cars.Developing protection requires a good understanding of the attack mechanisms in order to propose effective countermeasures.In terms of fault injection methods, electromagnetic interference has proven to be an effective source of disruption, being less intrusive and with a low cost setup.Besides the adjustment of the injection parameters, the effectiveness of this attack mean lies in the choice of the probe that generates the electromagnetic radiation.The state of the art already proposes many works related to the design and characterization of this type of injector.However, the corresponding results point out to some difference between those from simulation and those from experimental tests.The first part of the thesis addresses the question of the efficiency of magnetic probes, with a focus on their properties.In order to compare the probes, we propose to observe the impact of electromagnetic pulses at the logic level, on particular targets such as FPGA.The characterization is also established according to the variation of the injection parameters such as the amplitude and the polarity of the pulse, the number of pulses or the injection time.These results allowed to converge on the optimal parameters that maximize the effect of the magnetic probes.The characterization is then extended to the architecture level on microcontroller targets.The purpose of the second contribution is to present an analysis approach, based on three generic methods, which are used to determine the vulnerabilities of microcontrollers with respect to instructions or data.These methods concern the identification of vulnerable elements at the architecture level, the analysis of fault models at the bit level, and finally the definition of the temporal fault status, i.e. transient or semi-persistent.Establishing the fault patterns, as well as the number of the impacted instructions or data, is an important milestone for the design of more robust countermeasures.Regarding the latter, instruction-level countermeasures have been proposed against software fault models.Currently, the most common mechanism is to apply a redundant execution of the program to be protected.However, this type of countermeasure is based on the assumption that a fault injection imply a single instruction jump.With respect to our observations, these countermeasures based on instruction-level duplication present vulnerabilities, which we identify and then correct
Le, Bouder Hélène. "UN FORMALISME UNIFIANT LES ATTAQUES PHYSIQUES SUR CIRCUITS CRYTOGRAPHIQUES ET SON EXPLOITATION AFIN DE COMPARER ET RECHERCHER DE NOUVELLES ATTAQUES". Thesis, Saint-Etienne, EMSE, 2014. http://www.theses.fr/2014EMSE0759/document.
Pełny tekst źródłaThe main subject of this work is the physical cryptanalysis of blocks ciphers. Even if cryptographic algorithms are properly designed mathematically, they may be vulnerable to physical attacks. Physical attacks are mainly divided in two families: the side channel attacks which are based on the observation of the circuit behaviour during the computation, and the fault injection attacks which consist in disturbing the computation in order to alter the correct progress of the algorithm. These attacks are used to target the cipher key or to reverse engineer the algorithm. A formalism is proposed in order to describe the two families in a unified way. Unifying the different attacks under a same formalism allows to deal with them with common mathematical tools. Additionally, it allows a comparison between different attacks. Using this framework, a generic method to assess the vulnerabilities of generalized Feistel networks to differential fault analysis is presented. This work is furthermore extended to improve a FIRE attack on DES-like cryptosystems with customized s-boxes
Moro, Nicolas. "Sécurisation de programmes assembleur face aux attaques visant les processeurs embarqués". Thesis, Paris 6, 2014. http://www.theses.fr/2014PA066616/document.
Pełny tekst źródłaThis thesis focuses on the security of embedded programs against fault injection attacks. Due to the spreadings of embedded systems in our common life, development of countermeasures is important.First, a fault model based on practical experiments with a pulsed electromagnetic fault injection technique has been built. The experimental results show that the injected faults were due to the corruption of the bus transfers between the Flash memory and the processor’s pipeline. Such faults enable to perform instruction replacements, instruction skips or to corrupt some data transfers from the Flash memory.Although replacing an instruction with another very specific one is very difficult to control, skipping an instruction seems much easier to perform in practice and has been observed very frequently. Furthermore many simple attacks can carried out with an instruction skip. A countermeasure that prevents such instruction skip attacks has been designed and formally verified with model-checking tool. The countermeasure replaces each instruction by a sequence of instructions. However, this countermeasure does not protect the data loads from the Flash memory. To do this, it can be combined with another assembly-level countermeasure that performs a fault detection. A first experimental test of these two countermeasures has been achieved, both on isolated instructions and complex codes from a FreeRTOS implementation. The proposed countermeasure appears to be a good complement for this detection countermeasure and allows to correct some of its flaws
Monnet, Yannick. "Étude et modélisation de circuits résistants aux attaques non intrusives par injection de fautes". Grenoble INPG, 2007. https://tel.archives-ouvertes.fr/tel-00163817.
Pełny tekst źródłaNew hardware cryptanalysis methods such as fault-based attacks have shown their efficiency to break cryptosystems. This work is focused on the development of new techniques and tools that enable the design of robust circuits against fault injection attacks (Differential Fault Analysis: DFA). The study and the design of resistant asynchronous circuits against these attacks are particularly addressed. We first specify a faults sensitivity evaluation of asynchronous circuits. Then, hardening techniques are proposed in order to improve circuits resistance and tolerance. Practical results are evaluated on asynchronous cryptographic circuits using a laser beam fault injection system. These results validate both the theoretical analysis and the hardening techniques, and confirm that asynchronous technology is an efficient solution to design secure systems
Moro, Nicolas. "Sécurisation de programmes assembleur face aux attaques visant les processeurs embarqués". Electronic Thesis or Diss., Paris 6, 2014. http://www.theses.fr/2014PA066616.
Pełny tekst źródłaThis thesis focuses on the security of embedded programs against fault injection attacks. Due to the spreadings of embedded systems in our common life, development of countermeasures is important.First, a fault model based on practical experiments with a pulsed electromagnetic fault injection technique has been built. The experimental results show that the injected faults were due to the corruption of the bus transfers between the Flash memory and the processor’s pipeline. Such faults enable to perform instruction replacements, instruction skips or to corrupt some data transfers from the Flash memory.Although replacing an instruction with another very specific one is very difficult to control, skipping an instruction seems much easier to perform in practice and has been observed very frequently. Furthermore many simple attacks can carried out with an instruction skip. A countermeasure that prevents such instruction skip attacks has been designed and formally verified with model-checking tool. The countermeasure replaces each instruction by a sequence of instructions. However, this countermeasure does not protect the data loads from the Flash memory. To do this, it can be combined with another assembly-level countermeasure that performs a fault detection. A first experimental test of these two countermeasures has been achieved, both on isolated instructions and complex codes from a FreeRTOS implementation. The proposed countermeasure appears to be a good complement for this detection countermeasure and allows to correct some of its flaws
Chamelot, Thomas. "Sécurisation de l’exécution des applications contre les attaques par injection de fautes par une contre-mesure intégrée au processeur". Electronic Thesis or Diss., Sorbonne université, 2022. http://www.theses.fr/2022SORUS417.
Pełny tekst źródłaEmbedded systems are ubiquitous in our everyday life. Those embedded systems, by their nomadic nature, are particularly sensitive to the so-called fault injection attacks. For example, an attacker might inject a physical perturbation in an integrated circuit to compromise the security features of the system. Originally used to compromise cryptographic systems, those attacks can now target any kind of system. Notably, those attacks enable to compromise the execution of a program. In this manuscript, we introduce a new security property to protect the execution of instructions in the microarchitecture: execution integrity. From this property, we describe the concept of SCI-FI, a counter-measure that ensures the protection of the whole instruction path thanks to code, control-flow and execution integrity properties. We build SCI-FI around a bit vector that we call pipeline state and that is composed of microarchitecture control signals. Two modules interact around the pipeline state to ensure the security properties. The first module computes a signature from the pipeline state to ensure code and control-flow integrity and partially execution integrity. The second module completes the execution integrity support in the microarchitecture thanks to a redundancy mechanism. We also propose a solution for indirect branches and interrupts that are required to design embedded systems. We implement two versions of SCI-FI, one built around a cryptographic primitive which provides the best security level and another lighter one built around a CRC to maximize the performances. We integrate SCI-FI into a 32 bits RISC-V processor, and we modify the LLVM compiler. We analyze the security provided by our two implementations and we show that SCI-FI, even with the lightweight implementation, is robust against state-of-the-art attacker. Finally, we evaluate the performances of our implementations through an ASIC synthesis and through the execution of the benchmark suite Embench-IoT. We show that SCI-FI has comparable performances to state-of-the-art counter-measures while ensuring a new security property: execution integrity
Faurax, Olivier. "Évaluation par simulation de la sécurité des circuits face aux attaques par faute". Phd thesis, Université de la Méditerranée - Aix-Marseille II, 2008. http://tel.archives-ouvertes.fr/tel-00368222.
Pełny tekst źródłaRécemment, des attaques sur les algorithmes de cryptographie basées sur l'utilisation de fautes ont fait leur apparition. L'ajout d'une faute lors d'un calcul du circuit permet d'obtenir un résultat faux. À partir d'un certain nombre de résultats corrects et de résultats faux correspondants, il est possible d'obtenir des informations secrètes et dans certains cas des clés cryptographiques complètes.
Cependant, les perturbations physiques utilisées en pratique (impulsion laser, radiations, changement rapide de la tension d'alimentation) correspondent rarement aux types de fautes nécessaires pour réaliser ces attaques théoriques.
Dans ce travail, nous proposons une méthodologie pour tester les circuits face aux attaques par faute en utilisant de la simulation. L'utilisation de la simulation permet de tester le circuit avant la réalisation physique mais nécessite beaucoup de
temps. C'est pour cela que notre méthodologie aide l'utilisateur à choisir les fautes les plus importantes pour réduire significativement le temps de simulation.
L'outil et la méthodologie associée ont été testés sur un circuit cryptographique (AES) en utilisant un modèle de faute utilisant des délais. Nous avons notamment montré que l'utilisation de délais pour réaliser des fautes permet de générer des fautes correspondantes à des attaques connues.