Artykuły w czasopismach na temat „Application specific instruction-set processor (ASIP)”
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Imai, Masaharu, Yoshinori Takeuchi, Keishi Sakanushi i Nagisa Ishiura. "Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP)". IPSJ Transactions on System LSI Design Methodology 3 (2010): 161–78. http://dx.doi.org/10.2197/ipsjtsldm.3.161.
Pełny tekst źródłaSharma, Poonam, Ashwani Kumar Dubey i Ayush Goyal. "Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier". Recent Patents on Engineering 13, nr 2 (27.05.2019): 174–80. http://dx.doi.org/10.2174/1872212112666180810150357.
Pełny tekst źródłaXin, Yao, Will X. Y. Li, Zhaorui Zhang, Ray C. C. Cheung, Dong Song i Theodore W. Berger. "An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics". IEEE/ACM Transactions on Computational Biology and Bioinformatics 12, nr 5 (1.09.2015): 1034–47. http://dx.doi.org/10.1109/tcbb.2015.2440248.
Pełny tekst źródłaSafaei Mehrabani, Yavar. "Synthesis of an Application Specific Instruction Set Processor (ASIP) for RIPEMD-160 Hash Algorithm". International Journal of Electronics Letters 7, nr 2 (25.05.2018): 154–65. http://dx.doi.org/10.1080/21681724.2018.1477182.
Pełny tekst źródłaZhang, Diandian, Li Lu, Jeronimo Castrillon, Torsten Kempf, Gerd Ascheid, Rainer Leupers i Bart Vanthournout. "Efficient Implementation of Application-Aware Spinlock Control in MPSoCs". International Journal of Embedded and Real-Time Communication Systems 4, nr 1 (styczeń 2013): 64–84. http://dx.doi.org/10.4018/jertcs.2013010104.
Pełny tekst źródłaIwaizumi, Hiroki, Shingo Yoshizawa i Yoshikazu Miyanaga. "A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems". VLSI Design 2013 (18.03.2013): 1–10. http://dx.doi.org/10.1155/2013/625019.
Pełny tekst źródłaQiao, Wan, i Dake Liu. "A scalable ASIP for BP Polar decoding with multiple code lengths". MATEC Web of Conferences 232 (2018): 01046. http://dx.doi.org/10.1051/matecconf/201823201046.
Pełny tekst źródłaWong, Tingh Wee, Bryan Ng i Chee Onn Wong. "Encoding Custom Instruction Generation as Satisfiability Problem". Advanced Materials Research 403-408 (listopad 2011): 502–10. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.502.
Pełny tekst źródłaFischer, Dirk, Jürgen Teich, Ralph Weper i Michael Thies. "BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs". Journal of Circuits, Systems and Computers 12, nr 03 (czerwiec 2003): 353–75. http://dx.doi.org/10.1142/s0218126603000799.
Pełny tekst źródłaAhmed, O., S. Areibi i G. Grewal. "Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm". International Journal of Reconfigurable Computing 2013 (2013): 1–33. http://dx.doi.org/10.1155/2013/681894.
Pełny tekst źródłaSalmela, Perttu, Adrian Burian, Tuomas Järvinen, Aki Happonen i Jarmo Henrik Takala. "Low-Complexity Inverse Square Root Approximation for Baseband Matrix Operations". ISRN Signal Processing 2011 (16.02.2011): 1–8. http://dx.doi.org/10.5402/2011/615934.
Pełny tekst źródłaCATANIA, VINCENZO, MAURIZIO PALESI i DAVIDE PATTI. "ANALYSIS AND TOOLS FOR THE DESIGN OF VLIW EMBEDDED SYSTEMS IN A MULTI-OBJECTIVE SCENARIO". Journal of Circuits, Systems and Computers 16, nr 05 (październik 2007): 819–46. http://dx.doi.org/10.1142/s0218126607003915.
Pełny tekst źródłaUrban, Roberto, Heinrich T. Vierhaus, Mario Schölzel, Enrico Altmann i Horst Seelig. "Non-Cyclic Design Space Exploration for ASIPs — Compiler-Centered Microprocessor Design (CoMet)". Journal of Circuits, Systems and Computers 25, nr 03 (28.12.2015): 1640012. http://dx.doi.org/10.1142/s0218126616400120.
Pełny tekst źródłaMeloni, Paolo, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo i Menno Lindwer. "Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper". VLSI Design 2012 (29.03.2012): 1–16. http://dx.doi.org/10.1155/2012/580584.
Pełny tekst źródłaKammler, David, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers i Heinrich Meyr. "Automatic Generation of Memory Interfaces for ASIPs". International Journal of Embedded and Real-Time Communication Systems 1, nr 3 (lipiec 2010): 1–23. http://dx.doi.org/10.4018/jertcs.2010070101.
Pełny tekst źródłaYoshitomi, Hiroyuki. "OrientalHydrocyphon(Coleoptera: Scirtidae: Scirtinae): Seven New Species from Indonesia, Thailand, Malaysia, and India". Psyche: A Journal of Entomology 2012 (2012): 1–16. http://dx.doi.org/10.1155/2012/603875.
Pełny tekst źródłaRadhakrishnan, S., H. Guo, S. Parameswaran i A. Ignjatovic. "HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors". IET Computers & Digital Techniques 3, nr 1 (2009): 94. http://dx.doi.org/10.1049/iet-cdt:20080005.
Pełny tekst źródłaShen, Zheng, Hu He, Yanjun Zhang i Yihe Sun. "A Video Specific Instruction Set Architecture for ASIP design". VLSI Design 2007 (15.11.2007): 1–7. http://dx.doi.org/10.1155/2007/58431.
Pełny tekst źródłaAntikainen, Juho, Perttu Salmela, Olli Silvén, Markku Juntti, Jarmo Takala i Markus Myllylä. "Application-Specific Instruction Set Processor Implementation of List Sphere Detector". EURASIP Journal on Embedded Systems 2007 (2007): 1–14. http://dx.doi.org/10.1155/2007/54173.
Pełny tekst źródłaAntikainen, Juho, Perttu Salmela, Olli Silvén, Markku Juntti, Jarmo Takala i Markus Myllylä. "Application-Specific Instruction Set Processor Implementation of List Sphere Detector". EURASIP Journal on Embedded Systems 2007, nr 1 (2007): 054173. http://dx.doi.org/10.1186/1687-3963-2007-054173.
Pełny tekst źródłaSisto, A., L. Pilato, R. Serventi, S. Saponara i L. Fanucci. "Application specific instruction set processor for sensor conditioning in automotive applications". Microprocessors and Microsystems 47 (listopad 2016): 375–84. http://dx.doi.org/10.1016/j.micpro.2016.10.001.
Pełny tekst źródłaSaponara, Sergio, Luca Fanucci, Stefano Marsi, Giovanni Ramponi, David Kammler i Ernst Martin Witte. "Application-Specific Instruction-Set Processor for Retinex-Like Image and Video Processing". IEEE Transactions on Circuits and Systems II: Express Briefs 54, nr 7 (lipiec 2007): 596–600. http://dx.doi.org/10.1109/tcsii.2007.896778.
Pełny tekst źródłaPeters, H., R. Sethuraman, A. Beric, P. Meuwissen, S. Balakrishnan, C. A. A. Pinto, W. Kruijtzer i in. "Application specific instruction-set processor template for motion estimation in video applications". IEEE Transactions on Circuits and Systems for Video Technology 15, nr 4 (kwiecień 2005): 508–27. http://dx.doi.org/10.1109/tcsvt.2005.844462.
Pełny tekst źródłaHoffmann, A., T. Kogel, A. Nohl, G. Braun, O. Schliebusch, O. Wahlen, A. Wieferink i H. Meyr. "A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, nr 11 (2001): 1338–54. http://dx.doi.org/10.1109/43.959863.
Pełny tekst źródłaChoi, Seung-Hyun, Tae-Moon Roh, Yong Ho Song i Seong-Won Lee. "Design of an application specific instruction set processor for a universal bitstream codec". IEICE Electronics Express 11, nr 24 (2014): 20141047. http://dx.doi.org/10.1587/elex.11.20141047.
Pełny tekst źródłaZhaohui Liu, K. Dickson i J. V. McCanny. "Application-specific instruction set processor for SoC implementation of modern signal processing algorithms". IEEE Transactions on Circuits and Systems I: Regular Papers 52, nr 4 (kwiecień 2005): 755–65. http://dx.doi.org/10.1109/tcsi.2005.844109.
Pełny tekst źródłaMbaye, Mame Maria, Normand Bélanger, Yvon Savaria i Samuel Pierre. "A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration". Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 47, nr 3 (27.03.2007): 297–315. http://dx.doi.org/10.1007/s11265-007-0050-0.
Pełny tekst źródłaBytyn, Andreas, Rainer Leupers i Gerd Ascheid. "ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs". IEEE Open Journal of Circuits and Systems 2 (2021): 3–15. http://dx.doi.org/10.1109/ojcas.2020.3037758.
Pełny tekst źródłaMooney, James, Abdulhussain E. Mahdi i Mark Halton. "Application-Specific Instruction-Set Processor for Control of Multi-Rail DC-DC Converter Systems". IEEE Transactions on Circuits and Systems I: Regular Papers 60, nr 1 (styczeń 2013): 243–54. http://dx.doi.org/10.1109/tcsi.2012.2215783.
Pełny tekst źródłaHeo, Ingoo, Minsu Kim, Yongje Lee, Changho Choi, Jinyong Lee, Brent Byunghoon Kang i Yunheung Paek. "Implementing an Application-Specific Instruction-Set Processor for System-Level Dynamic Program Analysis Engines". ACM Transactions on Design Automation of Electronic Systems 20, nr 4 (28.09.2015): 1–32. http://dx.doi.org/10.1145/2746238.
Pełny tekst źródłaZHANG, Yuli, Jun HAN, Xinqian WENG, Zhongzhu HE i Xiaoyang ZENG. "Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm". IEICE Transactions on Electronics E95.C, nr 8 (2012): 1415–26. http://dx.doi.org/10.1587/transele.e95.c.1415.
Pełny tekst źródłaTamagnone, M., M. Martina i G. Masera. "An application specific instruction set processor based implementation for signal detection in multiple antenna systems". Microprocessors and Microsystems 36, nr 3 (maj 2012): 245–56. http://dx.doi.org/10.1016/j.micpro.2011.11.003.
Pełny tekst źródłaXIAO, Shanlin, Tsuyoshi ISSHIKI, Dongju LI i Hiroaki KUNIEDA. "Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm". IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100.A, nr 7 (2017): 1384–95. http://dx.doi.org/10.1587/transfun.e100.a.1384.
Pełny tekst źródłaGuan, Xuan, Yunsi Fei i Hai Lin. "Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, nr 3 (marzec 2012): 551–63. http://dx.doi.org/10.1109/tvlsi.2011.2105512.
Pełny tekst źródłaLin, Hai, i Yunsi Fei. "Resource Sharing of Pipelined Custom Hardware Extension for Energy-Efficient Application-Specific Instruction Set Processor Design". ACM Transactions on Design Automation of Electronic Systems 17, nr 4 (październik 2012): 1–20. http://dx.doi.org/10.1145/2348839.2348843.
Pełny tekst źródłaAbdel All, Mahmoud, Hanan M. Hassan, Medhat Hamdy, Omar A. Nasr, Karim Mohamed i Ahmed F. Shalash. "Design and implementation of application‐specific instruction‐set processor design for high‐throughput multi‐standard wireless orthogonal frequency division multiplexing baseband processor". IET Circuits, Devices & Systems 9, nr 3 (maj 2015): 191–203. http://dx.doi.org/10.1049/iet-cds.2014.0046.
Pełny tekst źródłaK.Jain, M., i Deepak Gour. "Comparison between the Simulator and Scheduler based approach of Design Space Exploration for Application Specific Instruction set Processor". International Journal of Computer Applications 43, nr 5 (30.04.2012): 14–19. http://dx.doi.org/10.5120/6098-8290.
Pełny tekst źródłaZiebinski, Adam, i Stanwlaw Swierc. "Soft Core Processor Generated Based on the Machine Code of the Application". Journal of Circuits, Systems and Computers 25, nr 04 (2.02.2016): 1650029. http://dx.doi.org/10.1142/s0218126616500298.
Pełny tekst źródłaSalmela, Perttu, Harri Sorokin i Jarmo Takala. "A Programmable Max-Log-MAP Turbo Decoder Implementation". VLSI Design 2008 (22.12.2008): 1–17. http://dx.doi.org/10.1155/2008/319095.
Pełny tekst źródłaZhang, Diandian, Han Zhang, Jeronimo Castrillon, Torsten Kempf, Bart Vanthournout, Gerd Ascheid i Rainer Leupers. "Optimized Communication Architecture of MPSoCs with a Hardware Scheduler". International Journal of Embedded and Real-Time Communication Systems 2, nr 3 (lipiec 2011): 1–20. http://dx.doi.org/10.4018/jertcs.2011070101.
Pełny tekst źródłaVenkanna, Mood, i Rameshwar Rao. "Static Worst-Case Execution Time Optimization using DPSO for ASIP Architecture". Ingeniería Solidaria 14, nr 25 (1.05.2018): 1–11. http://dx.doi.org/10.16925/.v14i0.2230.
Pełny tekst źródłaBispo, João, Nuno Paulino, João M. P. Cardoso i João Canas Ferreira. "Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units". International Journal of Reconfigurable Computing 2013 (2013): 1–20. http://dx.doi.org/10.1155/2013/340316.
Pełny tekst źródłaSugiura, Tomoki, Masaharu Imai, Jaehoon Yu i Yoshinori Takeuchi. "A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems". Journal of Information Processing 25 (2017): 210–19. http://dx.doi.org/10.2197/ipsjjip.25.210.
Pełny tekst źródłaVishnoi, U., i T. G. Noll. "Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies". Advances in Radio Science 10 (18.09.2012): 207–13. http://dx.doi.org/10.5194/ars-10-207-2012.
Pełny tekst źródłaVassiliadis, N., A. Chormoviti, N. Kavvadias i S. Nikolaidis. "THE EFFECT OF DATA-REUSE TRANSFORMATIONS ON MULTIMEDIA APPLICATIONS FOR APPLICATION SPECIFIC PROCESSORS". International Journal of Computing, 1.08.2014, 102–9. http://dx.doi.org/10.47839/ijc.4.3.369.
Pełny tekst źródłaJanwa, Naresh Kumar, i Dr Manoj Kumar Jain. "Identification of Research Gaps in an Efficient Designing of Application Specific Instruction Set Processor (ASIP) for Neural Prosthetics". SSRN Electronic Journal, 2019. http://dx.doi.org/10.2139/ssrn.3349573.
Pełny tekst źródłaGerlach, Lukas, Guillermo Payá-Vayá i Holger Blume. "A Survey on Application Specific Processor Architectures for Digital Hearing Aids". Journal of Signal Processing Systems, 20.03.2021. http://dx.doi.org/10.1007/s11265-021-01648-0.
Pełny tekst źródła"Design of Energy-Efficient Application-Specific Instruction Set Processors (ASIPS) [Book Review]". IEEE Circuits and Devices Magazine 22, nr 2 (marzec 2006): 31. http://dx.doi.org/10.1109/mcd.2006.1615247.
Pełny tekst źródłaRizk, Mostafa, Amer Baghdadi, Michel Jézéquel, Youssef Atat i Yasser Mohanna. "NISC-based MIMO MMSE Detector". Journal of Circuits, Systems and Computers, 2.09.2020, 2150069. http://dx.doi.org/10.1142/s0218126621500699.
Pełny tekst źródła"Implementation of 5-Stage 32-Bit Microprocessor Based Without Interlocked Pipelining Stages". International Journal of Innovative Technology and Exploring Engineering 9, nr 1 (10.11.2019): 4557–61. http://dx.doi.org/10.35940/ijitee.a4899.119119.
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