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Artykuły w czasopismach na temat „22-nm technology node”

Autor: Grafiati

Data publikacji: 6 września 2023

Data aktualizacji: 31 lipca 2025

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1

Li, Zongru, Christopher Jarrett Elash, Chen Jin, et al. "Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies." Electronics 11, no. 11 (2022): 1757. http://dx.doi.org/10.3390/electronics11111757.

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Total ionizing dose (TID) effects from Co-60 gamma ray and heavy ion irradiation were studied at the 22-nm FD SOI technology node and compared with the testing results from the 28-nm FD SOI technology. Ring oscillators (RO) designed with inverters, NAND2, and NOR2 gates were used to observe the output frequency drift and current draw. Experimental results show a noticeable increased device current draw and decreases in RO frequencies where NOR2 ROs have the most degradation. As well, the functionality of a 256 kb SRAM block and shift-register chains were evaluated during C0-60 irradiation. SRA

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Das, Pankaj Kumar, Anurag Yadav, and Nidhi Chandra. "Analysis of Delay and Dynamic Crosstalk in Spatially Arranged Mixed CNT Bundle Interconnects at Different Technology Nodes." Key Engineering Materials 994 (November 5, 2024): 39–45. http://dx.doi.org/10.4028/p-vcvy4l.

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In the present nanoscale regime, mixed carbon nanotube bundles (MCBs) are considered to be highly promising interconnect options. This research paper introduces a spatially arranged mixed carbon nanotubes (CNTs) bundle (MCB), wherein single-walled CNTs (SWCNTs) and multi-walled CNTs (MWCNTs) occupy equal halves in the MCB. An equivalent single conductor (ESC) model for MCB is employed to analyze the interconnect performances in terms of signal transmission delay and dynamic crosstalk delay at different technology nodes (i.e., 32nm, 22nm, and 16 nm). Encouragingly, a significant reduction in si

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Xu, Peng, Yinghua Piao, Liang Ge, et al. "Investigation of Novel Junctionless MOSFETs for Technology Node Beyond 22 nm." ECS Transactions 44, no. 1 (2019): 33–39. http://dx.doi.org/10.1149/1.3694293.

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Holmes, Steven. "22-nm-node technology active-layer patterning for planar transistor devices." Journal of Micro/Nanolithography, MEMS, and MOEMS 9, no. 1 (2010): 013001. http://dx.doi.org/10.1117/1.3302125.

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Saxena, Shubhangi, and Kamsali Manjunathachari. "Novel Nanoelectronic Materials and Devices: For Future Technology Node." ECS Transactions 107, no. 1 (2022): 15701–11. http://dx.doi.org/10.1149/10701.15701ecst.

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Since the last six decades, technology node has grown smaller from micrometer to nanometer dimensions. In continuation of Moore's Law, the research is going on for device/supply voltage shrinking to go beyond 22 nm CMOS technology node. However, many physical and quantum challenges appear at a smaller scale, which causes shrinking beyond 22 nm critical and needs innovative materials and devices for scaling in the nanometer regime. Incorporating nanoengineered materials to realize research achievements has shown timely development with significant influence in electronic industries. These new m

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6

Baklanov, Mikhail R., Evgeny A. Smirnov, and Larry Zhao. "Ultra Low Dielectric Constant Materials for 22 nm Technology Node and Beyond." ECS Transactions 35, no. 4 (2019): 717–28. http://dx.doi.org/10.1149/1.3572315.

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Mitrovic, Ivona Z., and Stephen Hall. "Rare Earth Silicate Formation: A Route Towards High-k for the 22 nm Node and Beyond." Journal of Telecommunications and Information Technology, no. 4 (June 26, 2023): 560. http://dx.doi.org/10.26636/jtit.2009.4.969.

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Over the last decade there has been a significant amount of research dedicated to finding a suitable high-k/metal gate stack to replace conventional SiON/poly-Si electrodes. Materials innovations and dedicated engineering work has enabled the transition from research lab to 300 mm production a reality, thereby making high-k/metal gate technology a pathway for continued transistor scaling. In this paper, we will present current status and trends in rare earthbased materials innovations; in particular Gd-based, for the high-k/metal gate technology in the 22 nm node. Key issues and challenges for

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8

Huang, Zhengfeng, Yan Zhang, Wenhui Wu, et al. "A high-speed quadruple-node-upset-tolerant latch in 22 nm CMOS technology." Microelectronics Reliability 147 (August 2023): 115032. http://dx.doi.org/10.1016/j.microrel.2023.115032.

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9

Li, Zongru, Christopher Elash, Chen Jin, et al. "SEU performance of Schmitt-trigger-based flip-flops at the 22-nm FD SOI technology node." Microelectronics Reliability 146 (July 2023): 115033. http://dx.doi.org/10.1016/j.microrel.2023.115033.

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10

Lu, Peng, Can Yang, Yifei Li, Bo Li, and Zhengsheng Han. "Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs." Eng 2, no. 4 (2021): 620–31. http://dx.doi.org/10.3390/eng2040039.

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The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined

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11

Singh, Karan, Shruti Kalra, and Jyoti Mahur. "Evaluating NBTI and HCI effects on device reliability for high-performance applications in advanced CMOS technologies." Facta universitatis - series: Electronics and Energetics 37, no. 4 (2024): 581–97. https://doi.org/10.2298/fuee2404581s.

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The integrated circuit (IC) industry faces significant reliability challenges as MOSFET devices age, particularly at advanced nodes. Key degradation mechanisms include hot-carrier injection (HCI), negative-bias temperature instability (NBTI), and positive-bias temperature instability (PBTI), affecting both PMOS and NMOS transistors. These aging effects alter critical parameters like drain current and threshold voltage, reducing device lifespan. This paper introduces a comprehensive aging framework for MOSFETs, accounting for PBTI, NBTI, and HCI with a focus on partial recovery in AC operations

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12

Changhwan Shin, Min Hee Cho, Yasumasa Tsukamoto, et al. "Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node." IEEE Transactions on Electron Devices 57, no. 6 (2010): 1301–9. http://dx.doi.org/10.1109/ted.2010.2046070.

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13

Shin, Changhwan, Nattapol Damrongplasit, Xin Sun, Yasumasa Tsukamoto, Borivoje Nikolic, and Tsu-Jae King Liu. "Performance and Yield Benefits of Quasi-Planar Bulk CMOS Technology for 6-T SRAM at the 22-nm Node." IEEE Transactions on Electron Devices 58, no. 7 (2011): 1846–54. http://dx.doi.org/10.1109/ted.2011.2139213.

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14

Mah, Siew Kien, Pin Jern Ker, Ibrahim Ahmad, Noor Faizah Zainul Abidin, and Mansur Mohammed Ali Gamel. "A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length." Materials 14, no. 19 (2021): 5721. http://dx.doi.org/10.3390/ma14195721.

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At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards th

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15

Duari, Chusen, Shilpi Birla, and Amit Kumar Singh. "A Dual Port 8T SRAM Cell Using FinFET & CMOS Logic for Leakage Reduction and Enhanced Read & Write Stability." Journal of Integrated Circuits and Systems 15, no. 2 (2020): 1–7. http://dx.doi.org/10.29292/jics.v15i2.140.

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Static Random-Access Memory cells with ultralow leakage and superior stability are the primary choice of embedded memories in contemporary smart devices. This paper presents a novel 8T SRAM cell with reduced leakage and improved stability. The proposed SRAM cell uses a stacking effect to reduce leakage and transmission gate as an access transistor to enhance stability. The performance of the proposed 8T SRAM cell with a stacked transistor has been analyzed based on the power consumption and static noise margin (RSNM, HSNM, and WSNM). The power consumption in the case of FinFET based 8T cell is

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16

Zhou, Jing, Jishan Zhang, and Chun Zheng. "STTSRL: Design of Triple-Node Upset Self-Recovery Latch Based on Schmidt Trigger." Journal of Physics: Conference Series 2658, no. 1 (2023): 012013. http://dx.doi.org/10.1088/1742-6596/2658/1/012013.

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Abstract With the continuous progress of semiconductor technology, the size of transistors has reduced, and the sensitivity of logic circuits to soft errors caused by radiation has enhanced. The multiple-node upset caused by radiation has affected the reliability of the circuit. This paper proposes a triple-node upset (TNU) self-recovery latch based on the Schmidt trigger (ST) for radiation hardness. The feedback loop is formed by connecting C-elements (CEs) and STs. Using the error filtering mechanism of CE and the hysteresis effect of ST is to realize the reliability of STTSRL. Under the 22

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17

Mazurier, J., O. Weber, F. Andrieu, et al. "Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below." Journal of Low Power Electronics 8, no. 1 (2012): 125–32. http://dx.doi.org/10.1166/jolpe.2012.1173.

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18

Karthikeyan, A., and P. S. Mallick. "Optimization Techniques for CNT Based VLSI Interconnects — A Review." Journal of Circuits, Systems and Computers 26, no. 03 (2016): 1730002. http://dx.doi.org/10.1142/s0218126617300021.

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Interconnects plays an important role in integrated circuits. Copper is used as an interconnect material, but beyond 22[Formula: see text]nm technology node it faces many problems due to grain boundary scattering, and therefore carbon nanotubes are the most promising future interconnect materials. Various techniques and approaches such as driver sizing, repeater sizing, repeater insertion, wire sizing, wire spacing, shielding, boos table repeater were used by various researchers. Many of these techniques can be utilized for future CNT based VLSI interconnects as well. This paper presents a det

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19

Verbitskiy, V. G., S. V. Voevodin, V. V. Fedulov, G. V. Kalistyi, and D. O. Verbitskiy. "Manifestation of the channeling effect when manufacturing JFET transistors." Semiconductor Physics, Quantum Electronics and Optoelectronics 23, no. 04 (2020): 379–84. http://dx.doi.org/10.15407/spqeo23.04.379.

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TThe proposed work covers the tasks of such areas as reducing input currents and bias voltage of integrated operational amplifiers (ICs OA) manufactured according to BiFET technology, the prospect of using JFET transistors in digital circuit technology, Si CMOS technology at 22 nm node and beyond, manufacturing bipolar transistors on ultra-thin layers of the active base and emitter, increasing resistance of ICs to external influences. The main method of experimental investigation of channeling is the construction of impurity distribution profiles using SIMS. In this work to study the channelin

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20

Valasa, Sresta, Shubham Tayal, and Laxman Raju Thoutam. "Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate Dielectric for Sub 5-nm Technology Node." ECS Journal of Solid State Science and Technology 11, no. 4 (2022): 041008. http://dx.doi.org/10.1149/2162-8777/ac6627.

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This paper demonstrates the impact of temperature variation on vertically stacked junctionless nanosheet field effect transistor (JL-NSFET) concerning analog/RF performances using different gate lengths (Lg) along with high-k gate dielectrics. A comprehensive analysis of analog/RF performances like Transconductance (gm), Gate capacitance (Cgg), Gate to drain capacitance (Cgd), Output conductance (gds), Intrinsic gain (Av), Maximum oscillation frequency (fMAX), Gain Frequency Product (GFP), Cutoff frequency (fT) is carried out for the temperature range 77 K to 400 K. It is noticed that with the

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21

Kwon, Ah-Young, Ju-Yeon Jeong, Hyun Park, et al. "miR-22-3p and miR-30e-5p Are Associated with Prognosis in Cervical Squamous Cell Carcinoma." International Journal of Molecular Sciences 23, no. 10 (2022): 5623. http://dx.doi.org/10.3390/ijms23105623.

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Alteration in expression of miRNAs can cause various malignant changes and the metastatic process. Our aim was to identify the miRNAs involved in cervical squamous cell carcinoma (SqCC) and metastasis, and to test their utility as indicators of metastasis and survival. Using microarray technology, we performed miRNA expression profiling on primary cervical SqCC tissue (n = 6) compared with normal control (NC) tissue and compared SqCC that had (SqC-M; n = 3) and had not (SqC-NM; n = 3) metastasized. Four miRNAs were selected for validation by qRT-PCR on 29 SqC-NM and 27 SqC-M samples, and nine

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22

Kumar Rai, Mayank, Rajesh Khanna, and Sankar Sarkar. "Control of tube parameters on SWCNT bundle interconnect delay and power dissipation." Microelectronics International 31, no. 1 (2013): 24–31. http://dx.doi.org/10.1108/mi-03-2013-0016.

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Purpose – This paper aims to propose to study the control of tube parameters in terms of diameter, separation between adjacent tubes and length, on delay and power dissipation in single-walled carbon nanotube (SWCNT) bundle interconnect for VLSI circuits. Design/methodology/approach – The paper considers a distributed-RLC model of interconnect. A CMOS-inverter driving a distributed-RLC model of interconnect with load of 1 pF. A 0.1 GHz pulse of 2 ns rise time provides input to the CMOS-inverter. For SPICE simulation, predictive technology model (PTM) is used for the CMOS-driver. The performanc

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23

Boureau, Victor, Aurèle Durand, Patrice Gergaud, et al. "Dark-field electron holography as a recording of crystal diffraction in real space: a comparative study with high-resolution X-ray diffraction for strain analysis of MOSFETs." Journal of Applied Crystallography 53, no. 4 (2020): 885–95. http://dx.doi.org/10.1107/s1600576720006020.

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Diffraction-based techniques, with either electrons or photons, are commonly used in materials science to measure elastic strain in crystalline specimens. In this paper, the focus is on two advanced techniques capable of accessing strain information at the nanoscale: high-resolution X-ray diffraction (HRXRD) and the transmission electron microscopy technique of dark-field electron holography (DFEH). Both experimentally record an image formed by a diffracted beam: a map of the intensity in the vicinity of a Bragg reflection spot in the former, and an interference pattern in the latter. The theo

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24

Bertsias, Panagiotis, Andreas Tsimpos, and George Souliotis. "A Linear Multi-Band Voltage-Controlled Oscillator with Process Compensation for SerDes Applications." Electronics 13, no. 3 (2024): 581. http://dx.doi.org/10.3390/electronics13030581.

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A new voltage-controlled oscillator (VCO) topology for serializer–deserializer (SerDes) applications is proposed in this paper. The topology is suitable for SATA, PCI Express, and USB 3 protocols. The VCO is based on two-ring oscillator cores and operates in several frequency bands, as required by the corresponding protocol specifications, with a constant VCO gain and improved linear control over the frequency tuning. Additionally, it is supported by an automatic digital compensation mechanism for process variations. The VCO has been designed to cover the several speeds of the SATA and PCI Exp

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25

Fallnich, Daniel, Christian Lanius, Shutao Zhang, and Tobias Gemmeke. "Efficient ASIC Architecture for Low Latency Classic McEliece Decoding." IACR Transactions on Cryptographic Hardware and Embedded Systems 2024, no. 2 (2024): 403–25. http://dx.doi.org/10.46586/tches.v2024.i2.403-425.

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Post-quantum cryptography addresses the increasing threat that quantum computing poses to modern communication systems. Among the available “quantum-resistant” systems, the Classic McEliece key encapsulation mechanism (KEM) is positioned as a conservative choice with strong security guarantees. Building upon the code-based Niederreiter cryptosystem, this KEM enables high performance encapsulation and decapsulation and is thus ideally suited for applications such as the acceleration of server workloads. However, until now, no ASIC architecture is available for low latency computation of Classic

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26

Merad, Faiza, and Ahlam Guen-Bouazza. "DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (2020): 4043. http://dx.doi.org/10.11591/ijece.v10i4.pp4043-4052.

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With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport

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27

Faiza, Merad, and Guen-Bouazza Ahlam. "DC performance analysis of a 20nm gate length n-type Silicon GAA junctionless (Si JL-GAA) transistor." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (2020): 4043–52. https://doi.org/10.11591/ijece.v10i4.pp4043-4052.

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With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum tr

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28

Andrieu, François. "(Invited) Advanced Non-Volatile-Memory Embedded with CMOS: Performance and Challenges." ECS Meeting Abstracts MA2025-01, no. 36 (2025): 1729. https://doi.org/10.1149/ma2025-01361729mtgabs.

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The microcontroller (MCU) market is progressively adopting alternatives to the NOR Flash as the embedded technology solutions below the 28nm node. Foundries already propose Magnetic Random Access Memory (MRAM) or oxide-based Resistive RAM (ReRAM) that are integrated in the Back-End-Of-the-Line (BEOL) above CMOS from 22nm node down to 12nm [1], [2], [3], [4], [5]. Another company offers the Phase-Change-Memory (PCM) as the resistive element at the 28nm and 18nm [6], [7]. The physics behind the switching mechanisms of these devices is different and so their comparative advantages/drawbacks. In t

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29

Wu, Banqiu. "Next-generation lithography for 22 and 16 nm technology nodes and beyond." Science China Information Sciences 54, no. 5 (2011): 959–79. http://dx.doi.org/10.1007/s11432-011-4227-6.

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Ganesh, Chokkakula, and Fazal Noorbasha. "Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell." Active and Passive Electronic Components 2023 (June 30, 2023): 1–17. http://dx.doi.org/10.1155/2023/3371599.

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This work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. The performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully differential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). The proposed SRAM cell dominates the SSDF 9T-ST SRAM cell in terms of write ability. The built-in self-read and write assist structure of the memo

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McCants, Carl E. "The IARPA Circuit Analysis Tools Program." EDFA Technical Articles 15, no. 4 (2013): 52–54. http://dx.doi.org/10.31399/asm.edfa.2013-4.p052.

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Abstract The semiconductor industry continues to scale microelectronics in accordance with Moore’s Law, as the minimum feature size on integrated circuits has decreased from 800 nm in 1993 to 90 nm in 2003 to 22 nm today. In addition, manufacturing advances include 3-D packaging, with multiple dice stacked in various configurations, and 3-D integrated circuits that use through-silicon vias or through-oxide vias to connect the various dice layers. The Intelligence Advanced Research Projects Activity (IARPA) Circuit Analysis Tools (CAT) program is developing tools and techniques to ensure that t

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Sharma, Himanshu, and Karmjit Singh Sandha. "Impact of Intercalation Doping on the Conductivity of Multi-Layer Graphene Nanoribbon (MLGNR) in On-Chip Interconnects." Journal of Circuits, Systems and Computers 29, no. 12 (2020): 2050185. http://dx.doi.org/10.1142/s0218126620501856.

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Graphene nanoribbons are considered potentially suitable and have exhibited excellent results in on-chip interconnects. In order to evaluate the different circuit impedance parameters of multi-layer graphene nanoribbons (MLGNRs), an electrical equivalent single conductor (ESC) along with an analytical model is proposed. On the basis of an electrical model, the impact of intercalation doping on the performance of MLGNRs at 32, 22, and 16[Formula: see text]nm technology nodes is discussed in this paper. Moreover, it is also discussed that the increase in intercalation doping increases the Fermi

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Wang, Guilei, Qiang Xu, Tao Yang, et al. "Application of Atomic Layer Deposition Tungsten (ALD W) as Gate Filling Metal for 22 nm and Beyond Nodes CMOS Technology." ECS Journal of Solid State Science and Technology 3, no. 4 (2014): P82—P85. http://dx.doi.org/10.1149/2.015404jss.

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Veloso, Anabela, An De Keersgieter, Stephan Brus, Naoto Horiguchi, Philippe P. Absil, and Thomas Hoffmann. "Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications." Japanese Journal of Applied Physics 50, no. 4S (2011): 04DC16. http://dx.doi.org/10.7567/jjap.50.04dc16.

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Wang, G., Q. Xu, T. Yang, et al. "Application of Atomic Layer Deposition Tungsten (ALD W) as Gate Filling Metal for 22 nm and Beyond Nodes CMOS Technology." ECS Transactions 58, no. 10 (2013): 317–24. http://dx.doi.org/10.1149/05810.0317ecst.

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Veloso, Anabela, An De Keersgieter, Stephan Brus, Naoto Horiguchi, Philippe P. Absil, and Thomas Hoffmann. "Multi-Gate Fin Field-Effect Transistors Junctions Optimization by Conventional Ion Implantation for (Sub-)22 nm Technology Nodes Circuit Applications." Japanese Journal of Applied Physics 50, no. 4 (2011): 04DC16. http://dx.doi.org/10.1143/jjap.50.04dc16.

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Cui, Hushan, Jun Luo, Jing Xu, et al. "Investigation of TaN as the wet etch stop layer for HKMG-last integration in the 22 nm and beyond nodes CMOS technology." Vacuum 119 (September 2015): 185–88. http://dx.doi.org/10.1016/j.vacuum.2015.05.021.

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Vijay N. Patil, Yuvraj V. Parkale, Ajjay S. Gaadhe,. "Investigating the Impact of Technology Scaling on Stability Performance of Sub-threshold Static Random Access Memory Bitcell Topologies." Journal of Electrical Systems 20, no. 2s (2024): 1034–43. http://dx.doi.org/10.52783/jes.1750.

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Static random-access memory (SRAM) is increasingly being used in VLSI circuits as a result of the development of portable devices. As the demand for low-power devices increases, sub-threshold operation of SRAMs has become a popular method to reduce power consumption but at the cost of reduced stability. The work aims to propose design parameters for SRAM bit cell topologies- 6T and 10T with proper device sizing and to investigate the impact of technology scaling on its stability performance in the sub threshold region. Moreover, analysis demonstrates the impact of variations of device sizing i

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Zhao, Chun, C. Z. Zhao, M. Werner, S. Taylor, and P. R. Chalker. "Advanced CMOS Gate Stack: Present Research Progress." ISRN Nanotechnology 2012 (February 9, 2012): 1–35. http://dx.doi.org/10.5402/2012/689023.

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The decreasing sizes in complementary metal oxide semiconductor (CMOS) transistor technology require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k). When the SiO2 gate thickness is reduced below 1.4 nm, electron tunneling effects and high leakage currents occur which present serious obstacles for device reliability. In recent years, various alternative gate dielectrics have been researched. Following the introduction of HfO2 into the 45 nm process by Intel in 2007, the screening and selection of high-k gate stacks, understanding their properties, an

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Veloso, Anabela, Soon Aik Chew, Tom Schram, et al. "W versus Co–Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes." Japanese Journal of Applied Physics 52, no. 4S (2013): 04CA03. http://dx.doi.org/10.7567/jjap.52.04ca03.

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DAOUD, HOUDA, SAMIR BENSELEM, SONIA ZOUARI, and MOURAD LOULOU. "USE OF ROBUST PREDICTIVE METHOD FOR NANO-CMOS PROCESS: APPLICATION TO BASIC BLOCK ANALOG CIRCUIT DESIGN." Journal of Circuits, Systems and Computers 21, no. 07 (2012): 1250061. http://dx.doi.org/10.1142/s0218126612500612.

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This paper deals with the prediction of primary parameters of CMOS transistor for upcoming process using the robust Bisquare Weights method which is able to provide solutions to the challenges of some parameters of Nanoscale CMOS. Predicted parameters for 45 nm to 22 nm process nodes are obtained in order to solve design challenges generated by Nanoscale process. These predicted primary parameters are helpful to estimate the performance of a basic element circuit having a key role in the design of upcoming analog systems. Comparisons between predictive technology model data and predicted param

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Chiu, H. Y., Y. K. Fang, T. H. Chou, Y. T. Chiang, and C. I. Lin. "A novel STI etching technology to mitigate an inverse narrow width effect, and improve device performances for 90 nm node and beyond CMOS technology." Semiconductor Science and Technology 22, no. 10 (2007): 1157–60. http://dx.doi.org/10.1088/0268-1242/22/10/013.

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"Ultra Low Dielectric Constant Materials for 22 nm Technology Node and beyond." ECS Meeting Abstracts, 2011. http://dx.doi.org/10.1149/ma2011-01/22/1407.

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Li, Zongru, Christopher Elash, Jiesi Xing, et al. "SEU Performance of RHBD Flip-Flops Using Guard-Gates at 22-nm FDSOI Technology Node." IEEE Transactions on Nuclear Science, 2023, 1. http://dx.doi.org/10.1109/tns.2023.3284758.

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Wang, Hanbin, Jinshun Bi, Jianhui Bu, et al. "Characteristics of 22 nm UTBB-FDSOI technology with an ultra-wide temperature range." Semiconductor Science and Technology, August 4, 2022. http://dx.doi.org/10.1088/1361-6641/ac86ec.

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Abstract The performance of the ultra-thin body and buried oxide (BOX) fully-depleted silicon-on-insulator (UTBB-FDSOI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) based on a 22 nm technology node is investigated in this paper over an ultra-wide temperature range from 6 K to 550 K. The current-voltage (I-V) characteristics under wide temperature range conditions are shown, including the influence of the back-gate bias (Vbg). The important electrical parameters, such as threshold voltage (Vt), subthreshold swing (SS), ON-state current (Ion), and OFF-state current (Ioff), are ex

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Wang, Guilei, Jun Luo, Jinbiao Liu, et al. "pMOSFETs Featuring ALD W Filling Metal Using SiH4 and B2H6 Precursors in 22 nm Node CMOS Technology." Nanoscale Research Letters 12, no. 1 (2017). http://dx.doi.org/10.1186/s11671-017-2080-2.

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Sharma, Vijay Kumar. "A Survey on Low Power Design Approaches in nanoscale regime." Micro and Nanosystems 12 (June 23, 2020). http://dx.doi.org/10.2174/1876402912999200623120558.

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Background: The increased demand of battery operated portable systems boost up the field of low power VLSI design. Integrated circuits are enhancing the performance of the systems in terms of lesser area requirement, higher functionality and faster response at lower technology nodes. The applied power supply and threshold voltage of the individual device is scaled down at lower technology node. Scaling of the threshold voltage of the devices raises the issue of leakage current. Objective: Leakage current should be made recessive with the continuous scaling of technology nodes. Methods: Various

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Barik, Rasmita, Rudra Sankar Dhar, Falah Awwad, and Mousa I. Hussein. "Evolution of type-II hetero-strain cylindrical-gate-all-around nanowire FET for exploration and analysis of enriched performances." Scientific Reports 13, no. 1 (2023). http://dx.doi.org/10.1038/s41598-023-38239-x.

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AbstractThe incubation of strained nano-system in the form of tri-layered structure as nanowire channel in the cylindrical-gate-all-around (CGAA) FET at 10 nm gate length is developed for the first time to keep abreast with the proposed 3 nm technology node of IRDS 2022. The system installs Type-II hetero-strain alignment in the channel attesting itself as the fastest operating device debasing the SCEs at nano regime. The ultra-thin strained-channel comprises of two cylindrical s-Si wells encompassing s-SiGe barrier in between, which enables improvement of carrier mobility by succumbing of qua

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Tang, Chaowei, Yichen Zhang, Yanqi Zheng, and Xian Tang. "A Single‐Inductor Multiple‐Output DC‐DC Converter With 2.8 V–5 V Battery Voltage Supply for SoC Application in 22 nm CMOS Technology." International Journal of Circuit Theory and Applications, November 21, 2024. http://dx.doi.org/10.1002/cta.4374.

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ABSTRACTIn advanced processes, single‐inductor multiple‐output (SIMO) DC‐DC converters with battery voltage as input face serious overvoltage problems due to low MOSFET withstand voltage. To meet the needs of SIMO converter design in advanced processes, this paper first proposes a SIMO converter with an adaptive power supply buffer (APSB) and voltage‐limiting techniques in 22‐nm CMOS. The proposed APSB technology ensures that the driving voltage of the power stage remains unchanged under the changing power supply, solving the breakdown problem caused by low MOSFET withstand voltage and simplif

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Yin, Zihan, Md Abdullah-Al Kaiser, Lamine Ousmane Camara, et al. "IRIS: Integrated Retinal Functionality in Image Sensors." Frontiers in Neuroscience 17 (September 1, 2023). http://dx.doi.org/10.3389/fnins.2023.1241691.

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Neuromorphic image sensors draw inspiration from the biological retina to implement visual computations in electronic hardware. Gain control in phototransduction and temporal differentiation at the first retinal synapse inspired the first generation of neuromorphic sensors, but processing in downstream retinal circuits, much of which has been discovered in the past decade, has not been implemented in image sensor technology. We present a technology-circuit co-design solution that implements two motion computations—object motion sensitivity and looming detection—at the retina's output that coul

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