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Artykuły w czasopismach na temat „10T SRAM CELL”

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Data publikacji: 11 września 2023

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1

Elangovan, M., i K. Gunavathi. "High Stable and Low Power 10T CNTFET SRAM Cell". Journal of Circuits, Systems and Computers 29, nr 10 (19.12.2019): 2050158. http://dx.doi.org/10.1142/s0218126620501583.

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The ultimate aim of a memory designer is to design a memory cell which could consume low power with high data stability in the deep nanoscale range. The implementation of Very Large-Scale Integration (VLSI) circuits using MOSFETs in nanoscale range faces many issues such as increasing of leakage power and second-order effects that are easily affected by the PVT variation. Hence, it is essential to find the best alternative of MOSFET for deep submicron design. The Carbon Nanotube Field Effect Transistor (CNTFET) can eradicate all the demerits of MOSFET and be the best replacement of MOSFET for nanoscale range design. In this paper, a 10T CNTFET Static Random Access Memory (SRAM) cell is proposed. The power consumption and Static Noise Margin (SNM) are analyzed. The power consumption and stable performance of the proposed 10T CNTFET SRAM cell are compared with that of conventional 10T CNTFET SRAM cell. The power and stability analyses of the proposed 10T and conventional 10T CNTFET SRAM cells are carried out for the CNTFET parameters such as pitch and chiral vector ([Formula: see text]). The power and SNM analyses are carried out for [Formula: see text]20% variation of oxide thickness (Hox), different dielectric constant (Kox). The supply voltage varies from 0.9[Formula: see text]V to 0.6[Formula: see text]V and temperature varies from 27∘C to 125∘C. The simulation results show that the proposed 10T CNTFET SRAM cell consumes lesser power than conventional 10T CNTFET SRAM cell during the write, hold and read modes. The write, hold and read stability of the proposed 10T CNTFET SRAM cell are higher as compared with that of conventional 10T CNTFET SRAM. The conventional and proposed 10T SRAM cells are also implemented using MOSFET. The stability and power performance of proposed 10T SRAM cell is also as good as conventional 10T SRAM for MOSFET implementation. The proposed 10T SRAM cell consumes lesser power and gives higher stability than conventional 10T SRAM cell in both CNTFET and MOSFET implementation. The simulation is carried out using Stanford University 32[Formula: see text]nm CNTFET model in HSPICE simulation tool.

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Reddy Gujjula, Nagarjuna, i Rameshbabu Kellampalli. "Design and implementation of 10T-SRAM cell using Carbon Nano Tube Field Effect Transistor". International Journal of Scientific Methods in Engineering and Management 01, nr 01 (2023): 47–57. http://dx.doi.org/10.58599/ijsmem.2023.1105.

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SRAM is a key component in many VLSI circuits for efficient storage data. Various researches have been performed on implementation of SRAM using Conventional CMOS, FinFET and GNRFET technologies. But, these methodologies generating the more number of faults with high power and delay consumption, tosolve this problem proposed10T SRAM cell is implemented with the CNTFET respectively. Present research involving CNTFET SRAM deals with leakage analysis and dealt with the dual hilarity characteristics. Fault introduction and analysis of faults were limited with CMOS SRAM. The detection algorithms and circuits possess limitations in terms of detecting the current at nanoscales and restricted with CMOS SRAM. These limitations made us to pursue the research in these areas to bring novel ideas. The performance metrics evaluated and experimental analysis is made and it helps us to choose between various SRAMS. The simulation results shows that the proposed 10T SRAM consumes less delay and power compared to the 7T SRAM cell.

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Ganesh, Chokkakula, i Fazal Noorbasha. "Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell". Active and Passive Electronic Components 2023 (30.06.2023): 1–17. http://dx.doi.org/10.1155/2023/3371599.

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This work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. The performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully differential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). The proposed SRAM cell dominates the SSDF 9T-ST SRAM cell in terms of write ability. The built-in self-read and write assist structure of the memory cell also dominates the improved write ability of SSDF 9T-ST SRAM by assist circuits such as negative bit line, ultra-dynamic voltage scaling (UDVS), write assist combining negative BL, and VDD collapse. The impact of assist circuits on write performance of memory cells is observed using Monte Carlo simulation for write margin (WM) parameter. WM of SSDF 9T-ST SRAM is improved by 15% and 25% by adding UDVS assist circuit and write assist combining negative BL and VDD collapse circuit. But BSRWA SRAM cell itself can improve WM by 32% without any assist circuit. The impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for the HSNM parameter. The deviation of HSNM for 15°C to 55°C is 14%, 5%, 4%, and 1% in conventional SRAM cell, FD 10T SRAM cell, SSDF 9T SRAM cell, and proposed BSRWA 10T SRAM cell, respectively. The proposed SRAM cell is designed at a 22 nm CMOS technology node and verified in the Synopsys Custom compiler. MC simulation results are monitored on Synopsys Cosmo-scope wave viewer.

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4

Rao, M. V. Nageswara, Mamidipaka Hema, Ramakrishna Raghutu, Ramakrishna S. S. Nuvvula, Polamarasetty P. Kumar, Ilhami Colak i Baseem Khan. "Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications". Journal of Electrical and Computer Engineering 2023 (7.06.2023): 1–13. http://dx.doi.org/10.1155/2023/7069746.

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Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue. Metal oxide semiconductor field effect transistor (MOSFET) face a set of difficulties, that results in higher leakage current (Ileakage) at lower strategy collisions. Fin field effect transistor (FinFET) is a highly effective substitute to complementary metal oxide semiconductor (CMOS) under the 45 nm variant due to advanced stability. Memory cells are significant in the large-scale computation system. SRAM is the most commonly used memory type; SRAMs are thought to utilize more than 60% of the chip area. The proposed SRAM cell is developed with FinFETs at 16 nm knot. Power, delay, power delay product (PDP), Ileakage, and stationary noise margin (SNM) are compared with traditional 6T SRAM cells. The designed cell decreases leakage power, current, and read access time. While comparing 6T SRAM and earlier low power SRAM cells, FinFET-based 10T SRAM provides significant SNM with reduced access time. The proposed 10T SRAM based on FinFET provides an 80.80% PDP reduction in write mode and a 50.65% PDP reduction in read mode compared to MOSEFET models. There is an improvement of 22.20% in terms of SNM and 25.53% in terms of Ileakage.

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5

Islam, A., i M. Hasan. "Leakage Characterization of 10T SRAM Cell". IEEE Transactions on Electron Devices 59, nr 3 (marzec 2012): 631–38. http://dx.doi.org/10.1109/ted.2011.2181387.

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Chaurasia, Ranu, Brijesh Kumar, Sudhanshu Verma i Akhilesh Kumar. "Design and Performance Improvement of 10T SRAM Using Sleepy Keeper and Drain Gating Techniques". IOP Conference Series: Materials Science and Engineering 1272, nr 1 (1.12.2022): 012007. http://dx.doi.org/10.1088/1757-899x/1272/1/012007.

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This paper presents the sleepy keeper and drain gating technique to improve the performance of 10T SRAM cell. The behavior of 10T SRAM cell is evaluated using benchmarked industry standard GPDK 45nm Technology Node of the Cadence Virtuoso EDA tool. The performance is analyzed in terms of dynamic and static parameters of 10T SRAM cell and compared with 6T SRAM, where find the reduction in dynamic power and static power dissipation. Besides this, observed the reduction in leakage current using sleepy keeper and drain gating technique. The proposed modified topology applicable in single-ended write and differential read operation. The read delay product and the write delay product is decreased by 36.7 % and 67.5 %, respectively. The major goal of the suggested architecture is to provide the improved stability, reduction in delay, as well as reduction in leakage current.

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7

Liu, Changjun, Hongxia Liu i Jianye Yang. "A Novel Low-Power and Soft Error Recovery 10T SRAM Cell". Micromachines 14, nr 4 (13.04.2023): 845. http://dx.doi.org/10.3390/mi14040845.

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In SRAM cells, as the size of transistors and the distance between transistors decrease rapidly, the critical charge of the sensitive node decreases, making SRAM cells more susceptible to soft errors. If radiation particles hit the sensitive nodes of a standard 6T SRAM cell, the data stored in the cell are flipped, resulting in a single event upset. Therefore, this paper proposes a low-power SRAM cell, called PP10T, for soft error recovery. To verify the performance of PP10T, the proposed cell is simulated by the 22 nm FDSOI process, and compared with the standard 6T cell and several 10T SRAM cells, such as Quatro-10T, PS10T, NS10T, and RHBD10T. The simulation results show that all of the sensitive nodes of PP10T can recover their data, even when S0 and S1 nodes flip at the same time. PP10T is also immune to read interference, because the change of the ‘0’ storage node, directly accessed by the bit line during the read operation, does not affect other nodes. In addition, PP10T consumes very low-holding power due to the smaller leakage current of the circuit.

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8

Zhou, Hong Gang, Qiang Song, Chun Yu Peng i Shou Biao Tan. "A New 10T SRAM Cell with Improved Read/Write Margin and No Half Select Disturb for Bit-Interleaving Architecture". Applied Mechanics and Materials 263-266 (grudzień 2012): 9–14. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.9.

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A new 10T SRAM cell is proposed in this paper for simultaneously addressing the half select problem and improving the read/write stability. Without the half select condition, the proposed 10T cell allows efficient bit-interleaving to provide soft error rate protection and the dynamic power is also decreased significantly due to the reduction in the number of bitlines discharged and charged during the read and write operation. In the new 10T SRAM cell, one side of the cross-coupled inverters cuts off the pull up path or pull down path through adding two gated transistors according to the write ‘0’ or ‘1’ operation. It brings a great improvement for write stability without considering the half select disturb during the write operation. The simulation results indicate that the RSNM and WM of the proposed SRAM cell are enhanced by 130% and 58%, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology.

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9

Singh, Arjun, i Sangeeta Nakhte. "Optimized High Performance 10T SRAM Cell Characterization". International Journal of Computer Applications 134, nr 5 (15.01.2016): 29–33. http://dx.doi.org/10.5120/ijca2016907964.

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Gupta, Neha, Ambika Prasad Shah, Sajid Khan, Santosh Kumar Vishvakarma, Michael Waltl i Patrick Girard. "Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications". Electronics 10, nr 14 (17.07.2021): 1718. http://dx.doi.org/10.3390/electronics10141718.

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This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage.

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11

Shah, Ambika Prasad, i Michael Waltl. "Bias Temperature Instability Aware and Soft Error Tolerant Radiation Hardened 10T SRAM Cell". Electronics 9, nr 2 (3.02.2020): 256. http://dx.doi.org/10.3390/electronics9020256.

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In this paper, we propose an asymmetric radiation-hardened 10T (AS10T) SRAM cell and analyze the impact of bias temperature instabilities (BTI) on the single event upset of the modified structure. For this, we make use of a read decoupled circuit to improve the stability of the reading cycle, and a charge booster circuit to increase the critical charge at the sensitive node of the SRAM cell. First, we compare the noise margin of several reference cells and can clearly observe that the read static noise margin (RSNM) of AS10T is 3.25× higher than as can be achieved for the 6T SRAM cell. This improvement is due to the read decoupled path used for the read operation. To analyze the soft-error hardening, we calculate the critical charge and observe that the critical charge of the proposed AS10T cell exceed the same parameter of other SRAM cells. Further, we perform critical charge simulations and stability analysis considering BTI and observe that the AS10T SRAM cell is also less affected by BTI as the reference cells.

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12

Aparna i Ram Chandra Singh Chauhan. "Low Power PPN inverter based 10T SRAM Cell". Indian Journal of Science and Technology 14, nr 20 (25.05.2021): 1699–710. http://dx.doi.org/10.17485/ijst/v14i20.400.

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13

Sharma, Neha, i Rajeevan Chandel. "Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS". International Journal of Modeling, Simulation, and Scientific Computing 12, nr 04 (9.03.2021): 2150029. http://dx.doi.org/10.1142/s179396232150029x.

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With technology scaling, stability, power dissipation, and device variability, the impact of process, voltage and temperature (PVT) variations has become dominant for static random access memory (SRAM) analysis for productivity and failure. In this paper, ten-transistors (10T) and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors (FGMOS). Power centric parameters viz. read power, write power, hold power and delay are the performance analysis metrics. Further, the stochastic parameter variation to study the variability tolerance of the redesigned cell, PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell. Stability has been illustrated with the conventional butterfly method giving read static noise margin (RSNM) and write static noise margin (WSNM) metrics for read stability and write ability, respectively. A comparative analysis with standard six-transistor SRAM cell is carried out. HSPICE simulative analysis has been carried out for 32[Formula: see text]nm technology node. The redesigned FGMOS SRAM cells provide improved performance. Also, these are robust and reliability efficient with comparable stability.

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14

Lakshmi, T. Venkata, T. Edukondalu, S. Rahul, R. S. P. L. Suvarna i T. Rohit Chaitanya. "A Low Power 10T SRAM Cell with Extended Static Noise Margins is Used to Implement an 8 by 8 SRAM Array in 16nm CMOS". International Journal for Research in Applied Science and Engineering Technology 11, nr 4 (30.04.2023): 714–21. http://dx.doi.org/10.22214/ijraset.2023.50158.

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Abstract: Thus, it must have an ultra-low power design. Low power techniques must be used to obtain SRAM cells. First, all current high performance VLSI circuits must be designed with the 10T SRAM cell, which must also be checked for write and data storage capabilities. Large amounts of data need to be stored and accessed as quickly as possible in today's world. Static random access memory (SRAM) is a type of memory that is frequently utilised in consumer devices. The necessary circuits for designing the read operation for the 88 SRAM array are the 3 to 8 Decoder, Precharge circuit, Write Driver, and Sense amplifier. commence the application of low power approaches to the SRAM cell after that. Here, the SRAM Cell is designed using two low power methods.

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15

Zhou, Hong Gang, Shou Biao Tan, Qiang Song i Chun Yu Peng. "A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS". Applied Mechanics and Materials 373-375 (sierpień 2013): 1607–11. http://dx.doi.org/10.4028/www.scientific.net/amm.373-375.1607.

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With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

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Leavline, Epiphany Jebamalar, i Arumugam Sugantha. "Reliability improved dual driven feedback 10T SRAM bit cell". Microelectronics Reliability 139 (grudzień 2022): 114804. http://dx.doi.org/10.1016/j.microrel.2022.114804.

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Ahmad, Sayeed, Naushad Alam i Mohd Hasan. "A Robust 10T SRAM Cell with Enhanced Read Operation". International Journal of Computer Applications 129, nr 2 (17.11.2015): 7–12. http://dx.doi.org/10.5120/ijca2015906751.

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Limachia, Mitesh Jethabhai, Rajesh A. Thakker i Nikhil J. Kothari. "Characterization of a novel 10T SRAM cell with improved data stability and delay performance for 20-nm tri-gated FinFET technology". Circuit World 44, nr 4 (5.11.2018): 187–94. http://dx.doi.org/10.1108/cw-01-2018-0002.

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PurposeThis paper aims to propose a new ten-transistor (10T) SRAM bit-cell with differential read and write operations. The cell structure has read buffer on each side of the cell to improve read performance and comprises six main body transistors’ connections similar to the commercial 6T SRAM cell to improve write performance. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on a silicon-on-insulator (SOI) substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell. The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher read static noise margin (RSNM) as compared with that of 8T and 6T bit-cells, respectively, at a VDD of 0.9 V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit- cell. The overall electrical quality of the SRAM circuit with the proposed bit-cell is enhanced up to 1.673 times and 1.22 times as compared with the 8T SRAM-NEW and 6T bit-cells, respectively. Design/methodology/approachA new 10T SRAM bit-cell with differential read and write operations is proposed. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on an SOI substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell. FindingsThe proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher RSNM as compared with that of the 8T and 6T bit-cells, respectively, at a VDD of 0.9V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with the 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit-cell. Originality/valueThe proposed bit-cell is novel compared with existing bit-cells.

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Joshi, Shital, i Umar Alabawi. "Comparative Analysis of 6T, 7T, 8T, 9T, and 10T Realistic CNTFET Based SRAM". Journal of Nanotechnology 2017 (2017): 1–9. http://dx.doi.org/10.1155/2017/4575013.

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CMOS technology below 10 nm faces fundamental limits which restricts its applicability for future electronic application mainly in terms of size, power consumption, and speed. In digital electronics, memory components play a very significant role. SRAM, due to its unique ability to retain data, is one of the most popular memory elements used in most of the digital devices. With aggressive technology scaling, the design of SRAM is seriously challenged in terms of delay, noise margin, and stability. This paper compares the performance of various CNTFET based SRAM cell topologies like 6T, 7T, 8T, 9T, and 10T cell with respect to static noise margin (SNM), write margin (WM), read delay, and power consumption. To consider the nonidealities of CNTFET, variations in tube diameter and effect of metallic tubes are considered for various structures with respect to various performance metrics like SNM, WM, read delay, and power consumption.

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Mansore, S. R., i Amit Naik. "Design of a Single-Ended-Write Schmitt-Trigger Based 10T SRAM Cell". Journal of VLSI Design and Signal Processing 8, nr 3 (16.11.2022): 18–22. http://dx.doi.org/10.46610/jovdsp.2022.v08i03.003.

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Technology scaling is done in order to accommodate more and more transistors in today’s high performance VLSI circuits. These high-performance digital circuits demand large capacity of memory to accomplish faithful operations. However, at scaled technology, SRAM-cell stability is a major issue of concern. Also, increased integration density of these VLSI circuits causes increased power consumption. Leakage power in today’s VLSI circuits has become comparable to dynamic power consumption which also needs to be addressed. In this work, a Schmitt-trigger (ST) based 10T SRAM cell with single-ended-writing and differentially-read feature is proposed. The proposed cell offers enhanced stability and dissipates lower leakage power. Due to separate ports for writing and reading in the proposed cell, the conflict design requirement (which is a condition in conventional 6T cell) is eliminated. Schmitt-trigger based inverters in the proposed cell causes increased threshold voltage of the inverters resulting in enhanced cell stability during read operation. Simulation is carried out on TSPICE using a 65nm Predictive Technology Model (PTM). Results show that the proposed 10T cell provides a 1.7x larger Read static noise margin (RSNM) than the conventional 6T cell. Proposed 10T cell provides Write static noise margin (WSNM) of 155mV during write ‘0’ while 150mV during write ‘1’ operation, respectively, at 0.4V. At a supply voltage of 0.4V, the proposed 10T cell consumes 0.71x lesser static power as compared to that of a conventional 6T cell. However, proposed cell uses more transistors (10 transistors) as compared to that of the conventional 6T cell, therefore, our cell occupies large chip-area as compared to the conventional 6T cell.

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Bhanuchandar, R., B. Harikrishna i Suman Mishra. "10T Sram cell designusing single ended decoupled read bit line". Indian Journal of Public Health Research & Development 9, nr 11 (2018): 2081. http://dx.doi.org/10.5958/0976-5506.2018.01757.6.

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Shah, Ambika Prasad, Santosh Kumar Vishvakarma i Michael Hübner. "Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications". Journal of Electronic Testing 36, nr 2 (6.03.2020): 255–69. http://dx.doi.org/10.1007/s10836-020-05864-7.

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Manikandan, A. "Enhancing Energy Efficiency of Sram through Optimization of Sram Array Structures". Journal of Electronics,Computer Networking and Applied Mathematics, nr 22 (26.03.2022): 29–39. http://dx.doi.org/10.55529/jecnam.22.29.39.

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Reliability is a major concern in the microprocessor industry. In terms of power consumption, SRAM plays a key role in improving processing performance. Improving SRAM efficiency requires changes to the array structure. A general method in which the SRAM array has more rows than columns.The above techniques are proposed to improve efficiency by 10% for 8kbit and 40% for 64kbit at the same SRAM byte density and supply voltage. Implement suggested deep submicron technology for better reliability. Many proposed designs focus on low power consumption, often with reduced response times.As the technology scales, the power consumption of on-chain system devices with gate leakage, subthreshold current, and tunneling increases significantly. Small SRAM capabilities are important.This task demonstrates the potential of using larger SRAM array structures to achieve better SRAM energy efficiency, especially when the number of rows is less than the number of low-power columns. Compared to traditional 8T SRAM, the proposed 10T cell uses less power, has a different temperature and better performance.

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Yao, Ruxue, Hongliang Lv, Yuming Zhang, Xu Chen, Yutao Zhang, Xingming Liu i Geng Bai. "A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications". Micromachines 14, nr 7 (25.06.2023): 1305. http://dx.doi.org/10.3390/mi14071305.

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The static random-access memory (SRAM) cells used in the high radiation environment of aerospace have become highly vulnerable to single-event effects (SEE). Therefore, a 12T SRAM-hardened circuit (RHB-12T cell) for the soft error recovery is proposed using the radiation hardening design (RHBD) concept. To verify the performance of the RHB-12T, the proposed cell is simulated by the 28 nm CMOS process and compared with other hardened cells (Quatro-10T, WE-Quatro-12T, RHM-12T, RHD-12T, and RSP-14T). The simulation results show that the RHB-12T cell can recover not only from single-event upset caused by their sensitive nodes but also from single-event multi-node upset caused by their storage node pairs. The proposed cell exhibits 1.14×/1.23×/1.06× shorter read delay than Quatro-10T/WE-Quatro-12T/RSP-14T and 1.31×/1.11×/1.18×/1.37× shorter write delay than WE-Quatro-12T/RHM-12T/RHD-12T/RSP-14T. It also shows 1.35×/1.11×/1.04× higher read stability than Quatro-10T/RHM-12T/RHD-12T and 1.12×/1.04×/1.09× higher write ability than RHM-12T/RHD-12T/RSP-14T. All these improvements are achieved at the cost of a slightly larger area and power consumption.

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Muthusamy, Parimaladevi, i Sharmila Dhandapani. "Leakage Characterization of a Novel Transmission Gate based 10T SRAM Cell". Asian Journal of Research in Social Sciences and Humanities 6, nr 7 (2016): 844. http://dx.doi.org/10.5958/2249-7315.2016.00469.x.

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Kumar, C. I., i B. Anand. "Design of highly reliable energy‐efficient SEU tolerant 10T SRAM cell". Electronics Letters 54, nr 25 (grudzień 2018): 1423–24. http://dx.doi.org/10.1049/el.2018.7267.

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Feki, Anis, Bruno Allard, David Turgis, Jean-Christophe Lafont, Faress Tissafi Drissi, Fady Abouzeid i Sebastien Haendler. "Sub-threshold 10T SRAM bit cell with read/write XY selection". Solid-State Electronics 106 (kwiecień 2015): 1–11. http://dx.doi.org/10.1016/j.sse.2014.11.018.

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Sudha, D., Ch Santhi Rani i Sreenivasa Rao Ijjada. "SOI FinFET Based 10T SRAM Cell Design against Short Channel Effects". Acta Physica Polonica A 135, nr 4 (kwiecień 2019): 702–4. http://dx.doi.org/10.12693/aphyspola.135.702.

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Mansore, S. R., R. S. Gamad i D. K. Mishra. "A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability". Journal of Circuits, Systems and Computers 29, nr 05 (1.07.2019): 2050067. http://dx.doi.org/10.1142/s021812662050067x.

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Data stability, write ability and leakage power are major concerns in submicron static random access memory (SRAM) cell design. This paper presents an 11T SRAM cell with differential write and single-ended read. Proposed cell offers improved write ability by interrupting its ground connection during write operation. Separate read buffer provides disturb-free read operation. Characteristics are obtained from HSPICE simulation using 32[Formula: see text]nm high-performance predictive technology model. Simulation results show that the proposed cell achieves 4.5[Formula: see text] and 1.06[Formula: see text] higher read static noise margin (RSNM) as compared to conventional 6T (C6T) and PNN-based 10T cells, respectively, at 0.4[Formula: see text]V. Write static noise margin (WSNM) of the proposed design is 1.65[Formula: see text], 1.71[Formula: see text] and 1.77[Formula: see text] larger as compared to those of C6T, PPN-based 10T and PNN-based 10T cells, respectively, at 0.4V. Write “1” delay of the proposed cell is 0.108[Formula: see text] and 0.81[Formula: see text] as those of PPN10T and PNN10T cells, respectively. Proposed circuit consumes 1.40[Formula: see text] lesser read power as compared to PPN10T cell at 0.4[Formula: see text]V. Leakage power of the proposed cell is 0.35[Formula: see text] of C6T cell at 0.4[Formula: see text]V. Proposed 11T cell occupies 1.65[Formula: see text] larger area as compared to that of conventional 6T.

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Kiran, PN Vamsi, i Nikhil Saxena. "Parameter Analysis of different SRAM Cell Topologies and Design of 10T SRAM Cell at 45nm Technology with Improved Read Speed". International Journal of Hybrid Information Technology 9, nr 2 (28.02.2016): 111–22. http://dx.doi.org/10.14257/ijhit.2016.9.2.10.

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Rahman Aura, Shourin, S. M. Ishraqul Huq i Satyendra N. Biswas. "Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature". International journal of electrical and computer engineering systems 13, nr 9 (6.12.2022): 823–29. http://dx.doi.org/10.32985/ijeces.13.9.11.

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An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software is used to implement the suggested topology in the 16nm predictive technology model (PTM). Investigations into and comparisons with conventional 6T, 8T, 9T, and 10T SRAM cells have been made regarding read and write operations' delay and power consumption as well as power delay product (PDP). The simulation outcomes show that the suggested design offers the fastest read operation and PDP optimization overall. Compared to the current 6T and 9T topologies, the noise margin is also enhanced. Finally, the comparison of the figure of merit (FoM) indicates the best efficiency of the proposed design.

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Shakouri, Erfan, Behzad Ebrahimi, Nima Eslami i Mohammad Chahardori. "Single-Ended 10T SRAM Cell with High Yield and Low Standby Power". Circuits, Systems, and Signal Processing 40, nr 7 (11.01.2021): 3479–99. http://dx.doi.org/10.1007/s00034-020-01636-y.

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Dohar, Suraj Singh, Siddharth R. K., Vasantha M. H. i Nithin Kumar Y. B. "A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application". IEEE Transactions on Electron Devices 68, nr 5 (maj 2021): 2265–70. http://dx.doi.org/10.1109/ted.2021.3064899.

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Dolatshah, Amir, Erfan Abbasian, Maryam Nayeri i Sobhan Sofimowloodi. "A sub-threshold 10T FinFET SRAM cell design for low-power applications". AEU - International Journal of Electronics and Communications 157 (grudzień 2022): 154417. http://dx.doi.org/10.1016/j.aeue.2022.154417.

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MANSORE, Shivram, i Radheshyam GAMAD. "A data-aware write-assist 10T SRAM cell with bit-interleaving capability". TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 26, nr 5 (28.09.2018): 2361–73. http://dx.doi.org/10.3906/elk-1801-272.

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Jahinuzzaman, Shah M., David J. Rennie i Manoj Sachdev. "A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability". IEEE Transactions on Nuclear Science 56, nr 6 (grudzień 2009): 3768–73. http://dx.doi.org/10.1109/tns.2009.2032090.

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Abbasian, Erfan, Farzaneh Izadinasab i Morteza Gholipour. "A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins". IEEE Transactions on Circuits and Systems I: Regular Papers 69, nr 4 (kwiecień 2022): 1606–16. http://dx.doi.org/10.1109/tcsi.2021.3138849.

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Sachdeva, Ashish, i V. K. Tomar. "Design of 10T SRAM cell with improved read performance and expanded write margin". IET Circuits, Devices & Systems 15, nr 1 (15.12.2020): 42–64. http://dx.doi.org/10.1049/cds2.12006.

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Shirode, Ujwal R., Rajendra D. Kanphade i Ajjay S. Gaadhe. "Stability and Power Analysis of Schmitt Trigger Based Low Power SRAM Bit-Cell Using CMOS and CNTFET Technology at 22nm Technology Node". Key Engineering Materials 945 (19.05.2023): 41–46. http://dx.doi.org/10.4028/p-73f387.

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SRAM (Static Random Access Memory) is an essential component of memory devices such as laptops, phones, etc., which act as a semiconductor memory. The “Carbon Nanotube Field Effect Transistor (CNTFET)” is silicon associated high-stability, low-power device with excellent performance. CNTFET has been verified to be very advantageous for Very large-scale integration circuit designs in the nanoscale range because of its remarkable properties of metal oxide semiconductor field effect transistor (MOSFET). The material was brought to light because of its genuinely incredible electrochemical performance. Carbon nanotubes have unique properties such as high charge carrier mobility, high voltage, small footprint, exceptionally short and high control over pulse duration, and large current densities. In traditional MOSFET, bulk silicon is used, which has high leakage current and high field-effect; thus, CNTFET has been used as an alternative in recent years. When compared to the 10T CNTFET SRAM Bit cell is designed using HSPICE Tool in 22nm technology. Long-term stability and significant process variable changes are significant challenges with nanoscale SRAM cells.

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Krishna, R., i Punithavathi Duraiswamy. "Low leakage 10T SRAM cell with improved data stability in deep sub-micron technologies". Analog Integrated Circuits and Signal Processing 109, nr 1 (6.05.2021): 153–63. http://dx.doi.org/10.1007/s10470-021-01870-7.

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Bansal, Saloni, i V. K. Tomar. "Simulation and Analysis of P-P-N 10T SRAM cell for IoT based devices". IOP Conference Series: Materials Science and Engineering 1116, nr 1 (1.04.2021): 012111. http://dx.doi.org/10.1088/1757-899x/1116/1/012111.

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Lo, Cheng-Hung, i Shi-Yu Huang. "P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation". IEEE Journal of Solid-State Circuits 46, nr 3 (marzec 2011): 695–704. http://dx.doi.org/10.1109/jssc.2010.2102571.

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Fuketa, Hiroshi, Masanori Hashimoto, Yukio Mitsuyama i Takao Onoye. "Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM". IEEE Transactions on Nuclear Science 58, nr 4 (sierpień 2011): 2097–102. http://dx.doi.org/10.1109/tns.2011.2159993.

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Harada, R., S. Abe, H. Fuketa, T. Uemura, M. Hashimoto i Y. Watanabe. "Angular Dependency of Neutron-Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM". IEEE Transactions on Nuclear Science 59, nr 6 (grudzień 2012): 2791–95. http://dx.doi.org/10.1109/tns.2012.2224373.

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Eslami, Nima, Behzad Ebrahimi, Erfan Shakouri i Deniz Najafi. "A single-ended low leakage and low voltage 10T SRAM cell with high yield". Analog Integrated Circuits and Signal Processing 105, nr 2 (8.06.2020): 263–74. http://dx.doi.org/10.1007/s10470-020-01669-y.

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Sheu, Ming-Hwa, Chang-Ming Tsai, Ming-Yan Tsai, Shih-Chang Hsia, S. M. Salahuddin Morsalin i Jin-Fa Lin. "A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications". Sensors 21, nr 19 (2.10.2021): 6591. http://dx.doi.org/10.3390/s21196591.

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An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 μW and 3.82 μW, while the average energy consumption is only 0.39 pJ.

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SHIBATA, Nobutaro, Yoshinori GOTOH i Takako ISHIHARA. "A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications". IEICE Transactions on Electronics E99.C, nr 6 (2016): 717–26. http://dx.doi.org/10.1587/transele.e99.c.717.

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Upadhyay, Prashant, Rajib Kar, Durbadal Mandal i Sakti Prasad Ghoshal. "Characteristic analysis of a novel low power 10T SRAM cell during read and write operations". International Journal of Computer Aided Engineering and Technology 7, nr 4 (2015): 496. http://dx.doi.org/10.1504/ijcaet.2015.072603.

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Sable, Varun, i Shyam Akashe. "Noise Voltage Apportioned a New Reliability Concern in Low Power 10T SRAM Cell Using FinFET Device". Journal of Nanoelectronics and Optoelectronics 10, nr 6 (1.12.2015): 745–48. http://dx.doi.org/10.1166/jno.2015.1833.

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Sable, et al., Varun. "Static Noise Margin Enhanced in FinFET Based 10T SRAM Cell at 45 nm using EDA Tool". International Journal of Computing and Digital Systemss 5, nr 6 (1.11.2016): 451–56. http://dx.doi.org/10.12785/ijcds/050603.

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