Bibliografie tematiche / Transistors

Letteratura scientifica selezionata sul tema "Transistors"

Autore: Grafiati
Pubblicato: 4 giugno 2021
Ultima modifica: 8 giugno 2024

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Articoli di riviste sul tema "Transistors"

1

Vukic, Vladimir, e Predrag Osmokrovic. "Power lateral pnp transistor operating with high current density in irradiated voltage regulator". Nuclear Technology and Radiation Protection 28, n. 2 (2013): 146–57. http://dx.doi.org/10.2298/ntrp1302146v.

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The operation of power lateral pnp transistors in gamma radiation field was examined by detection of the minimum dropout voltage on heavily loaded low-dropout voltage regulators LM2940CT5, clearly demonstrating their low radiation hardness, with unacceptably low values of output voltage and collector-emitter voltage volatility. In conjunction with previous results on base current and forward emitter current gain of serial transistors, it was possible to determine the positive influence of high load current on a slight improvement of voltage regulator LM2940CT5 radiation hardness. The high-current flow through the wide emitter aluminum contact of the serial transistor above the isolation oxide caused intensive annealing of the positive oxide-trapped charge, leading to decrease of the lateral pnp transistor's current gain, but also a more intensive recovery of the small-signal npn transistors in the control circuit. The high current density in the base area of the lateral pnp transistor immediately below the isolation oxide decreased the concentration of negative interface traps. Consequently, the positive influence of the reduced concentration of the oxide-trapped charge on the negative feedback reaction circuit, together with the favourable effect of reduced interface traps concentration, exceeded negative influence of the annealed oxide-trapped charge on the serial pnp transistor's forward emitter current gain.
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2

Knyaginin, D. A., E. A. Kulchenkov, S. B. Rybalka e A. A. Demidov. "Study of characteristics of n-p-n type bipolar power transistor in small-sized metalpolymeric package type SOT-89". Journal of Physics: Conference Series 2086, n. 1 (1 dicembre 2021): 012057. http://dx.doi.org/10.1088/1742-6596/2086/1/012057.

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Abstract In this study the input, output and current gain characteristics of silicon n-p-n type medium power bipolar junction transistors KT242A91 made by the "GRUPPA KREMNY EL" in modern small-sized metalpolymeric package type (SOT-89) have been obtained. The SPICE model that allows simulating realistic transistor behaviour of n-p-n type transistor KT242A91 has been proposed. It is shown that established experimental characteristics for KT242A91 transistor correspond to similar transistor’s type characteristics.
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3

Horng. "Thin Film Transistor". Crystals 9, n. 8 (9 agosto 2019): 415. http://dx.doi.org/10.3390/cryst9080415.

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The special issue is "Thin Film Transistor". There are eight contributed papers. They focus on organic thin film transistors, fluorinated oligothiophenes transistors, surface treated or hydrogen effect on oxide-semiconductor-based thin film transistors, and their corresponding application in flat panel displays and optical detecting. The present special issue on “Thin Film Transistor” can be considered as a status report reviewing the progress that has been made recently on thin film transistor technology. These papers can provide the readers with more research information and corresponding application potential about Thin Film Transistors.
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4

BLALOCK, BENJAMIN J., SORIN CRISTOLOVEANU, BRIAN M. DUFRENE, F. ALLIBERT e MOHAMMAD M. MOJARRADI. "THE MULTIPLE-GATE MOS-JFET TRANSISTOR". International Journal of High Speed Electronics and Systems 12, n. 02 (giugno 2002): 511–20. http://dx.doi.org/10.1142/s0129156402001423.

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A new SOI device, the MOS-JFET, has been developed that combines two different transistors, JFET and MOSFET, superimposed in a single silicon island so that they share the same body. A unique attribute of the MOS-JFET is that it can be viewed as a four gate transistor (two side junction-based gates, the top MOS gate, and the back gate activated by SOI substrate biasing). Each of these four gates can control the conduction characteristics of the transistor. This novel transistor's multiple gate inputs give rise to exciting circuit opportunities for analog, RF, mixed-signal, and digital applications. Measured results of MOS-JFET transistors, fabricated in a conventional partially-depleted SOI technology, demonstrate that the device is fully operational. From the experiments and systematic 2-D simulations, typical regions of operation are identified. These results indicate that optimum performance is reached when the MOS and junction field-effects are combined.
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5

Arunabala, Dr C. "Design of a 4 bit Arithmetic and Logical unit with Low Power and High Speed". International Journal of Innovative Technology and Exploring Engineering 10, n. 5 (30 marzo 2021): 87–92. http://dx.doi.org/10.35940/ijitee.e8660.0310521.

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In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using the different modules. The Various modules are AND gate & OR gate designed with six transistors, While the XOR modules is designed with both eight transistors & six transistors. The six transistor XOR module gives optimized results. Another one is the four by one multiplexer designed with eight transistors implemented using Pass transistor logic (PTL) style. The full adder module is designed by using 18 transistors implemented through PTL style. Here because of PTL style the number of transistor count optimized such that the constraints get optimized results. By using the AND, OR, XOR, 4X1 MUX and full adder modules with reduced transistor count we designed the one bit ALU. With one bit ALU we designed 4 bit ALU and compared the outcomes with conventional 4 bit ALU design so that the proposed 4 bit ALU design has optimized transistor count, area, power, delay and power delay product (PDP). Simulations are verified through 130nm mentor graphics tool.
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6

Tappertzhofen, S., L. Nielen, I. Valov e R. Waser. "Memristively programmable transistors". Nanotechnology 33, n. 4 (5 novembre 2021): 045203. http://dx.doi.org/10.1088/1361-6528/ac317f.

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Abstract When designing the gate-dielectric of a floating-gate-transistor, one must make a tradeoff between the necessity of providing an ultra-small leakage current behavior for long state retention, and a moderate to high tunneling-rate for fast programming speed. Here we report on a memristively programmable transistor that overcomes this tradeoff. The operation principle is comparable to floating-gate-transistors, but the advantage of the analyzed concept is that ions instead of electrons are used for programming. Since the mass of ions is significantly larger than the effective mass of electrons, gate-dielectrics with higher leakage current levels can be used. We demonstrate the practical feasibility of the device using a proof-of-concept study based on a micrometer-sized thin-film transistor and LT-Spice simulations of 32 nm transistors. Memristively programmable transistors have the potential of high programming endurance and retention times, fast programming speeds, and high scalability.
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7

Xie, Fangqing, Maryna N. Kavalenka, Moritz Röger, Daniel Albrecht, Hendrik Hölscher, Jürgen Leuthold e Thomas Schimmel. "Copper atomic-scale transistors". Beilstein Journal of Nanotechnology 8 (1 marzo 2017): 530–38. http://dx.doi.org/10.3762/bjnano.8.57.

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We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO4 + H2SO4) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and −170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes (U bias) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1G 0 (G 0 = 2e2/h; with e being the electron charge, and h being Planck’s constant) or 2G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.
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8

Yarmukhamedov, A., A. Zhabborov e B. Turimbetov. "EXPERIMENTAL RESEARCH AND COMPUTER SIMULATION OF MULTI-CASCADE COMPOSITE TRANSISTORS FOR STABILIZING THE OPERATING MODE OF OUTPUT CASCADES OF RADIO ENGINEERING DEVICES". Technical science and innovation 2019, n. 1 (11 giugno 2019): 33–42. http://dx.doi.org/10.51346/tstu-01.18.2.-77-0009.

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Experimental results and computer simulation of multi-stage composite transistors are presented. To study the volt - ampere characteristics of multistage composite transistors, a dialogue computer simulation program, the Delphi programming environment, has been developed. It is shown that the proposed multistage composite transistors can improve manufacturability in its industrial production. It is shown that multistage homostructure transistors according to the Darlington and Shiklai circuits operate stably at collector-emitter voltages five times higher than in the case of individual transistors. The power dissipated on the collector is 3 times higher than the rated value of the maximum permissible power of the composite transistors. It is established that the efficiency of the method of stabilizing the emitter current of a three-link homostructure transistor is 7 times higher in voltage and three orders of magnitude higher in temperature compared to a conventional composite transistor. The proposed homostructure transistors are designed to operate in terminal stages of power amplifiers, radio transmitting devices, electronic equipment of industrial and automotive electronics
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9

Hebali, Mourad, Menaouer Bennaoum, Mohammed Berka, Abdelkader Baghdad Bey, Mohammed Benzohra, Djilali Chalabi e Abdelkader Saidane. "A high electrical performance of DG-MOSFET transistors in 4H-SiC and 6H-SiC 130 nm technology by BSIM3v3 model". Journal of Electrical Engineering 70, n. 2 (1 aprile 2019): 145–51. http://dx.doi.org/10.2478/jee-2019-0021.

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Abstract In this paper, the electrical performance of double gate DG-MOSFET transistors in 4H-SiC and 6H-SiC technologies have been studied by BSIM3v3 model. In which the I–V and gm–V characteristics and subthreshold operation of the DGMOSFET have been investigated for two models (series and parallel) based on equivalent electronic circuits and the results so obtained are compared with the single gate SG-MOSFET, using 130 nm technology and OrCAD PSpice software. The electrical characterization of DG-MOSFETs transistors have shown that they operate under a low voltage less than 1.2 V and low power for both models like the SG-MOSFET transistor, especially the series DG-MOSFET transistor is characterized by an ultra low power. The different transistors are characterized by an ultra low OFF leakage current of pA order, very high ON/OFF ratio of and high subthreshold slope of order 0.1 V/dec for the transistors in 6H-SiC and 4H-SiC respectively. These transistors also proved higher transconductance efficiency, especially the parallel DG-MOSFET transistor.
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Balti, M., D. Pasquet e A. Samet. "PROPAGATION EFFECTS ON Z PARAMETERS IN AN FET EQUIVALENT CIRCUIT". SYNCHROINFO JOURNAL 7, n. 5 (2021): 21–25. http://dx.doi.org/10.36724/2664-066x-2021-7-5-21-25.

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The design of microwave circuits needs a good analysis of the performances of the field-effect transistor equivalent circuit. Indeed the small signal equivalent circuit of the field-effect transistors makes it possible to easily determine their performances such as the gain and the noise figure. A field-effect transistor constitutes a propagation structure along its gate width. Telegraphists’ equations are solved for this structure. One deduces from this the effect of the propagation on the transistor Z-parameters which can be taken into account in electric simulations and which may improve the use of long transistors at lower frequencies and of short transistors at higher frequencies.
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Tesi sul tema "Transistors"

1

Pratapgarhwala, Mustansir M. "Characterization of Transistor Matching in Silicon-Germanium Heterojunction Bipolar Transistors". Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7536.

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Transistor mismatch is a crucial design issue in high precision analog circuits, and is investigated here for the first time in SiGe HBTs. The goal of this work is to study the effects of mismatch under extreme conditions including radiation, high temperature, and low temperature. One portion of this work reports collector current mismatch data as a function of emitter geometry both before and after 63 MeV proton exposure for first-generation SiGe HBTs with a peak cut-off frequency of 60 GHz. However, minimal changes in device-to-device mismatch after radiation exposure were experienced. Another part of the study involved measuring similar devices at different temperatures ranging from 298K to 377K. As a general trend, it was observed that device-to-device mismatch improved with increasing temperature.
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2

Cerutti, Robin. "Transistors à grilles multiples adaptés à la conception". Grenoble INPG, 2006. http://www.theses.fr/2006INPG0174.

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"En technologie MOS sur silicium, les transistors de type "double grille" (DG) sont considérés comme les meilleurs candidats pour les nœuds technologiques 32 et 22 nm de ITRS. Avec l'apparition de différentes architectures (FINFET, TriGate, Planar DG,. . . ) il est important de concevoir une intégration simple et compatible avec les requêtes circuit. Ce travail de thèse prend en compte les intéractions entre la conception et la technologie afin de définir des technologies tridimensionelles basées sur le module SON ("Silicon On Nothing"). De nouveaux transistors ont été inventés et développés et "ensemble des résultats morphologiques et électriques sont présentés pour confirmer le potentiel de ces composants en tant que plateforme technologique. "
Double Gate transistors are nowadays considered as the best candidate for the 32 and 22 nm technological node using silicon technologies. Within the amount of multi-gate technologies that show up ( Finfet, TriGate, Planar DG,. . ) , it is mandatory not only to be able to create transistors but also to define simple architectures that are directly compatible with circuit designs. This phd is the result of a work linking directly design and integration in order to process new tri-dimensionnal technology based on SON technique ( 'Silicon On Nothing'). New transistors have bee invented and processed and morphological and electrical results are shown in order to prove the potential of our components within the future technological platforms
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3

Lee, Yi-Che. "Development of III-nitride transistors: heterojunction bipolar transistors and field-effect transistors". Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/53472.

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The fabrication processes development for on III-nitride (III-N) heterojunction bipolar transistors (HBTs), heterojunction field-effect transistors (HFETs) and metal-insulator-semiconductor field-effect transistors (MISFETs) were performed. D.c, microwave and quasi-static I-V and C-V measurements were carried out to characterize the fabricated III-N transistors and diodes. The GaN/InGaN direct-growth HBTs (DG-HBTs) grown on free-standing GaN (FS-GaN) substrates demonstrated a high current gain (hfe) > 110, high current density (JC) > 141 kA/cm2, and high power density (Pdc) > 3 MW/cm2. The first III-N DG-HBT showing fT > 8 GHz and fmax > 1.3 GHz were also demonstrated on sapphire substrates. Recessed-gate AlGaN/AlN/GaN HFETs demonstrated Vth = 0 V with 0.17 V deviation across the sample. Baliga's figure of merit is 240 MW/cm2 was achieved. Current collapse was eliminated and the dynamic on-resistance was reduced by 67% after using a remote-oxygen-plasma treatment. Normally-off recessed-gate AlGaN/AlN/GaN MISFETs with Vth = 0.9 V were also fabricated with the remote-oxygen-plasma treatment. Low leakage current (< 1 pA/mm), high on-off ratio (> 2.2E11) are achieved. These achievements suggest that high-performance III-N transistors are very promising for high-power switching and microwave amplification. Findings concerning remaining process issues and implications for future research are also discussed.
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Ozório, Maíza da Silva. "Estudo de compósitos de tips-pentaceno para aplicações em transistores /". Presidente Prudente, 2016. http://hdl.handle.net/11449/152818.

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Orientador: Neri Alves
Banca: Edson Laureto
Banca: Carlos José Leopoldo Constantino
Resumo: Um dos atuais desafios da eletrônica orgânica é a obtenção de semicondutores com alta mobilidade que forme filmes com boa morfologia quando depositado/impresso por solução, resultando em boa uniformidade e reprodutibilidade dos dispositivos. O poli(3- hexiltiofeno) (P3HT) e o 6,13-(triisopropilsililetinil)pentaceno (TP) estão entre os semicondutores orgânicos mais utilizados. O TP tem como característica a formação de estruturas cristalinas, e desse modo, apresenta mobilidade muito maior que o P3HT, no entanto é difícil de obter filmes com boa morfologia e resultados reprodutíveis. Visando um material semicondutor que apresente mobilidade significativamente melhor que a do P3HT e uma morfologia melhor que a do TP, estudou-se compósitos a partir da mistura destes materiais (P3HT:TP) para aplicação em transistores orgânicos de efeito de campo (OFETs), utilizando óxido de alumínio anodizado (Al2O3) tratado com HMDS como dielétrico de gate. Para análise da morfologia dos compósitos semicondutores de P3HT:TP usou-se microscopia eletrônica de varredura (MEV), microscopia de força atômica (AFM) e microscopia óptica (MO). Análise óptica foi feita através de medidas de fotoluminescência (PL) e de tempo de decaimento por fotoluminescência. Espectroscopia Raman e FTIR foram utilizadas para análises estruturais. No modo transistor a caracterização foi feita através de curvas de saída e transferência. Através das caracterizações elétricas determinou-se os parâmetros do semicondutor, tais ... (Resumo completo, clicar acesso eletrônico abaixo)
Abstract: One of the current challenges of organic electronics is the development of semiconductors with high mobility to form films with good morphology when deposited/printed by solution, resulting in good uniformity and reproducibility of the devices. The poly (3-hexylthiophene) (P3HT) and 6,13-(triisopropilsililetinil)pentacene (TP) are among the most widely used organic semiconductors. The TP films are constituted by crystalline lamellar structures, and thus has greater mobility than the P3HT, however, it is difficult handling it to obtain films with good morphology and reproducible results. Targeting a semiconductor material with significantly better mobility than that of P3HT and better morphology than that of TP, we studied composites of these materials (P3HT: TP) for using in organic field effect transistors (OFETs). The transistor was prepared depositing the solution of the semiconductor composite, by spin coating, on the aluminium oxide, obtained by anodization and treated with HMDS, followed by the thermal evaporation of gold on the top, to form the drain and source electrodes. For analysis of the morphology of the composites semiconductors (P3HT: TP) was used scanning electron microscopy (SEM), atomic force microscopy (AFM) and optical microscopy (OM). Optical analysis was performed using photoluminescence (PL) measurements and decay time by photoluminescence. FTIR and Raman spectroscopy were used to structural analysis. In mode transistor, characterization was performed u... (Complete abstract click electronic access below)
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5

Ricci, Simona. "Liquid-gated transistors for biosensing applications". Doctoral thesis, Universitat Autònoma de Barcelona, 2020. http://hdl.handle.net/10803/670786.

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En aquesta tesi, hem estudiat diferents aspectes relacionats amb transistors orgànics, en particular transistors orgànics electroquímics d’efecte de camp (EGOFETs) i transistors orgànics electroquímics (OECTs). Els dispositius EGOFET es van fabricar dipositant a partir de dissolucions de semiconductors orgànics (OSC) basats en molècules conjugades barrejats amb polímers aïllants, mitjançant la tècnica de Bar-assisted meniscus shearing (BAMS). BAMS és una tècnica ràpida, de baix cost i escalable que permet la formació de pel·lícules cristal·lines i uniformes. Els EGOFET van ser estudiats pel desenvolupament d’un biosensor per a la detecció de la proteïna α-sinucleina, que és un biomarcador per a malalties neurodegeneratives, incloses les malalties de Parkinson. A més, es van utilitzar dispositius OECT també per a la detecció de α-sinucleina, per estudiar el possible ús d’aquests dispositius com a immunosensors, camp molt poc explorat en la literatura. Finalment, es va fabricar un EGOFET completament flexible basat en un nou semiconductor molecular. Per primera vegada, s’ha estudiat la resposta elèctrica sota tensió mecànica per a un EGOFET.
En esta tesis, hemos estudiado diferentes aspectos relacionados con los transistores orgánicos activados por líquido, en particular los transistores de efecto de campo orgánicos activados por electrolitos (EGOFET) y los transistores electroquímicos orgánicos (OECT). Los dispositivos EGOFET se fabricaron depositando a partir de soluciones pequeñas moléculas de semiconductores orgánicos (OSC) mezclados con polímeros aislantes, a través de la técnica de Bar-assisted meniscus shearing (BAMS). BAMS es una técnica rápida, de bajo costo y escalable que permite la formación de películas finas cristalinas y uniformes. Los EGOFET se estudiaron para el desarrollo de un biosensor para la detección de un biomarcador de enfermedades neurodegenerativas, incluidas las enfermedades de Parkinson, es decir, la alpha-sinucleína. Además, se emplearon dispositivos OECT para la biodetección de α-sinucleína, para estudiar el posible uso de estos dispositivos como inmunosensores, campo que aún está menos explorado en la literatura. Finalmente, se fabricó un EGOFET totalmente flexible basado en una pequeña molécula semiconductora mezclada con un polímero aislante y se evaluó su respuesta eléctrica bajo tensión mecánica, por primera vez, hasta donde sabemos, para dispositivos EGOFET.
In this thesis, we have studied different aspects related to liquid-gated organic transistors, in particular electrolyte-gated organic field-effect transistors (EGOFETs) and organic electrochemical transistors (OECTs). EGOFET devices were fabricated by depositing from solution small molecules organic semiconductors (OSC) blended with insulating polymers, through the bar-assisted meniscus-shearing technique (BAMS). BAMS is a rapid, low-cost and scalable technique that allows the formation of crystalline and uniform thin films. The EGOFETs were studied for the development of a biosensor for the detection of a biomarker for neurodegenerative diseases, including Parkinson’s diseases, namely α-synuclein. Further, OECT devices were employed for the biosensing of α-synuclein, to give an insight into the possible use of these devices as immunosensors, field which is still less explored in literature. Finally, an all-flexible EGOFET based on a small molecule OSC blended with an insulating polymer thin film, was fabricated and its electrical response under bending strain was evaluated, for the first time, as far as we know, for liquid-gated OFETs.
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6

Tachi, Kiichi. "Etude physique et technologique d'architectures de transistors MOS à nanofils". Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00721968.

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Il a été démontré que la structure gate-all-around en nanofils de silicium peut radicalement supprimer les effets de canaux courts. De plus, l'introduction d'espaceurs internes entre ces nanofils peut permettre de contrôler la tension de seuil, à l'aide d'une deuxième grille de contrôle. Ces technologies permettent d'obtenir une consommation électrique extrêmement faible. Dans cette thèse, pour obtenir des opérations à haute vitesse (pour augmenter le courant de drain), la technique de réduction de la résistance source/drain sera débattue. Les propriétés de transport électronique des NWs empilées verticalement seront analysées en détail. De plus, des simulations numériques sont effectuées pour examiner les facultés de contrôle de leur tension de seuil utilisant des grilles sépares.
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Acosta, Sandra Massulini. "Projeto de amplificadores operacionais CMOS utilizando transistores compostos em "sea-of-transistors"". reponame:Repositório Institucional da UFSC, 1997. https://repositorio.ufsc.br/handle/123456789/111588.

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8

Huang, Yong. "InAlGaAs/InP light emitting transistors and transistor lasers operating near 1.55 μm". Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/37298.

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Light emitting transistors (LETs) and transistor lasers (TLs) are newly-emerging optoelectronic devices capable of emitting spontaneous or stimulated light while performing transistor actions. This dissertation describes the design, growth, and performances of long wavelength LETs and TLs based on InAlGaAs/InP material system. First, the doping behaviors of zinc (Zn) and carbon (C) in InAlGaAs layers for p-type doping were investigated. Using both dopants, the N-InP/p-In0.52(AlxGa1-x)0.48As/N-In0.52Al0.48As LETs with InGaAs quantum wells (QWs) in the base demonstrate both light emission and current gains (β). The device performances of Zn- and C-doped LETs have been compared, which is explained by a charge control analysis involving the quantum capture and recombination process in the QWs. A TL based on a C-doped double heterostructure (DH-TL) with single QW was designed and fabricated. The device lases at 77 K with a threshold current density (Jth) of 2.25 kA/cm2, emission wavelength (λ) at ~1.55 µm, and β of 0.02. The strong intervalence band absorption (IVBA) is considered as the main intrinsic optical loss that prohibits the device from lasing at room temperature. Based on a threshold condition analysis taking into account the strong IVBA, it is found that room-temperature lasing of a DH-TL is achieved only when the base thickness and doping level are within a specific narrow range and improved performance is expected in a separate confinement heterostructure (SCH) TL.
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9

Xu, Ziyan Niu Guofu. "Low temperature modeling of I-V characteristics and RF small signal parameters of SiGe HBTs". Auburn, Ala., 2009. http://hdl.handle.net/10415/1925.

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10

Krumm, Jürgen. "Circuit analysis methodology for organic transistors = Methodik zur Schaltungsanalyse für organische Transistoren". kostenfrei, 2008. http://deposit.d-nb.de/cgi-bin/dokserv?idn=989071553.

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Più fonti

Libri sul tema "Transistors"

1

Welter, Michael. Transistor dictionary: Bipolar transistors. Bonn: International Thomson, 1996.

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2

Intermetall, ITT. Transistors. [Germany]: ITT Intermetall, 1996.

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3

Semiconductors, ITT. Transistors. Freiburg: ITT Semiconductors, 1987.

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4

Semiconductors, ITT. Transistors. Freiburg: ITT Semiconductors, 1992.

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5

Understanding Modern Transistors and Diodes. Cambridge: Cambridge University Press, 2010.

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6

(Firm), Knovel, a cura di. Understanding modern transistors and diodes. Cambridge: Cambridge University Press, 2010.

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Components, Philips. PowerMOS transistors. [London]: Philips Components, 1988.

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1932-, Granberg Helge, a cura di. Radio frequency transistors: Principles and practical applications. 2a ed. Boston: Newnes, 2001.

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1932-, Granberg Helge, a cura di. Radio frequency transistors: Principles and practical applications. Boston: Butterworth-Heinemann, 1993.

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Semiconductors, Philips. RF wideband transistors, video transistors and modules: Data handbook. Eindhoven: Philips Semiconductors, 1993.

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Capitoli di libri sul tema "Transistors"

1

Julien, Levisse Alexandre Sébastien, Xifan Tang e Pierre-Emmanuel Gaillardon. "Innovative Memory Architectures Using Functionality Enhanced Devices". In Emerging Computing: From Devices to Systems, 47–83. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7487-7_3.

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AbstractSince the introduction of the transistor, the semiconductor industry has always been able to propose an increasingly higher level of circuit performance while keeping cost constant by scaling the transistor’s area. This scaling process (named Moore’s law) has been followed since the 80s. However, it has been facing new constraints and challenges since 2012. Standard sub-30nm bulk CMOS technologies cannot provide sufficient performance while remaining industrially profitable. Thereby, various solutions, such as FinFETs (Auth et al. 2012) or Fully Depleted Silicon On Insulator (FDSOI) (Faynot et al. 2010) transistors have therefore been proposed. All these solutions enabled Moore’s law scaling to continue. However, when approaching sub-10nm technology nodes, the story starts again. Again, process costs and electrical issues reduce the profitability of such solutions, and new technologies such as Gate-All-Around (GAA) (Sacchetto et al. 2009) transistors are seen as future FinFET replacement candidates.
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Jain, S., M. Willander e R. Van Overstraeten. "Transistors". In Compound Semiconductors Strained Layers and Devices, 245–64. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4441-8_8.

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Razeghi, Manijeh. "Transistors". In Technology of Quantum Devices, 173–207. Boston, MA: Springer US, 2009. http://dx.doi.org/10.1007/978-1-4419-1056-1_5.

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Grundmann, Marius. "Transistors". In Graduate Texts in Physics, 713–66. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-13884-3_23.

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Brand, John R. "Transistors". In Handbook of Electronics Formulas, Symbols, and Definitions, 201–52. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4684-6491-7_2.

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Stoecker, W. F., e P. A. Stoecker. "Transistors". In Microcomputer Control of Thermal and Mechanical Systems, 45–60. Boston, MA: Springer US, 1989. http://dx.doi.org/10.1007/978-1-4684-6560-0_4.

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Powell, Richard F. "Transistors". In Testing Active and Passive Electronic Components, 103–30. Boca Raton: Routledge, 2022. http://dx.doi.org/10.1201/9780203737255-8.

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Winnacker, Albrecht. "Transistors". In The Physics Behind Semiconductor Technology, 199–220. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-10314-8_13.

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Robinson, Kevin. "Transistors". In Practical Audio Electronics, 291–314. Abingdon, Oxon : Routledge, an imprint of the Taylor & Francis Group, 2020.: Focal Press, 2020. http://dx.doi.org/10.4324/9780429343056-17.

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Verhaevert, Jo. "Transistors". In Fundamental Electrical and Electronic Principles, 184–99. 4a ed. London: Routledge, 2023. http://dx.doi.org/10.1201/9781003308294-7.

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Atti di convegni sul tema "Transistors"

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(Jane) Li, Yuanjing, John Aguada, Jiafang Lu, Jessica Yang, Roy Ng e Howard Lee Marks. "Capturing Defects in Flip-Chip CMOS Devices Using Backside EBAC Technique and SEM Microscopy". In ISTFA 2016. ASM International, 2016. http://dx.doi.org/10.31399/asm.cp.istfa2016p0118.

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Abstract This paper presents backside physical failure analysis methods for capturing anomalies and defects in advanced flip-chip packaged, bulk silicon CMOS devices. Sample preparation involves chemically removing all the silicon, including the diffusions, to expose the source/drain contact silicide and the gate of the transistors from the backside. Scanning Electron Microscopy (SEM) is used to form high resolution secondary and/or backscattered electron images of the transistor structures on and beneath the exposed surface. If no visual defects/anomalies are found at the transistor level, the Electron Beam Absorbed Current (EBAC) technique is used to isolate short/open defects in the interconnect metallization layers by landing nano-probe(s) on a transistor’s source/drain silicide or on the gate. Using the combination of secondary and backscattered electron imaging and backside EBAC thus allows defects residing in either the transistors or the metal nets to be found. Case studies from 20 nm technology node graphics processing units (GPU) are presented to demonstrate the effectiveness of this approach.
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Moiseev, Grigor. "MODELLING OF STRUCTURE BASED ON JUNCTIONLESS TRANSISTOR IN TCAD SYSTEM". In International Forum “Microelectronics – 2020”. Joung Scientists Scholarship “Microelectronics – 2020”. XIII International conference «Silicon – 2020». XII young scientists scholarship for silicon nanostructures and devices physics, material science, process and analysis. LLC MAKS Press, 2020. http://dx.doi.org/10.29003/m1662.silicon-2020/397-399.

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The purpose of this work is to synthesize a transistor with a lower leakage current. The paper describes a new type of transistors that do not contain p-n junctions - junctionless transistors. The physical principles of operation of such devices are briefly stated. On the basis of the junctionless transistor, a structure is proposed that has a lower leakage current as compared to the junctionless transistors. Numerical modeling of the proposed structure in the TCAD system is carried out. The current-voltage characteristic (CVC) of the proposed structure is calculated. It is clearly shown that the proposed structure has a lower leakage current in comparison with the leakage current of a junctionless transistor.
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Desplats, Romain, Alban Eral, Felix Beaudoin, Philippe Perdu, Alain Chion, Ketan Shah e Ted Lundquist. "IC Diagnostic with Time Resolved Photon Emission and CAD Auto-Channeling". In ISTFA 2003. ASM International, 2003. http://dx.doi.org/10.31399/asm.cp.istfa2003p0045.

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Abstract The use of time resolved photon emission (TRPE) to compare internal measurements with simulations can dramatically reduce the time required for IC analysis. During debug, this technique makes it possible to probe only transistors of interest. Two limitations must be overcome: precise location of transistor photon emission areas and distinction between photons emitted by closely spaced transistors. Otherwise results may be seriously biased. Introducing CAD auto-channeling for TRPE makes it possible to generate virtual layers where emissions are expected. As a result, transistor TRPE areas can be automatically located and emission from nearby transistors is taken into account, thus significantly reducing the duration of IC analysis.
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Anholt, Robert, R. Dettmer, C. Bozada, C. A. Cerny, G. Desalvo, J. Ebel, J. Gillespie et al. "Self Heating in III-V Transistors". In ASME 1996 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 1996. http://dx.doi.org/10.1115/imece1996-1330.

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Abstract The III-V integrated-circuits industry makes use of measured and modeled thermal impedances to model and to optimize transistor performance and to design circuits. In field effect transistors (FETs), heat is generated in a very small volume on the drain side of the gate, but models assume that it is generated in wide rectangular bars on the surface of the device. We describe electrical techniques for measuring the thermal impedances in FETs and in heterojunction bipolar transistors (HBTs). In HBTs the maximum power densities are limited by self heating, and we describe experimental studies of thermal shunt designs that reduce the thermal impedances.
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Teo, J. K. J., C. M. Chua, L. S. Koh e J. C. H. Phang. "Characterization of MOS Transistors Using Dynamic Backside Reflectance Modulation Technique". In ISTFA 2011. ASM International, 2011. http://dx.doi.org/10.31399/asm.cp.istfa2011p0170.

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Abstract The channel of metal-oxide-semiconductor (MOS) transistors at different modes of operation has been characterized using dynamic backside laser reflectance modulation technique for different NMOS and PMOS transistors with different channel lengths. The reflectance modulations contain a primary peak near the drain-end when the MOS transistor is in saturation mode. Comparison studies with a Pseudo-Two-Dimensional analytical model support the hypothesis that the observed peak corresponds to the pinch-off point.
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Ruprecht, Michael W., Shengmin Wen e Rolf-P. Vollertsen. "Sample Preparation for Vertical Transistors in DRAM". In ISTFA 2002. ASM International, 2002. http://dx.doi.org/10.31399/asm.cp.istfa2002p0307.

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Abstract This paper describes a newly developed preparation technique for vertical transistors in DRAM. The recently developed concept of DRAM cells combining a deep trench storage capacitor and a vertical access transistor promises a significant reduction in cell size. In the vertical transistor concept two gates are used to access one storage cell, which creates a challenge for the analysis of gate oxide fails. A gate oxide breakdown is determined and localized in the memory array by electrical probing and photoemission microscopy. The preparation technique combines focused ion beam (FIB) milling and selective wet chemical etching to expose both gates of the transistor simultaneously. Gate oxide pinholes are decorated by the wet etch to allow efficient inspection in a secondary electron microscope (SEM).
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Kim, Jong Eun, Jong Hak Lee, Jong Kyu Cho, Sang Hyun Ban, Chang Su Park, Nam Il Kim, Dae Woo Kim et al. "Analysis of SRAM Function Failure Due to Unformed CoSi2 Using Nanoprober and Transmission Electron Microscopy". In ISTFA 2016. ASM International, 2016. http://dx.doi.org/10.31399/asm.cp.istfa2016p0137.

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Abstract In this article, an analysis of a failure in the embedded SRAM in a CMOS Image Sensor is investigated. The failure was due to unformed CoSi2. Because unformed CoSi2 causes a varying degree of response, a nano-prober was used to find the abnormally operating transistors among a 1-bit SRAM cell consisting of six transistors(6T). After measuring and analyzing the current-voltage relationships between each transistor, the current magnitude of one pull-down transistor was found to be less than the expected range and particularly lower than that of a connected access transistor. To visualize the failure phenomenon and find the root cause of this, TEM analysis was conducted. Using the EELS (Electron Energy Loss Spectroscopy) elemental mapping, unformed CoSi2 was detected between the contact and substrate, where the contact corresponds to the VSS of the pull-down transistor. This caused an increase in the contact resistance, thus lowering the current magnitude of the abnormal transistor to a greater degree than expected.
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Plante, J., E. Allen e G. Lum. "Characterization of Californium – 252 (252Cf) as a Laboratory Source of Radiation for Testing and Analysis of Semiconductor Devices". In ISTFA 1997. ASM International, 1997. http://dx.doi.org/10.31399/asm.cp.istfa1997p0171.

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Abstract Bipolar silicon transistors were exposed to Californium (252Cf) radiation and neutron radiation obtained from nuclear facilities. The effect of the radiation on the transistors was measured by recording the transistor's electrical characteristic as a function of radiation fluence. Correlation between Californium (252Cf) -induced and neutron-induced damage and previously published data for proton-induced radiation damage was made. Finally, the effect ofthenna1 annealing on gain recovery was also investigated.
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Suwa, Tohru, e Hamid Hadim. "Multi-Packaging-Level Thermal Modeling Technique for Silicon Chip Transistors". In ASME 2009 International Mechanical Engineering Congress and Exposition. ASMEDC, 2009. http://dx.doi.org/10.1115/imece2009-11815.

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Although thermal performance is always a critical issue in electronic packaging design at every packaging level, there is a significant lack of reliable and efficient thermal modeling and analysis techniques at the silicon chip level. With millions of transistor gates acting as heat sources, accurate thermal modeling and analysis at micrometer level has not been possible using conventional techniques. For the present study, an efficient and accurate multi-level thermal modeling and analysis technique integrating transistor level into silicon chip level has been developed. The technique combines finite element analysis sub-modeling and superposition methods for more efficient modeling and simulation. Detailed temperature distribution caused by a single heat source is obtained using the finite element sub-modeling technique, while the temperature rise distribution caused by multiple heat sources is obtained using the superposition method. Using the proposed thermal modeling methodology, one case of finite element analysis with a single heat source is sufficient for modeling a silicon chip with millions of transistors acting as heat sources. When the whole package is modeled in the finite element analysis, the effect of the package is also included in the superposition results, which makes possible to model over one million transistors in a silicon chip. No present methodologies for existing silicon chip thermal modeling techniques have been able to model such a large number of transistors. The capabilities of the proposed methodology are demonstrated through a case study involving thermal modeling and analysis of a microprocessor chip.
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Campbell, Ann N., Paiboon Tangyunyong, Jeffrey R. Jessing, Charles E. Hembree, Daniel M. Fleetwood, Scot E. Swanson, Jerry M. Soden, Nicholas Antoniou, William E. Vanderlinde e Marsha T. Abramo. "Focused Ion Beam Induced Effects on MOS Transistor Parameters". In ISTFA 1999. ASM International, 1999. http://dx.doi.org/10.31399/asm.cp.istfa1999p0273.

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Abstract We report on recent studies of the effects of 50 keV focused ion beam (FIB) exposure on MOS transistors. We demonstrate that the changes in transistor parameters (such as threshold voltage, Vt) are essentially the same for exposure to a Ga+ ion beam at 30 and 50 keV under the same exposure conditions. We characterize the effects of FIB exposure on test transistors fabricated in both 0.5 μm and 0.225 μm technologies from two different vendors. We report on the effectiveness of overlying metal layers in screening MOS transistors from FIB-induced damage and examine the importance of ion dose rate and the physical dimensions of the exposed area.
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Rapporti di organizzazioni sul tema "Transistors"

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Kastner, Marc A. Single Electron Transistors. Fort Belvoir, VA: Defense Technical Information Center, ottobre 2004. http://dx.doi.org/10.21236/ada427420.

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Morkoc, Hadis. High Speed Heterostructure Transistors. Fort Belvoir, VA: Defense Technical Information Center, maggio 1995. http://dx.doi.org/10.21236/ada301117.

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Tsui, D. C. Double Superlattice GaAs IR Transistors. Fort Belvoir, VA: Defense Technical Information Center, agosto 1995. http://dx.doi.org/10.21236/ada300606.

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Xing, Huili. Ideal Channel Field Effect Transistors. Fort Belvoir, VA: Defense Technical Information Center, marzo 2010. http://dx.doi.org/10.21236/ada518256.

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Kastner, Marc A. Electron Spins in Single Electron Transistors. Fort Belvoir, VA: Defense Technical Information Center, gennaio 2009. http://dx.doi.org/10.21236/ada500634.

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Ho, P. P., e R. R. Alfano. All-optical Transistors for Ultrafast Computing. Fort Belvoir, VA: Defense Technical Information Center, settembre 2001. http://dx.doi.org/10.21236/ada402850.

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Cooper, James A., e Jr. Exploratory Development of SiC Bipolar Transistors and GaN Heterojunction Bipolar Transistors for High-Power Switching Applications. Fort Belvoir, VA: Defense Technical Information Center, marzo 2003. http://dx.doi.org/10.21236/ada413135.

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Lee, Charles Y., e Klaus Dimmler. Organic Based Flexible Transistors and Electronic Device. Fort Belvoir, VA: Defense Technical Information Center, maggio 2005. http://dx.doi.org/10.21236/ada434601.

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Lussem, Bjorn. Finding the Equilibrium of Organic Electrochemical Transistors. Kent State University, 2020. http://dx.doi.org/10.21038/blus.2020.0101.

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Dodabalapur, Ananth. High Performance Crystalline Organic Transistors and Circuit. Fort Belvoir, VA: Defense Technical Information Center, ottobre 2009. http://dx.doi.org/10.21236/ada561601.

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