Tesi sul tema "SOC.045.040.001"
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Pratomo, Istas. "Adaptive NoC for reconfigurable SoC". Phd thesis, Université Rennes 1, 2013. http://tel.archives-ouvertes.fr/tel-00980066.
Testo completoYap, S. Y. "SoC architectures for video compression". Thesis, Queen's University Belfast, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.411805.
Testo completoProcháska, František. "Implementace protokolu EtherCAT pro SoC". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-400616.
Testo completoNemoto, Rie. "Soil organic carbon (SOC) now and in the future. Effect of soil characteristics and agricultural management on SOC and model initialisation methods using recent SOC data". Phd thesis, Université Blaise Pascal - Clermont-Ferrand II, 2013. http://tel.archives-ouvertes.fr/tel-00973853.
Testo completoDing, Hao. "Key concepts for implementing SoC-Holter". Thesis, Clermont-Ferrand 2, 2011. http://www.theses.fr/2011CLF22166/document.
Testo completoAccording to the figures released by World Health Organization (WHO), cardiovascular disease is the number one cause of death in the world. In France every year more than 50,000 people die suddenly due cardiac arrhythmias. Identification of high risk sudden death patients is still a challenge. To detect cardiac arrhythmias, currently Holter is generally used to record 1~4 leads electrocardiogram (ECG) signals during 24h to 72h. However the use of Holter is limited among the population due to its form factor (not user-friendly) and cost. An integrated single chip wearable Holter named SoC-Holter that enables to record 1 to 4 leads ECG is introduced. Deployment of wireless sensor network requires each SoC-Holter with less power consumption, low-cost charging system and less die area.To minimize energy consumption and system cost, Complementary Metal Oxide Semiconductor (CMOS) technology (0.35μm) is used to prototype the first implementation of SoC-Holter. Then a novel method based on Compressed Sensing (CS) technique is introduced for solving the problems of power consumption and storage capacity of SoC-Holter. The main principle underlying this framework is to sample analog signals at sub-Nyquist rate and to classify directly compressed measurement into normal and abnormal state. Minimizing the wire connected electrodes to the platform can make the carrier more comfortable because two electrodes are attached closely on the surface of the body. Recording difference ECG is analyzed using Vectorcardiogram (VCG) theory. Experimental results show that an integrated, low cost, and user-friendly SoC-Holter is feasible. SoC-Holter consumes less than 10mW while the device is operating. It takes advantage of estimating parameters directly from compressed measurements, thereby eliminating the reconstruction stage and reducing the computational complexity on the platform. In addition, the framework provides compressed ECG signals without loss of information, reducing significantly the power consumption for message sending and memory storage space. The effect of electrode placement is evaluated by estimating QRS complex in recorded ECG signals by two adjacent electrodes. The method is based on the QRS-VCG loop alignment algorithm that estimates Least Square (LS) between an observed VCG loop and a reference loop with respect to the transformations of rotation and time synchronization. The electrode location with less sensitive to interference is investigated
Ding, Jian. "Electro-thermal models for highly integrated SoC". Thesis, Queen's University Belfast, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.486133.
Testo completoLü, Liang. "Reconfigurable SoC architectures for video motion compensation". Thesis, Queen's University Belfast, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.491876.
Testo completoBuitenga, John. "An embedded microcontroller core for SOC applications". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0032/MQ65868.pdf.
Testo completoFlynn, David Walter. "Energy-efficient SOC design technology and methodology". Thesis, Loughborough University, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.479318.
Testo completoBecker, Carlos André. "Detecção distribuída de falhas em SoC multiprocessado". Pontifícia Universidade Católica do Rio Grande do Sul, 2008. http://hdl.handle.net/10923/3207.
Testo completoIncreasing evolution in the microelectronic field within the last decades has resulted in an expansive growth of integration capacity of systems on a single chip, that has brought about the need for new technologies for analyzing the correct functioning of systems. Recently, new processor architectures have been observed moving from a single CPU (Central Processing Unit) to multiple cores (typically 2, 4 and 8 processors on a single chip). It is a scenario which evolves from mono electronic systems to multiprocessors that this paper lies, aiming at proposing an expansion of CFCSS (Control Flow Checking by Software Signatures) technique, which was developed by Edward J. McCluskey for monoprocessed systems, in a version applicable to systems with multiple processors in a single SoC (Systemon- Chip). This work is made of two parts. The first part presents taxonomy and basic concepts of fault-tolerating systems, followed by a bibliographical review of main techniques for detecting fault in software in monoprocessed systems, besides approaching reprogrammable technology evolution. The second part describes the development methodology for hardware and software platforms, as well the stages carried out and the difficulties found. In addition, it presents the CFCSS technique adapted to several processors, the communication protocol developed to carry out tests and the results obtained. This paper presents an innovative profile and is justified by the tendency of embedded systems to have, in the near future, multiple processors and applications being executed simultaneously.
A crescente evolução da área da microeletrônica nas últimas décadas acarretou um aumento expressivo da capacidade de integração de sistemas em um único chip, o que levou à necessidade de novas tecnologias para a análise do correto funcionamento dos sistemas. Observam-se, recentemente, novas arquiteturas de processadores, migrando de uma única CPU (Unidade Central de Processamento) para múltiplos núcleos (tipicamente, 2, 4 e 8 processadores em uma única pastilha). É neste cenário, que evolui de sistemas eletrônicos mono para multiprocessados, que este trabalho se insere, visando propor uma expansão da técnica CFCSS (Control Flow Checking by Software Signatures), desenvolvida por Edward J. McCluskey para sistemas monoprocessados, a uma versão aplicável a sistemas com vários processadores em um SoC (System-on-Chip). Quanto à sua estrutura, este trabalho constitui-se de duas partes. A primeira apresenta a taxonomia e os conceitos básicos de sistemas tolerantes a falhas e uma revisão bibliográfica das principais técnicas de detecção de falhas em software em sistemas monoprocessados, além de abordar a evolução da tecnologia reprogramável. A segunda parte descreve a metodologia de desenvolvimento das plataformas de hardware e de software, bem como as etapas realizadas e as dificuldades encontradas. Além disso, apresenta a técnica CFCSS adaptada a vários processadores, o protocolo de comunicação desenvolvido para a realização dos testes e os resultados obtidos. Assim, este trabalho demonstra caráter inovador e se justifica pela tendência de os sistemas embarcados possuírem, vários processadores e aplicações sendo executadas simultaneamente.
Rahkola, A. (Antti). "RF Pre-power Amplifier for LTE SoC". Master's thesis, University of Oulu, 2018. http://urn.fi/URN:NBN:fi:oulu-201806052447.
Testo completoTässä työssä tutkittiin yksipäisen komplementaarisen push-pull topologian soveltuvuutta LTE-järjestelmäpiirin RF-esitehovahvistimeksi, parantamaan tehohyötysuhdetta verrattuna nykyiseen A-luokan vahvistimeen. Push-pull -topologian soveltuvuutta tutkittiin tiukkaa lineaarisuusvaatimusta vasten. Tutkimuksen taajuusalue oli 1710–2020 MHz, ja 10 dBm siniaaltoulostuloteho oli tavoitteena. Työssä suunniteltiin ja simuloitiin yhteislähde- ja lähdeseuraaja-vahvistinversiot piirikaaviotasolla. Vahvistimet hajautettiin aktivoitaviin osioihin vahvistuksensäätöä varten ja lähdön DC-jännite asetettiin käyttäen yhteismuotoista takaisinkytkentää. Lähdeseuraaja-topologian suorituskykyyn vaikutti haitallisesti impedanssigyraatio, jota kompensoitiin laskemalla vahvistimen tuloimpedanssia. Tämä kuitenkin laski suorituskykyä merkittävästi, ja tästä syystä yhteislähde-topologian todettiin olevan parempi vaihtoehto esitehovahvistimelle. Molemmat topologiat olivat riittävän lineaarisia. Piirikaaviotason yhteislähde-version simulaatiot osoittivat hyvää tyypillistä suorituskykyä LTE-kanavilla 2 ja 23, vaikka version kehityskohteitakin tunnistettiin. Yli 40 % PAE simuloitiin 10 dBm siniaallolla, S22 ollessa parempi kuin -10 dB. Harmonisten taajuuksien tasot olivat matalat, ja 23 dBm OIP3 saavutettiin. Piirikaaviosimulaatioiden mukaan A-luokan 1.8 GHz esitehovahvistin voidaan korvata komplementaarisella yhteislähde push-pull -vahvistimella, jotta parempi tehohyötysuhde saavutettaisiin
Noun, Ziad. "Wireless Approach for SIP and SOC Testing". Thesis, Montpellier 2, 2010. http://www.theses.fr/2010MON20002.
Testo completoSo far, the test of integrated circuits and systems at wafer level relies on a physical contact between the test equipment and the devices under test on the wafer. This contact-based method is limited by several factors, such as the number of devices tested in parallel, the reduction of the size and the pitch of the bond pads, the number of touchdowns before bond pads are damaged, the cost of the test operations, among others. To solve these issues, we propose a novel test approach and architecture based on wireless communication between the tester and the devices under test (DUT). For that, a Wireless Test Control Block (WTCB) is added to every DUT on the wafer as a wireless interface between the tester and the internal test structures of the DUT. This WTCB embeds a communication protocol stack to manage the communication with the tester, and a Test Control Block to manage the test application at DUT level. Taking advantage of a wireless transmission, the tester can broadcast the test data to all DUT on the wafer in one path, maximizing the concurrent test, and reducing therefore the test time. Moreover, our WTCB architecture allows a local comparison of the DUT response with the correct response expected by the tester. By performing this comparison in the WTCB of the DUT, the tester collects from every DUT its 1-bit comparison result instead of a complete response, leading to a faster wireless test and extremely reduced test time. The WTCB has been implemented on FPGA, and a successful wireless test of a real circuit was performed, proving the efficient design of our WTCB, and highlighting the potential of our wireless test method, where it can be extended and used to perform a remote in-situ test
Buitenga, John. "An embedded microcontroller core for SOC applications". Ottawa : National Library of Canada = Bibliothèque nationale du Canada, 2002. http://www.nlc-bnc.ca/obj/s4/f2/dsk1/tape4/PQDD%5F0032/MQ65868.pdf.
Testo completoFaravelon, Aurélien. "Une démarche de conception et d'implémentation de la protection de la vie privée basée sur le contrôle d'accès appliquée aux compositions de services". Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENM036/document.
Testo completoPrivacy is hot topic. Lawyers, technicians and plain people are all concerned by this notion. Nowadays, most discussions focus on the effects of digital tools, such as social media or surveillance software. However, privacy is still ill-defined. Moreover, digital tools which endanger privacy are widely used. Should not we leave privacy aside and accept that we are, maybe more than ever, visible ?In this doctoral thesis, I address this question from a twofold viewpoint. I first inquire into the nature of our digital condition from a philosophical standpoint. I claim that digital artifacts rework the implementation of our frontiers, be them geographical or social. However, I contend that such frontiers are necessary. As I show that code defines the structure and the effects of digital tools, I point out that properties such as privacy management should be addressed right from the conception of software applications.Helping out designers to address such properties is the second issue I tackle. I focus on Service-Oriented Computing as it is a widely used paradigm. Most speci- fically, I deal with the composition of heterogenous and dynamic services. I define access control as an efficient mechanism to protect privacy and I propose a twofold generative approach to secure services compositions. The composition and its access control policies are separately defined at an abstract level. An expert is responsible for each of them. As we promote an abstract description of the application, we free the designer from technical complexity. At runtime, we propose an architecture which selects and protects the actual services by hiding them behind proxies which run the access control policy. Automated model transformations permit to generate the application from its specification. We thus bypass manual programming. We have implemented a modeling and execution environment and applied our approach to a use case in order to validate our work
Mohn, Karin [Verfasser], Alexa [Akademischer Betreuer] Franke e Anke [Gutachter] Lengning. "Dortmunder Kinder-SOC (DoK-SOC) - Validierung eines Erhebungsinstruments zum Kohärenzgefühl bei Kindern / Karin Mohn. Betreuer: Alexa Franke. Gutachter: Anke Lengning". Dortmund : Universitätsbibliothek Dortmund, 2013. http://d-nb.info/1111812039/34.
Testo completoRyu, Kyeong Keol. "Automated Bus Generation for Multi-processor SoC Design". Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5076.
Testo completoBOURDEAUDUCQ, SÉBASTIEN. "A performance-driven SoC architecture for video synthesis". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-26151.
Testo completoHuang, Tzu-Ming, e 黃子銘. "SoC Integration and Verification of a 3D Graphics SoC". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/48366849635640925032.
Testo completo國立中山大學
資訊工程學系研究所
99
While consumer demand for electronic equipment and more mature systems integration capabilities, it makes the system complexity of chip design increasing significantly. Also accompany an issue is how to efficiently and accurately verify that such a large-scale chip. In this thesis, we make 3D graphics SoC as a case study, investigate the various aspect, i.e. architecture design, system integration, verification methods and verification platform. This thesis proposes a verification methodology with unified test pattern from system modeling level to test chip level, and via increase of the abstraction level of test patterns, that avoided the way through the manual to generate the test patterns. Not only eliminate manual editing effort and reduce the possibility of error, but also allows developers to more focus on algorithm design and functional verification. In addition, through the pre-described of test scenario (Test-bench) which automated verification and comparison methodology. The efficiency of regression test will be increased. And it''s much easier to meet the constraint of time to market. However, In order to demonstrate our chip on new prototyping based board. We not only modified the channel of 3DG chip, but also develop a high-performance bus bridge to keep the efficient of exchange data between two system buses which in platform board and our SoC. And shorten the longest path of the overall system so that system clock rate could be enhanced from 82.6MHz to 120.4 MHz system clock rate.
Xue, Zhong-You, e 薛仲佑. "Security-Inside-SOC". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/98551565178351957182.
Testo completo國立交通大學
資訊科學系所
93
Along with the evolution of the communication technology, more and more data in our daily life are transferred and exchanged on internet or other communication equipments. Therefore, dealing with data on the internet becomes the problem solved in need of the computer operation system. Problems in this aspect were handled by general CPU, but nowadays the situation has changed. NPU is developed to offer high speed packet switching in order to solve the daily increasing internet flow problem. And there are more and more requirements both on information encrypted system and data transformation on internet. In this thesis, shortening the encryption time of general CPU or internet processor by foresighted secure module chip and personal trust device are proposed. Mobile communication devices such as PDA and cellular phone will be inalterable and credible by installing the PTD (Personal Trusted Device). The secure module chip is the combination of mathematical calculations such as Symmetric Key Cryptosystem, Public Key Cryptosystem, Message Digest, signature and random number generator, and is capable to offer functions like encryption, decryption, certification and signature. Further more, the safety module chip enable the PTD to perform encryption, decryption, certification and digital signature, and become a concrete device or vehicle under PKI (Public Key Infrastructure).
Wu, Chun-Ching, e 吳俊慶. "An SoC Design Framework Integrating SDRAM Controller, SIPs, and SoC Bus Analyzer". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/89euf6.
Testo completo崑山科技大學
電子工程研究所
97
The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.
Mo, Ming-Hui, e 莫明輝. "SOC Physical Design Methodology". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/50053356593607533476.
Testo completo國立成功大學
電機工程學系
89
As process technology gets into deep submicro, system-on-a-chip is an essential trend for high performance circuit design. However, physical design is going to be more complex due to larger gate count and new device property, e.g. interconnect delay and noise coupling. In this situation, the design methodology faces a new challenge to resolve the issues of SOC, e.g. timing closure and noise coupling. In this paper, we propose a SOC physical design methodology to satisfy the need for handling deep-submicro effects, and reduce the design cost due to iterative improvement by the integrated design flow.
Wang, Chih Hao, e 王志浩. "Programmable SOC Test Controller". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/99643110698865570967.
Testo completoWu, Cheng-Ta, e 吳政達. "SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/13530876256639054468.
Testo completo國立中山大學
資訊工程學系研究所
102
Nowadays, due to improvement of fabrication and IP design technology, the design complexity of System on Chip is increasing very fast. Thus we need huge amount of test pattern to verify the SOC, so how to verify the system effectively is very important. In this thesis, we take the 3DG OpenGL ES2.0 SoC which was developed by our 3DG design group as example, introducing how to build a verification platform with unified method through each level from System Modeling Level to FPGA Emulation Level. Furthermore, we use the automatic verification mechanism to improve the effectiveness of the test pattern and correctness of comparison results. And in order to improve the performance of 3DG OpenGL ES2.0 SoC, we change the original adopted AHB system bus into high performance AXI system bus. We use coreConsultant (developed by Synopsys) to generate the related IP modules, so we can save development and verification time of modules under AXI environment, and we will also introduce the flow of IP generation and synthesis in this thesis.
LIN, YU-TIEN, e 林育典. "ATE Testing for LTE SoC". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/56jukx.
Testo completo中華大學
電機工程學系碩士在職專班
101
In this thesis, the author is dedicated in the mass production testing technique of LTE wireless communication transceiver, the verification of equipment measurement, as well as the design and realization of test circuit. The test circuit contains three topics including the basic test program of the wireless communication transceiver and mix signal, measurement method, and the realization of automatic test equipment. In order to achieve fast production speed, automatic test equipment is different from other instruments. Automatic test equipment requires not only the integration of all measuring instruments but also high stability and high throughput. To obtain good matching between DUT and ATE, the property of ATE and DUT should be taken into consideration. The author utilized LTXc FUSION MX to do production measurement.
Lin, Hsuan-Yeh, e 林宣燁. "Alert Integration in Mobile SOC". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/61614935611540197717.
Testo completo國立成功大學
電腦與通信工程研究所
95
With the universal of Internet, the use of network has become a part of our daily life, for example: e-government, commodity trade, banking service…etc. There are a lot of dangers of attacks, malice behaviors in network when we deal with all of those above. Besides, we put more and more privacy data in network, hence, the risks that hosts suffered attack that made our data lose or be stolen will be more and more serious. There have been already a lot of security software to prevent from all of those above (for example: IDS, IPS, anti-virus software, firewalls…etc), but there are still a lot of problem in these security software, such as “High False Positive Rate”, large amounts of non-relevant events. The bigger the organization is, the more the security software is, as a result, its deploy must be more complex, and the amount of these alerts they generated must be surplus. Because the alert is different as the different equipment, to manage those things is very difficult. Security Operation Center (SOC) that provides assistance in automation to security policy management, security organizational management and security operation management at the upper level could solve all of those problems above. We present one hierarchical-SOC using mobile agent, hierarchy will expand the range of the network that one manages, and the distributed system could reduce the probability of being attacked. Under the part—“alert correlation”, there are two components. We enumerate several real attacks to test and verify our architecture on Taiwan Network Security Testbed, and the result match what we expected.
Shieh, Wen-Bing, e 謝文彬. "PCI INTERFACE SOC PLATFORM DESIGN". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/78664174601320754488.
Testo completo大同大學
電機工程學系(所)
93
ABSTRACT This thesis proposed a general purpose and basic platform for the SoC investigation in the future which includes three major interconnect bus : the PCI bus, the Wishbone bus and the Microprocessor bus, also consists some other common buffers such as dual port memory, FIFOs and some state machines, and UART port as a LCD interface. The PCI Local bus is a high performance 32-bit or 64-bit bus with multiplexed address and data lines, which is intended for use as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in-cards and processor/memory systems. The WISHBONE System-on-Chip (SoC) interconnection Architecture for Portable IP Cores is a flexible design methodology for use with semiconductor IP cores. Its purpose is to foster design reuse by alleviating System-on-Chip integration problems. Wishbone is public domain standard. The microprocessor is selected with a very popular and common used 8051 micro-controller. It’s a 8-bit microprocessor IP, and integrate with sequencer, instructions set, internal memory, general purpose registers etc. Combine the IPs above and some dual port memory, FIFOs and UART, it becomes a general purpose SoC platform and easy to extend with PCI or Wishbone bus which are popular in the current SoC design field.
Chia-Chi, Wu, e 吳家頎. "Fingerprint Verification System on SoC". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/01575945899273418139.
Testo completo國立臺灣科技大學
資訊工程系
91
Fingerprint verification is one of the most reliable personal identification methods. However, manual fingerprint verification is so tedious, time-consuming, and inefficiency. Therefore, an automatic fingerprint identification system (AFIS) is widely needed. It plays a very important role in forensic and civilian applications such as criminal identification, access control. This paper describes the design and implementation of a fingerprint verification system on System on a Chip (SoC). Our fingerprint verification system operates in four stages: fingerprint acquisition, image pre-processing, minutiae extraction and minutiae matching. Image pre-processing consists of segmentation, smoothing and thinning, which help for extract significant minutiae more accurately. The minutiae extraction algorithm is implemented for extracting features from an input fingerprint image captured with the sensor. For our fingerprint verification system in this paper, we use ridge endings and ridge bifurcations for fingerprint matching. We use Altera’s Nios SoC development kit to implement fingerprint verification system. We build hardware core, including CPU and peripheral modules, with System On a Programmable Chip (SOPC) Builder, and implement fingerprint verification algorithm using C programming language. We also use Programming Language Interface (PLI) routine to proceed hardware & software co-verification in high-level language. To make sure the system be correct, we use UART which communicates PC with the Nios development board to verify the accuracy of SoC.
Tsai, Cheng-Hsiung, e 蔡正雄. "Clock Distribution Network for SoC". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/44764184048825295093.
Testo completo國立成功大學
電機工程學系碩博士班
91
As fabrication technology gets into deep sub-micro era, System-on-a-Chip (SoC) becomes an essential trend for high performance circuit design. However, physical design automation is getting more and more complex due to parasitic effects, e.g. wire delay, etc. In this situation, the design methodology has to face a new challenge to resolve the issues of SoC. In this paper, we propose a new flexible clock distribution network design to solve the clock skew problem and support “plug-and-play” in SoC integrated overall SoC operation. Reduce the design cost due to iterative improvement in the integrated design.
Tsai, Chun-Tien, e 蔡均典. "Software Development Process in SOC". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/77499475805972753387.
Testo completo國立交通大學
電資學院學程碩士班
91
IC design in Taiwan has been developing for more that 10 years, which evolved from pure hardware IC in the early years into SOC with complex software inside. But most of the IC design developers tend to focus more on the hardware without being aware of the importance of designing hardware and software at the same time, which leads to many cases of IC design failures. Being aware of the seriousness of the problem, the objective of this dissertation is to build a system of software developing process for SOC. The software in SOC not only firmware which stored in ROM, but also including application program、device driver、real-time operation system which use the IC. It’s content is huge and complex. Since the quality of the software design has a close link with the success and failure of the product, thus designing IC software requires strict rules and processes, in order to make the designed IC products marketable quickly. This research analysis the issues for present development process of IC hardware and software. The basic problem is that design process lack of exact review process and explicit software design process. To define the job, task, output documents and review key-point for software design process based on planning, analysis, design, implementation and integration phases. Because of the complex design change for IC product, also define software configuration management process. The design process of this paper had implemented in the IC design company, and obtained some benefits, including shorten IC product development schedule, find out design defects early and increase software reuse.
Tseng, Shih-Fang, e 曾世芳. "ATE Testing for Bluetooth SOC". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/35946138762922790849.
Testo completo中華大學
電機工程學系碩士班
102
This thesis is focus for Bluetooth SOC(System On the Chip) mass-production testing method. The contents include the introduction of ATE (Automatic Testing Equipment) structure, a real case on implementation of the Bluetooth testing board and development of the testing program on the ATE. The proposed ATE testing structure is different from general purpose RF SOC testing instrument. It should design a test board which can test all items on the same board and finish all testing items at one time. The testing time is also requested to be as shorter as possible, normally it is around several seconds. The used ATE is SG9000 G4 tester.
Chuang, Feng-yuan, e 莊豐源. "IP Verification for SoC Applications". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/23749158186952577695.
Testo completo義守大學
電子工程學系碩士班
93
In this thesis﹐we proposed a methodology of wrapper design﹒In our example﹐We use LCD driver IP and viterbi decoder IP to integrate in SOC as AMBA slave components﹒ Conventional LCD driver can not drive different size panel﹒In the thesis﹐we proposed LCD driver in different size panel﹒With different parameters﹐our LCD IP builder can automatically generate a synthesizable Verilog code and embedded in AUK system provided by CIC﹒We also take systolic-traced-back viterbi decoder embedded in AUK for example﹒ Although those IPs are not relative﹐we can prove different IP integrate in SOC is not a dream﹒In the future﹐IP integration will be a key in SOC design﹒
Yang, Fu-Ching, e 楊馥璟. "SYS-SIP SoC Development Infrastructure". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/56020307841939926155.
Testo completo國立中山大學
資訊工程學系研究所
98
System-on-a-Chip (SoC) is a trend to achieve high performance, low cost, and low power in modern electronic devices. As the demand of functionality and performance increase, more IPs (Intellectual Property) are integrated into a modern SoC. Developing such a complex SoC is challenging since the SoC has limited observability; modern SoCs usually leave limited spared I/O pins for debugging purpose due to cost consideration, making it hard to analyze the internal activities via the limited I/O pins. This hampers the SoC development. To ease the difficulty, we have implemented the SYS-SIP (National Sun Yat-Sen university''s SoC Infrastructure IP''s) to enable the SoC development in terms of verification, debugging, monitor ing, and performance tuning. The SYS-SIP consists of five members: Processor External Interrupt Verification Module (PEVM), ICE, processor tracer, bus tracer, and protocol checker. Each of them serves specific purposes in verification, debugging, monitoring, and performance tuning. The SYS-SIP can be applied at diffierent design stages: RTL, FPGA, and chip level. The results show that SYS-SIP eases the SoC development and shortens the time-to-market significantly.
"HPI Future SOC Lab : proceedings 2011". Universität Potsdam, 2013. http://opus.kobv.de/ubp/volltexte/2013/6400/.
Testo completoIn Kooperation mit Partnern aus der Industrie etabliert das Hasso-Plattner-Institut (HPI) ein “HPI Future SOC Lab”, das eine komplette Infrastruktur von hochkomplexen on-demand Systemen auf neuester, am Markt noch nicht verfügbarer, massiv paralleler (multi-/many-core) Hardware mit enormen Hauptspeicherkapazitäten und dafür konzipierte Software bereitstellt. Das HPI Future SOC Lab verfügt über prototypische 4- und 8-way Intel 64-Bit Serversysteme von Fujitsu und Hewlett-Packard mit 32- bzw. 64-Cores und 1 - 2 TB Hauptspeicher. Es kommen weiterhin hochperformante Speichersysteme von EMC². SAP stellt ihre neueste Business by Design (ByD) Software zur Verfügung und auch komplexe reale Unternehmensdaten stehen zur Verfügung, auf die für Forschungszwecke zugegriffen werden kann. Interessierte Wissenschaftler aus universitären und außeruniversitären Forschungsinstitutionen können im HPI Future SOC Lab zukünftige hoch-komplexe IT-Systeme untersuchen, neue Ideen / Datenstrukturen / Algorithmen entwickeln und bis hin zur praktischen Erprobung verfolgen. In diesem Technischen Bericht werden die Ergebnisse der Forschungsprojekte des Jahres 2011 vorgestellt. Ausgewählte Projekte stellten ihre Ergebnisse am 15. Juni 2011 und 26. Oktober 2011 im Rahmen der Future SOC Lab Tag Veranstaltungen vor.
Lin, Sung-chun, e 林松君. "Configurable Interface Design Methodology in SoC". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/04755385088402490622.
Testo completo國立雲林科技大學
電子與資訊工程研究所碩士班
92
A typical co-design environment has a number of component processes assigned for execution either in hardware or in software. These components have an obvious interaction requirement in order to meet the system functionality. Reuse of Intellectual Property (IP) is crucial in SoC design. The discrepancies in interface logic and communication/bus protocols among IPs, however, remain as the main obstacle in system integration. In this paper, we examine the interface logic generation problem and propose a novel scheme to automate the process. The scheme consists of an automatic communication / bus protocol translation and a template based interface logic / bus wrapper generation. Real case test bench, e.g. AHB in AMBA v.s. BVCI in VCI was applied to verify the correctness and the efficiency of the generated interface. The design is also implemented in FPGA and incurred interface circuitry overhead is small.
Wu, Ming-Ju, e 吳明儒. "SoC architecture for Reconfigurable Video Coding". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/05828404675162256782.
Testo completo國立交通大學
資訊科學與工程研究所
97
This thesis presents a flexible SoC architecture for video decoding applications. Comparing to traditional hardwired codec approaches, the proposed framework is more flexible in the sense that it allows runtime construction of a new data path using available hardware and software functional units. This framework was original developed to support MPEG reconfigurable video coding (RVC) framework. However, there are some weaknesses in previous proposal. First, the original proposal was implemented on an SoC emulation platform (ARM Integrator) that has high software-hardware communication overhead. Secondly, the original design has not been verified with inter-frame decoding behavior. In this thesis, the complete system behavior of an H.264/AVC baseline video decoder has been implemented on a single-chip hardware-software co-implementation platform targeted for a large capacity FPGA. In particular, we have verified that the system behaviors of managing inter-frame can also be supported by the proposed flexible SoC architecture for RVC. In summary, the proposed SoC architecture is promising for practical applications.
"HPI future SOC lab : proceedings 2013". Universität Potsdam, 2014. http://opus.kobv.de/ubp/volltexte/2014/6819/.
Testo completoDas Future SOC Lab am HPI ist eine Kooperation des Hasso-Plattner-Instituts mit verschiedenen Industriepartnern. Seine Aufgabe ist die Ermöglichung und Förderung des Austausches zwischen Forschungsgemeinschaft und Industrie. Am Lab wird interessierten Wissenschaftlern eine Infrastruktur von neuester Hard- und Software kostenfrei für Forschungszwecke zur Verfügung gestellt. Dazu zählen teilweise noch nicht am Markt verfügbare Technologien, die im normalen Hochschulbereich in der Regel nicht zu finanzieren wären, bspw. Server mit bis zu 64 Cores und 2 TB Hauptspeicher. Diese Angebote richten sich insbesondere an Wissenschaftler in den Gebieten Informatik und Wirtschaftsinformatik. Einige der Schwerpunkte sind Cloud Computing, Parallelisierung und In-Memory Technologien. In diesem Technischen Bericht werden die Ergebnisse der Forschungsprojekte des Jahres 2013 vorgestellt. Ausgewählte Projekte stellten ihre Ergebnisse am 10. April 2013 und 24. September 2013 im Rahmen der Future SOC Lab Tag Veranstaltungen vor.
"HPI future SOC lab : proceedings 2012". Universität Potsdam, 2013. http://opus.kobv.de/ubp/volltexte/2014/6899/.
Testo completoDas Future SOC Lab am HPI ist eine Kooperation des Hasso-Plattner-Instituts mit verschiedenen Industriepartnern. Seine Aufgabe ist die Ermöglichung und Förderung des Austausches zwischen Forschungsgemeinschaft und Industrie. Am Lab wird interessierten Wissenschaftlern eine Infrastruktur von neuester Hard- und Software kostenfrei für Forschungszwecke zur Verfügung gestellt. Dazu zählen teilweise noch nicht am Markt verfügbare Technologien, die im normalen Hochschulbereich in der Regel nicht zu finanzieren wären, bspw. Server mit bis zu 64 Cores und 2 TB Hauptspeicher. Diese Angebote richten sich insbesondere an Wissenschaftler in den Gebieten Informatik und Wirtschaftsinformatik. Einige der Schwerpunkte sind Cloud Computing, Parallelisierung und In-Memory Technologien. In diesem Technischen Bericht werden die Ergebnisse der Forschungsprojekte des Jahres 2012 vorgestellt. Ausgewählte Projekte stellten ihre Ergebnisse am 18. April 2012 und 14. November 2012 im Rahmen der Future SOC Lab Tag Veranstaltungen vor.
Lin, Cheng-Ju, e 林政儒. "Java SoC Self-booting Circuit Design". Thesis, 2016. http://ndltd.ncl.edu.tw/handle/7w3gh4.
Testo completo國立交通大學
資訊科學與工程研究所
105
In this thesis, we present a self-booting JRE on a full-system hardwired Java processor, JAIP. With a new implemented simple boot logic, the JAIP JRE itself now can boot up intanstly. And to support dynamic class loading during runtime, we implement a class loader written in Java which is responsible for loading other Java applications. We also add a circuit "JAIPPointer" and its Java APIs to provide a memory-mapped interface, so user can easily integrate other I/O devices by adding their own Java software driver.
Chih-HsuanWang e 王志亘. "PIPELINED SCHEDULE SYNTHESIS FOR MULTIMEDIA SOC". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/06820709950847495741.
Testo completo國立臺灣大學
資訊工程學研究所
95
Multimedia SoCs have property of throughput constraints. The throughput of multimedia application is the rate at which it processes input data, and this is usually the prime constraint on most multimedia applications. In order to meet the throughput constraints of these system with low cost, it is necessary to construct more efficient implementation with pipelined design. Idea of pipelined design is to divide applications into several concurrently executing stages, thus increasing its data rate. In this thesis, we presented a solution to pipelined schedule synthesis for multimedia SoCs such that pipeline buffer is minimized under throughput constraints. We proposed a three-step exploration methodology to obtain pipelined schedule with minimal pipeline buffer which meets the given throughput constraints. Performance evaluation results prove the proposed three-step exploration methodology could reduce the run-time overhead and derive a near-optimal solution.
Wu, Chang-Yu, e 吳長餘. "Mask Programmable Cell Array for SoC". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/06626813757987320540.
Testo completo國立中正大學
電機工程研究所
92
In this paper, we propose a new Structured ASIC design technique, called Mask Programmable Cell Array, or MPCA. We investigate not only a more competitive architecture but also a new type of cell design-Transistors Array. In order to decide upon the most competitive cell design from various explorations of T.A. type cell, we have made our experiment flow and evaluation metrics. Besides, for area optimization , we also propose a approach known as Regional Packing to save the wasted transistors on MPCA.
Liu, Chih-Feng, e 劉智. "Programmable Arbiter Design for SoC Application". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/31696095258507373392.
Testo completo義守大學
電子工程學系
92
In order to obtain high bandwidth utilization and low latency for on-chip bus communication, a hybrid arbitration algorithm and a programmable arbiter architecture are described in this thesis. The hybrid arbitration algorithm contains static fixed priority algorithm in conjunction with dynamic algorithm to gain low latency in system performance is explained. The implementation of a programmable arbiter to increase the bandwidth utilization is proposed. The analysis of various combinations of the arbitration algorithms indicates a better performance can be achieved as compared with the traditional arbitration assignment scheme. The simulation results of the programmable arbiter are shown on Altera Max Plus II design environment and implementation in Altera EPF10K100ARC240-1 FPGA and verified in ARM AMBA University Kit (AUK) environment.
Lin, Yi-Horng, e 林宜宏. "DSP Library for SOC ADC Testing". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/42418502369248602108.
Testo completo國立中央大學
電機工程研究所
89
In this thesis, we will construct an IEEE 1057-1994 mixed signal circuit test library for mixed-signal SOC; use Histogram and FFT to measure. We will use Texas Instruments (TI) TMS 320c62x EVM, DSP processor and evaluation kit as the test vehicle. The test results include the relation between SNR and Number of Sampling, sampling frequency number of sampling cycle, ENOB.
Lee, Hong Tsan, e 李宏燦. "Strategic Planning of Taiwan’s SOC Industry". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/23739788147997227477.
Testo completo國立交通大學
科技管理所
91
This thesis reports on strategic planning of Taiwan’s SOC Industry. Specific emphasis is placed on strategic planning, industrial portfolio analysis, industrial innovation requirements (IIRs) , and innovation policies. Attempts are made to provide policy recommendations to Taiwan IC firms positioning at different strategic segments. The portfolio model entails a 2-dimensional analysis. The strategic grouping and the value chain represent, respectively, as the vertical and horizontal variables. Results show that the majority of the Taiwanese firms in the industry are positioned as the manufacturers or OEM suppliers, and only a few IC design houses possess leveragable in the IP Mall, or Star IP Providers. This research suggests that future prospects should focus on cultivating core technology, and developing in the design of innovative products. The analysis of the Innovation Requirements and innovation policy reveals that the most critical categories of the policy instruments are “Scientific and Technical Development”, “Education”, and “Political”. Specifically, the government should dictate and subsidize the development of the star IPs, establish an educational framework for the SOC industry to enhance relevant expertise and human resources, maintain technological superiority to that of China, and reinforce intellectual property protection and patent laws. In addition, government should encourage diffusion and exchange of IPs among SOC firms to assist applications and sharing of IPs. A result in accordance with the expert interviews held during the course of this research.
Huang, Wen-Chieh, e 黃文傑. "SoC Software/Hardwaer Co-Verification System". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/54208219538964776072.
Testo completo國立交通大學
電資學院學程碩士班
91
As the semiconductor technology has made great progress, System-on-Chip has become the kernel technologies for integrating computer, consumer, and communication. In other words, a system, which consists of CPU cores like RISC or DSP, memories and other IPs, can be easily embedded into a chip. But to make a SoC product successful, we must take care of the integration of hardware and software. Thus, it is quite critical that to build the HW/SW co-verification environment with EDA tools, HW/SW co-design tools, and other technologies to shorten the development cycle of SoC. The HW/SW co-verification system utilizes EDA tools, the features of various IPs, and hardware simulators, combining with the fast software simulation to improve the testing flow and the simulation performance. In this thesis, we build a HW/SW co-verification environment with innovative methods to speed the HW/SW simulation performance by integrating Faraday's DSP core [8], the test benches, and the Seamless [1] tool. In our HW/SW co-verification system, the software part will execute the computation-intensive part and the hardware will be responsible for the signal communication. The experiments have shown that our HW/SW co-verification system have a great improvement in the simulation performance over 70 times than the traditional method.
Alves, Pedro Miguel Ferreira. "Programmable flexible cores for SoC applications". Master's thesis, 2009. http://hdl.handle.net/10216/58731.
Testo completoWu, Kuang-Li, e 吳光立. "Bus Wrapper Design Methodology in SoC". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/3hw4hz.
Testo completo國立成功大學
電機工程學系碩博士班
90
Bus Wrapper Design Methodology in SoC Kuang-Li Wu* Jer-Min Jou** Department of Electrical Engineering National Cheng Kung University Tainan, Taiwan, Republic of China ABSTRACT In this paper, the bus wrapper design methodology is proposed in order to generate and synthesize communication interfaces in a system design context. This methodology will be used in bus-based SoCs for IP integration. To verify the practicability, we use this methodology to implementation the on-chip bus wrapper and on-board bus wrapper based on Virtual Component Interface (VCI)-compliant IPs by three cases, which are the AHB master wrapper, the AHB slave wrapper, and the PCI bus target wrapper. We can use the AHB wrapper to integrate the VCI-compliant IP into ARM development system, or use PCI wrapper to integrate the VCI-compliant IP into personal computer system. In the bus wrapper design we use the buffer to store the address and data temporary instant of FIFO, so we only use a small amount the area of bus wrapper. At the performance of the bus wrapper, we use the Mealy Machine Design method, so the input and output of the interface can be pass through the wrapper as soon as possible. It will not cause the communication latency between the interface of the bus and standard interface. *The author ** The advisor
Liu, Wei-ming, e 柳偉明. "SoC Design for Secured Network Transmission". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/z67vb6.
Testo completo逢甲大學
資訊工程所
91
As the time goes on, network has already become a part of our daily life. The life with information technology almost combines with network, and network can provide various kinds of information and service. As the network provides more and more services, there will be more and more data transmitted through the network. Of course, there must be some important information transmitted through the network. If we do not have good security system, and someone may steal those important data, easily. So, more and more people pay attention to the area, network security, and a lot of new secrecy mechanism have been developed. In this thesis, I want to develop a SOC platform with data encryption/decryption mechanism. With this system design, it can provide higher data transmission security for the systems that must transmit information through the network. In this thesis, I will use a system development tool that provided by ALTERA to development system, and DES circuit design to construct the main point of this thesis. I will propose three different architectures to implement this data encryption/decryption system. In the architecture1, the data encryption/decryption operation is done by software. In architecture2, we use custom instruction to add additional hardware instruction to speedup the DES data encryption/decryption operation. The last architecture will use a customized hardware to accomplish the data encryption/decryption operation. In this architecture, the first work is designing a DES circuit, and then is writing a wrapper to connect the DES circuit and the original architecture. These three different architectures let us know the performance, and the hardware space of each kind of architecture.
Chih-HsuanWang. "PIPELINED SCHEDULE SYNTHESIS FOR MULTIMEDIA SOC". 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1408200721483300.
Testo completoLin, Jia-hung, e 林嘉宏. "Software-Based Methodology for SOC Testing". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/17721851300565266404.
Testo completo義守大學
資訊工程學系碩士班
93
System on chip (SOC) is a trend of the electronic products in recent years. It integrates several silicon intelligent properties (SIPs) into a single chip with more compact size. However, it is difficult to test these deeply embedded SIPs because of the poor controllability and observability in SOC environment. In order to study SOC testing, we integrate M6800 CPU, peripheral interface adapter, and asynchronous communications interface adapter into a SOC verification platform based on WISHBONE system bus in this thesis. The software-based methodology based on instruction set architecture and register transfer level is proposed to generate test patterns for at-speed SOC testing. In this methodology, the M6800 CPU tests itself by executing a set of instructions and analyzes responses. After the M6800 CPU has been self-tested, it can be used for testing other SIPs cores. The benefits of the software-based self-test method contain at-speed testing, no performance decreasing, no area overhead, and decrease power consumption.
Lin, Shih-Jhe, e 林士哲. "SOC BUS System Design and Implementation". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/13191941163047862606.
Testo completo義守大學
電子工程學系碩士班
96
This paper is aimed at single layer and multi layer soc bus system that include visual master module、dynamic reconfigurable arbiter、output control module and system control method. The visual master module simulate master’s behavior and signal in soc when transform data. Combine four popular algorithm to dynamic reconfigurable arbiter including fix-priority 、 round-robin(RR) 、 first come first service(FCFS) 、 random access(RA) algorithm. The dynamic reconfigurable is more flexibility and variable than just only one algorithm arbiter. The output control method means a output decode module. The purpose soc bus system use handshake control method. The master which is using bus will make control signal to busy and disable arbiter until master finish its work. The purpose bus system use hardware distribution language (verilog) to complete and use C language to simulate the effect that use different traffic pattern. We also use primepower to analysis power consumption in different traffic pattern. Finally use design vision support by CIC to transform bus system to gate-level netlist and use SOC encounter to transform bus system from gate-level netlist to layout.