Letteratura scientifica selezionata sul tema "Programmable Dataplanes"

Traffic monitoring is a critical component of self-driving networks. In particular, any system that seeks to automatically manage a network's operation must first be equipped with insights about traffic currently flowing through the network. Typically, dedicated traffic monitoring systems deliver such insights in the form of traffic features to high-level human or automated decision makers. Inspired by the exciting capabilities of programmable dataplanes and the persistent challenges of network management, the research community has focused on improving the flexibility and efficiency of traffic monitoring systems for a variety of management tasks. However, a significant gap remains between the traffic monitoring requirements of practical, deployable self-driving networks and the capabilities of current state-of-the-art systems. This short paper provides a brief background of traffic monitoring systems, discusses how their claims and limitations relate to requirements of self-driving networks, and proposes several open challenges as exciting starting points for future research. Addressing these challenges requires large-scale efforts in traffic monitoring techniques and selfdriving network design, as well as enhanced dialog between researchers in both domains.

AbstractThe rapid growth of new applications with high resource demands leads to the need for more computing power. Datacenter servers may not be the most efficient way to run the necessary software. The introduction of programmable dataplanes opens up the possibility to run software directly in the dataplane with lower latency and higher energy efficiency than general purpose servers. Thus, the concept of in‐network computing is introduced. This paper addresses the challenges associated with executing software resorting to programmable networking devices while presenting a high level conceptual architecture including three layers of computing. The paper ends by taking the evaluated challenges into consideration and proposing future research directions for the evolution of the in‐network computing technology.

L'arrivée des switchs ASIC programmables de nouvelle génération a obligé la communauté des réseaux à repenser le fonctionnement des réseaux. La possibilité de reconfigurer la logique de traitement des paquets par le plan de transfert de données sans modifier le matériel sous-jacent et l'introduction de primitives de mémoire à état ont suscité un regain d'intérêt pour les cas d'utilisation qui peuvent être déchargés sur le plan de transfert de données. Cependant, les commutateurs programmables ne prennent toujours pas en charge les calculs à valeur réelle et obligent à utiliser des serveurs externes ou des boîtes intermédiaires pour effectuer ces opérations. Afin de réaliser pleinement la capacité de traitement en réseau, nos contributions proposent d'ajouter le support des opérations à valeur réelle sur le commutateur. Pour ce faire, nous utilisons des tables de consultation mathématiques pour construire des pipelines permettant de calculer des fonctions à valeur réelle. Nous commençons par développer des procédures pour calculer des opérations élémentaires de base, en gardant à l'esprit les contraintes et les limitations d'un commutateur programmable. Ces procédures sont une combinaison de tables de consultation et d'opérations natives fournies par le commutateur. Une fonction donnée est décomposée en une représentation qui met en évidence les opérations élémentaires qui la composent et les dépendances entre elles. Un pipeline est construit en assemblant les procédures prédéfinies pour chaque opération élémentaire sur la base de la représentation. Plusieurs techniques de réduction et d'optimisation des ressources sont également appliquées avant que le pipeline final ne soit déployé sur le commutateur. Ce processus a été étendu à plusieurs commutateurs du réseau, ce qui permet de déployer des fonctions encore plus importantes sur le commutateur. Le projet a été le premier à étudier un cadre générique pour la construction de pipelines pour le calcul à valeur réelle. Notre prototype sur le commutateur Barefoot Tofino montre l'efficacité de notre système pour le calcul en réseau de différents types d'opérations et son application pour les modèles de régression logistique en réseau utilisés pour les problèmes de classification et les fonctions de séries chronologiques comme ARIMA pour la détection des DDoS. Nos évaluations montrent qu'il est possible d'atteindre une erreur relative inférieure à 5%, voire 1%, avec une faible quantité de ressources, ce qui en fait une approche viable pour prendre en charge des fonctions et des algorithmes complexes
The advent of new-generation programmable switch ASICs have compelled the network community to rethink operation of networks. The ability to reconfigure the dataplane packet processing logic without changing the underlying hardware and the introduction of stateful memory primitives have resulted in a surge in interest and use-cases that can be offloaded onto the dataplane. However, programmable switches still do not support real-value computation and forcing the use of external servers or middle boxes to perform these operations. To fully realize the capability of in-network processing, our contributions propose to add support for real-value operations on the switch. This is achieved by leveraging mathematical lookup tables for building pipelines to compute a real-value functions. We start by developing procedures for computing basic elementary operations, keeping in mind the constraints and limitations of a programmable switch. These procedures are a combination of lookup tables and native operations provided by the switch. A given function is decomposed into a representation that highlights its constituent elementary operations and the dependencies between them. A pipeline is constructed by stitching together the predefined procedures for each elementary operation based on the representation. Several, reduction and resource optimization techniques are also applied before the final pipeline is deployed onto the switch. This process was further expanded to scale multiple switches in the network, enabling even larger functions to be deployed on the switch. The project was the first to investigate a generic framework for building pipelines for real-value computation. Our prototype on Barefoot Tofino switch shows the efficiency of our system for in-network computation of different types of operations and its application for in-network logistic regression models used for classification problems and time series functions like ARIMA for DDoS detection. Our evaluations show that reaching a relative error below 5% or even 1% is possible with a low amount of resources making it a viable approach to support complex functions and algorithms

Real-time sensitive network applications are emerging and require ultra-low latency to reach the desired QoS. A main issue that contributes to latency is excessive buffering at intermediate switches and routers. Existing queuing strategies that aim to reduce buffering induced latency typically apply a single queue AQM that does not support service differentiation and treats all packets equally. The recently proposed per packet value framework utilizes a packet value marker and a packet value aware AQM to solve this issue by supporting service differentiation in a single queue and introducing more advanced policies for resource sharing. However, the per packet value framework is implemented and tested in a software environment with no possibility to study the performance on hardware equipment.  This thesis utilizes P4 to design and implement a packet value marker on dataplane programmable devices. The marker should be capable of supporting multiple resource sharing policies, following resource sharing policies accurately, and not being the bottleneck in the network. A target-independent packet value marker is designed and modified with target-dependent P4 constructs to fit the implementation requirements of a Tofino switch and a Netronome smart NIC. An accurate Tofino implementation using this approach is difficult to achieve because of a complicated random number generation process and resource limitation. Evaluation using a testbed with a Netronome marker shows that the marker achieves desired functionality with accurate packet value distribution for throughputs larger than 5000 Kbps. However, the challenge of concurrent packet processing combined with a smart NIC that does not have powerful packet processing cores results in the marker having lower throughput and higher latency than expected. The evaluation also shows that resource limitation in terms of available memory and the number of supported policies affects the maximum number of supported users. We also ported a version to a switching ASIC with limited functionality due to the restrictions of the hardware platform. Our evaluation also provides insights into how such a marking scheme performs on different hardware targets and the limitation imposed by such target specific architecture.
Realtids Känsliga nätverksapplikationer utvecklas och kräver ultra-låg latens för att nå önskad QoS. Befintliga lösningar på detta problem tillämpar AQM på en enda kö och stöder inte tjänst differentiering och behandlar alla paket lika. Det nyligen föreslagna ramverket per packet value löser problemet genom att stödja tjänst differentiering på en kö och införa mer avancerade policyer för resursdelning. Ramverket per packet value implementeras och testas i en mjukvaru miljö utan möjlighet att studera prestanda på hårdvaru utrustning. Denna avhandling använder P4 för att designa och implementera en packet value marker på dataplan programmerbara enheter. Markern bör kunna stödja flera resursdelning principer, följa resursdelning principer exakt, och inte vara bottlenecken i nätverket. En hårdvaruoberoende packet value marker är designad och modifierad med hårdvaruberoende P4-konstruktioner för att passa implementerings kraven för en Tofino switch och en Netronome smart NIC. Slumpmässig talgenerering och resursbegränsning resulterar i en misslyckad implementering av en marker på Tofino med detta tillvägagångssätt. Utvärdering med hjälp av en testbädd med en Netronome marker visar att ett enanvändarscenario och en slumptalsgenerator orsakar lägre genomströmning och högre latens jämfört med forwarding. Resultaten visar att denna metod för Markern är felaktig när man tillämpar policyer vid lägre genomströmningar. Utvärderingen visar också att det maximala antalet användare begränsas av minnet och antalet policyer som stöds. Denna utvärdering ger inblick i hur en sådan marking algoritm är designad och svårigheterna med implementering för olika hårdvara.

New trends in dataplane programmability inside Software Defined Networking (SDN) paradigm are in an effort to bring multi-platform support with a high-level definition of the dataplane pipeline functions. The MultiArchitecture Compiler System for Abstract Dataplanes (MACSAD) can integrate the Protocol-Independent Packet Processors (P4) domain-specific language and the OpenDataPlane Project (ODP) APIs, to define a programmable dataplane across multiple targets in a unified compiler system. In this paper, we present and evaluate the IPv4/IPv6 Longest Prefix Match (LPM) support in MACSAD. We develop a new ODP Helper library implementing the IPv6 lookup mechanism based on the current IPv4 solution and evaluate its performance and scalability for diverse workloads and target platform configurations.

We propose a programmable optical fabric design for Data Center networks that extends SDN to L1. We present experiments on our HPC/ML testbed leveraging the programmable network to automatically failover from hardware or software failures.

A short-term solution for the depletion of Internet Protocol (IP) addresses and scaling problems in network routing is the reuse of IP address by placing Network Address Translators (NAT) at the borders of stub domains. In this article, we propose an implementation of NAT using Programming ProtocolIndependent Packet Processors (P4) language, taking advantage of its features such as target-agnostic dataplane programmability. Through the MACSAD framework, we generate a software switch that achieves high performance with the support of different hardware (H/W) and Software (S/W) platforms. The main contributions of this paper relate to the performance evaluation results of the NAT implementation using P4 language with MACSAD compiler.