Articoli di riviste: "Planar device architecture"

1

Misra, Ravi K., Sigalit Aharon, Michael Layani, Shlomo Magdassi e Lioz Etgar. "A mesoporous–planar hybrid architecture of methylammonium lead iodide perovskite based solar cells". Journal of Materials Chemistry A 4, n. 37 (2016): 14423–29. http://dx.doi.org/10.1039/c6ta06960f.

Testo completo

Abstract (sommario):

We report a hybrid mesoporous–planar architecture of methylammonium lead iodide perovskite based solar cells, to combine the benefits of both the mesoporous and planar architectures in a single device.

Gli stili APA, Harvard, Vancouver, ISO e altri

2

Bhattacharya, Debajit, e Niraj K. Jha. "FinFETs: From Devices to Architectures". Advances in Electronics 2014 (7 settembre 2014): 1–21. http://dx.doi.org/10.1155/2014/365689.

Testo completo

Abstract (sommario):

Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable continued transistor scaling. In this paper, we review research on FinFETs from the bottommost device level to the topmost architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.

Gli stili APA, Harvard, Vancouver, ISO e altri

3

Tarabella, Giuseppe, Simone Luigi Marasso, Valentina Bertana, Davide Vurro, Pasquale D’Angelo, Salvatore Iannotta e Matteo Cocuzza. "Multifunctional Operation of an Organic Device with Three-Dimensional Architecture". Materials 12, n. 8 (25 aprile 2019): 1357. http://dx.doi.org/10.3390/ma12081357.

Testo completo

Abstract (sommario):

This work aims to show the feasibility of an innovative approach for the manufacturing of organic-based devices with a true three-dimensional and customizable structure that is made possible by plastic templates, fabricated by additive manufacturing methods, and coated by conducting organic thin films. Specifically, a three-dimensional prototype based on a polyamide structure covered by poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS) using the dip-coating technique demonstrated a multifunctional character. The prototype is indeed able to operate both as a three-terminal device showing the typical response of organic electrochemical transistors (OECTs), with a higher amplification performance with respect to planar (2D) all-PEDOT:PSS OECTs, and as a two-terminal device able to efficiently implement a resistive sensing of water vaporization and perspiration, showing performances at least comparable to that of state-of-art resistive humidity sensors based on pristine PEDOT:PSS. To our knowledge, this is the first reported proof-of-concept of a true 3D structured OECT, obtained by exploiting a Selective laser sintering approach that, though simple in terms of 3D layout, paves the way for the integration of sensors based on OECTs into three-dimensional objects in various application areas.

Gli stili APA, Harvard, Vancouver, ISO e altri

4

Ravariu, Cristian, Elena Manea e Catalin Parvulescu. "An Appropriate Diffusion Process Changes the Behaviour of a Planar-Nothing on Insulator Device". Defect and Diffusion Forum 399 (febbraio 2020): 115–22. http://dx.doi.org/10.4028/www.scientific.net/ddf.399.115.

Testo completo

Abstract (sommario):

The paper investigates the tunneling currents through the gate terminals of the last MOSFET production and proposes a related structure, noted as p-NOI (planar-Nothing On Insulator) device. In fact, the p-NOI structure can arise as parasitic device in any MOSFET having a gate insulator sub-10nm thickness or can be separately produced to offer a tunneling device. The work principle of a p-NOI structure consists in the Fowler-Nordheim's tunneling of a thin insulator. Its architecture is derived from the Nothing On Insulator (NOI) device, using oxide instead vacuum. Essentially, the p-NOI current follows a metal-insulator-semiconductor trajectory. A critical issue is the field effect of a transistor that must be fulfilled by independent p-NOI device. In this purpose, a diffusion process seems to be the key. A planar p-NOI device with top three terminals is proposed. A diffusion process along to the Si-surface is a key technological step that offers distinct current traces.

Gli stili APA, Harvard, Vancouver, ISO e altri

5

Malosio, Matteo, Francesco Corbetta, Francisco Ramìrez Reyes, Hermes Giberti, Giovanni Legnani e Lorenzo Molinari Tosatti. "On a Two-DoF Parallel and Orthogonal Variable-Stiffness Actuator: An Innovative Kinematic Architecture". Robotics 8, n. 2 (27 maggio 2019): 39. http://dx.doi.org/10.3390/robotics8020039.

Testo completo

Abstract (sommario):

Variable-Stiffness Actuators are continuously increasing in importance due to their characteristics that can be beneficial in various applications. It is undisputed that several one-degree-of-freedom (DoF) solutions have been developed thus far. The aim of this work is to introduce an original two-DoF planar variable-stiffness mechanism, characterized by an orthogonal arrangement of the actuation units to favor the isotropy. This device combines the concepts forming the basis of a one-DoF agonist-antagonist variable-stiffness mechanism and the rigid planar parallel and orthogonal kinematic one. In this paper, the kinematics and the operation principles are set out in detail, together with the analysis of the mechanism stiffness.

Gli stili APA, Harvard, Vancouver, ISO e altri

6

Godlewski, M., E. Guziewicz, S. Gierałtowska, G. Łuka, T. Krajewski, Ł. Wachnicki e K. Kopalko. "Barriers in Miniaturization of Electronic Devices and the Ways to Overcome Them - from a Planar to 3D Device Architecture". Acta Physica Polonica A 116, Supplement (dicembre 2009): S—19—S—21. http://dx.doi.org/10.12693/aphyspola.116.s-19.

Testo completo

Gli stili APA, Harvard, Vancouver, ISO e altri

7

Zhou, Zheng, Jia Xu, Li Xiao, Jing Chen, Zhan'ao Tan, Jianxi Yao e Songyuan Dai. "Efficient planar perovskite solar cells prepared via a low-pressure vapor-assisted solution process with fullerene/TiO2 as an electron collection bilayer". RSC Advances 6, n. 82 (2016): 78585–94. http://dx.doi.org/10.1039/c6ra14372e.

Testo completo

Gli stili APA, Harvard, Vancouver, ISO e altri

8

Turren-Cruz, Silver-Hamill, Anders Hagfeldt e Michael Saliba. "Methylammonium-free, high-performance, and stable perovskite solar cells on a planar architecture". Science 362, n. 6413 (11 ottobre 2018): 449–53. http://dx.doi.org/10.1126/science.aat3583.

Testo completo

Abstract (sommario):

Currently, perovskite solar cells (PSCs) with high performances greater than 20% contain bromine (Br), causing a suboptimal bandgap, and the thermally unstable methylammonium (MA) molecule. Avoiding Br and especially MA can therefore result in more optimal bandgaps and stable perovskites. We show that inorganic cation tuning, using rubidium and cesium, enables highly crystalline formamidinium-based perovskites without Br or MA. On a conventional, planar device architecture, using polymeric interlayers at the electron- and hole-transporting interface, we demonstrate an efficiency of 20.35% (stabilized), one of the highest for MA-free perovskites, with a drastically improved stability reached without the stabilizing influence of mesoporous interlayers. The perovskite is not heated beyond 100°C. Going MA-free is a new direction for perovskites that are inherently stable and compatible with tandems or flexible substrates, which are the main routes commercializing PSCs.

Gli stili APA, Harvard, Vancouver, ISO e altri

9

Ju, J. H., X. J. Shi e S. F. Yu. "(Invited) A Comparison of Device Architecture, Electrical Performance and Process Flow between FinFET and Planar MOSFETs". ECS Transactions 60, n. 1 (27 febbraio 2014): 745–50. http://dx.doi.org/10.1149/06001.0745ecst.

Testo completo

Gli stili APA, Harvard, Vancouver, ISO e altri

10

Huang, Pei-Chen, e Chang-Chun Lee. "Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique". Materials 14, n. 18 (11 settembre 2021): 5226. http://dx.doi.org/10.3390/ma14185226.

Testo completo

Abstract (sommario):

Stress-induced performance change in electron packaging architecture is a major concern when the keep-out zone (KOZ) and corresponding integration density of interconnect systems and transistor devices are considered. In this study, a finite element analysis (FEA)-based submodeling approach is demonstrated to analyze the stress-affected zone of through-silicon via (TSV) and its influences on a planar metal oxide semiconductor field transistor (MOSFET) device. The feasibility of the widely adopted analytical solution for TSV stress-affected zone estimation, Lamé radial stress solution, is investigated and compared with the FEA-based submodeling approach. Analytic results reveal that the Lamé stress solution overestimates the TSV-induced stress in the concerned device by over 50%, and the difference in the estimated results of device performance between Lamé stress solution and FEA simulation can reach 22%. Moreover, a silicon–germanium-based lattice mismatch stressor is designed in a silicon p-type MOSFET, and its effects are analyzed and compared with those of TSV residual stress. The S/D stressor dominates the stress status of the device channel. The demonstrated FEA-based submodeling approach is effective in analyzing the stress impact from packaging and device-level components and estimating the KOZ issue in advanced electronic packaging.

Gli stili APA, Harvard, Vancouver, ISO e altri

11

Chen, Tingting, Rui He, Fan Zhang, Xia Hao, Zhipeng Xuan, Yunfan Wang, Wenwu Wang, Dewei Zhao, Jingquan Zhang e Lili Wu. "GABr Post-Treatment for High-Performance MAPbI3 Solar Cells on Rigid Glass and Flexible Substrate". Nanomaterials 11, n. 3 (16 marzo 2021): 750. http://dx.doi.org/10.3390/nano11030750.

Testo completo

Abstract (sommario):

Perovskite solar cells have exhibited astonishing photoelectric conversion efficiency and have shown a promising future owing to the tunable content and outstanding optoelectrical property of hybrid perovskite. However, the devices with planar architecture still suffer from huge Voc loss and severe hysteresis effect. In this research, Guanidine hydrobromide (GABr) post-treatment is carried out to enhance the performance of MAPbI3 n-i-p planar perovskite solar cells. The detailed characterization of perovskite suggests that GABr post-treatment results in a smoother absorber layer, an obvious reduction of trap states and optimized energy level alignment. By utilizing GABr post-treatment, the Voc loss is reduced, and the hysteresis effect is alleviated effectively in MAPbI3 solar cells. As a result, solar cells based on glass substrate with efficiency exceeding 20%, Voc of 1.13 V and significantly mitigated hysteresis are fabricated successfully. Significantly, we also demonstrate the effectiveness of GABr post-treatment in flexible device, whose efficiency is enhanced from 15.77% to 17.57% mainly due to the elimination of Voc loss.

Gli stili APA, Harvard, Vancouver, ISO e altri

12

Zhao, Chao, e Jinjuan Xiang. "Atomic Layer Deposition (ALD) of Metal Gates for CMOS". Applied Sciences 9, n. 11 (11 giugno 2019): 2388. http://dx.doi.org/10.3390/app9112388.

Testo completo

Abstract (sommario):

The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

Gli stili APA, Harvard, Vancouver, ISO e altri

13

Le, Binh H., Songrui Zhao, Xianhe Liu, Steffi Y. Woo, Gianluigi A. Botton e Zetian Mi. "Controlled Coalescence of AlGaN Nanowire Arrays: An Architecture for Nearly Dislocation-Free Planar Ultraviolet Photonic Device Applications". Advanced Materials 28, n. 38 (4 agosto 2016): 8446–54. http://dx.doi.org/10.1002/adma.201602645.

Testo completo

Gli stili APA, Harvard, Vancouver, ISO e altri

14

SHIK, ALEXANDER, HARRY E. RUDA e SLAVA V. ROTKIN. "ELECTROSTATICS OF NANOWIRES AND NANOTUBES: APPLICATION FOR FIELD–EFFECT DEVICES". International Journal of High Speed Electronics and Systems 16, n. 04 (dicembre 2006): 937–58. http://dx.doi.org/10.1142/s0129156406004090.

Testo completo

Abstract (sommario):

We present a quantum and classical theory of electronic devices with one–dimensional (1D) channels made of a single carbon nanotube or a semiconductor nanowire. An essential component of the device theory is a self–consistent model for electrostatics of 1D systems. It is demonstrated that specific screening properties of 1D wires result in a charge distribution in the channel different from that in bulk devices. The drift–diffusion model has been applied for studying transport in a long channel 1D field–effect transistor. A unified self–consistent description is given for both a semiconductor nanowire and a single–wall nanotube. Within this basic model we analytically calculate equilibrium (at zero current) and quasi–equilibrium (at small current) charge distributions in the channel. Numerical results are presented for arbitrary values of the driving current. General analytic expressions, found for basic device characteristic, differ from equations for a standard bulk three–dimensional field–effect device. The device characteristics are shown to be sensitive to the gate and leads geometry and are analyzed separately for bulk, planar and quasi–1D contacts. The basic model is generalized to take into account external charges which can be polarized and/or moving near the channel. These charges change the self–consistent potential profile in the channel and may show up in device properties, for instance, a hysteresis may develop which can have a memory application.

Gli stili APA, Harvard, Vancouver, ISO e altri

15

Kim, Kyung-Tae, Seung-Han Kang, Seung-Ji Nam, Chan-Yong Park, Jeong-Wan Jo, Jae-Sang Heo e Sung-Kyu Park. "Skin-Compatible Amorphous Oxide Thin-Film-Transistors with a Stress-Released Elastic Architecture". Applied Sciences 11, n. 12 (14 giugno 2021): 5501. http://dx.doi.org/10.3390/app11125501.

Testo completo

Abstract (sommario):

A highly reliable reverse-trapezoid-structured polydimethylsiloxane (PDMS) is demonstrated to achieve mechanically enhanced amorphous indium-gallium-zinc oxide (a-IGZO) thin-film-transistors (TFTs) for skin-compatible electronics. Finite element analysis (FEA) simulation reveals that the stress within a-IGZO TFTs can be efficiently reduced compared to conventional substrates. Based on the results, a conventional photolithography process was employed to implement the reverse-trapezoid homogeneous structures using a negative photoresist (NPR). Simply accessible photolithography using NPR enabled high-resolution patterning and thus large-area scalable device architectures could be obtained. The a-IGZO TFTs on the reverse-trapezoid-structured PDMS exhibited a maximum saturation mobility of 6.06 cm2V−1s−1 under a drain bias voltage of 10 V with minimal strain stress. As a result, the proposed a-IGZO TFTs, including stress-released architecture, exhibited highly enhanced mechanical properties, showing saturation mobility variation within 12% under a strain of 15%, whereas conventional planar a-IGZO TFTs on PDMS showed mobility variation over 10% even under a 1% strain and failed to operate beyond a 2% strain.

Gli stili APA, Harvard, Vancouver, ISO e altri

16

Zhang, Han, e Xue-lei Liang. "Bistable electrowetting device with non-planar designed controlling electrodes for display applications". Frontiers of Information Technology & Electronic Engineering 20, n. 9 (settembre 2019): 1289–95. http://dx.doi.org/10.1631/fitee.1800167.

Testo completo

Gli stili APA, Harvard, Vancouver, ISO e altri

17

Dunham, Brandon, Vivek Vattipalli e Christos Dimitrakopoulos. "Evaporation-Induced Self-Assembly of Semi-Crystalline PbI2(DMSO) Complex Films as a Facile Route to Reproducible and Efficient Planar p-i-n Perovskite Solar Cells". MRS Advances 3, n. 32 (2018): 1807–17. http://dx.doi.org/10.1557/adv.2018.137.

Testo completo

Abstract (sommario):

ABSTRACTHigh quality active layers for hybrid organic-inorganic perovskite solar cells are essential for achieving maximum device performance. However, perovskite active layers in solar cells are frequently prepared with unoptimized processes that lead to layers of inferior quality. This is often the case when research focuses on other aspects of the solar cell device, such as device design and architecture, carrier transport layers, electrodes, interlayers, etc. In this study, a single-step spin-coating method was used to prepare semi-crystalline PbI2(DMSO) complex films via evaporation-induced self-assembly. These optimized intermediate films were then used to form homogeneous methylammonium lead iodide (MAPbI3) perovskite films of optimum thickness (ca. 400 nm) with uniform surface coverage, good crystallinity, high purity, and grain sizes up to one micron, by employing a sequential deposition process involving intramolecular exchange between the PbI2(DMSO) complex film and a methylammonium iodide (MAI) layer deposited on top of it. We found that for certain ranges of MAI concentration, the formation of optimal-quality perovskite active layers was independent of MAI concentration, so long as MAI deposition occurred at specific corresponding spin speeds. Planar p-i-n perovskite solar cells comprising the optimized active layers were fabricated, and they exhibited negligible hysteresis and a maximum power conversion efficiency (PCE) of 16.72%, without any additional compositional and interfacial engineering. The latter can be used in the future to further enhance the PCE. These findings demonstrate the importance of an optimized perovskite active layer for reproducibly fabricating high-efficiency planar p-i-n photovoltaic devices. Additionally, the simplicity of the PbI2(DMSO) complex film preparation and the versatility of the MAI deposition with this fabrication method further enhances the potential of this material for large-scale processing.

Gli stili APA, Harvard, Vancouver, ISO e altri

18

Steckiewicz, Adam, Kornelia Konopka, Agnieszka Choroszucho e Jacek Maciej Stankiewicz. "Temperature Measurement at Curved Surfaces Using 3D Printed Planar Resistance Temperature Detectors". Electronics 10, n. 9 (7 maggio 2021): 1100. http://dx.doi.org/10.3390/electronics10091100.

Testo completo

Abstract (sommario):

In this article, novel 3D printed sensors for temperature measurement are presented. A planar structure of the resistive element is made, utilizing paths of a conductive filament embedded in an elastic base. Both electrically conductive and flexible filaments are used simultaneously during the 3D printing procedure, to form a ready–to–use measuring device. Due to the achieved flexibility, the detectors may be used on curved and irregular surfaces, with no concern for their possible damage. The geometry and properties of the proposed resistance detectors are discussed, along with a printing procedure. Numerical models of considered sensors are characterized, and the calculated current distributions as well as equivalent resistances of the different structures are compared. Then, a nonlinear influence of temperature on the resistance is experimentally determined for the exemplary planar sensors. Based on these results, using first–order and hybrid linear–exponential approximations, the analytical formulae are derived. Additionally, the device to measure an average temperature from several measuring surfaces is considered. Since geometry of the sensor can be designed utilizing presented approach and printed by applying fused deposition modeling, the functional device can be customized to individual needs.

Gli stili APA, Harvard, Vancouver, ISO e altri

19

Zhang, Wenqiang, Zhenguo Zhang, Mengyang Li e Xiaofei Chen. "GPU implementation of curved-grid finite-difference modelling for non-planar rupture dynamics". Geophysical Journal International 222, n. 3 (13 giugno 2020): 2121–35. http://dx.doi.org/10.1093/gji/ggaa290.

Testo completo

Abstract (sommario):

SUMMARY A deep understanding of earthquake physics requires a large amount of numerical simulations on seismic wave propagation and dynamic rupture. However, the corresponding intensive computational expense of simulations at traditional CPU (central processing unit) platforms make related researches time-consuming. There are many mature graphics processing unit (GPU) programs that can dramatically accelerate the calculation of seismic wave propagation. Unfortunately, there are few discussions about GPU implementations for rupture dynamics. In this work, we extend our 3-D curved-grid finite-difference method (CG-FDM) for rupture dynamics to the GPU platform using the CUDA (compute unified device architecture) programming language. By taking advantage of the new features of the NVIDIA Volta architecture, we implement the GPU-based program for rupture dynamics that is not only efficient but also easy to maintain. The GPU-based CG-FDM program is two orders of magnitude faster than our previous serial CPU-based program and still has a considerable advantage compared with the parallel one. The reliability and correctness of the program are carefully examined by the comparisons of the benchmarks from the ‘Southern California Earthquake Center/U.S. Geological Survey (SCEC/USGS) Dynamic Earthquake Rupture Code Verification Exercise’. The performance improvements of the GPU-based CG-FDM can save a lot of computing time, allowing researchers to perform much more numerical simulations of rupture dynamics to reveal more details of earthquake physics.

Gli stili APA, Harvard, Vancouver, ISO e altri

20

Bogdanowicz, Krzysztof Artur, Beata Jewłoszewicz, Agnieszka Iwan, Karolina Dysz, Wojciech Przybyl, Adam Januszko, Monika Marzec et al. "Selected Electrochemical Properties of 4,4’-((1E,1’E)-((1,2,4-Thiadiazole-3,5-diyl)bis(azaneylylidene))bis(methaneylylidene))bis(N,N-di-p-tolylaniline) towards Perovskite Solar Cells with 14.4% Efficiency". Materials 13, n. 11 (27 maggio 2020): 2440. http://dx.doi.org/10.3390/ma13112440.

Testo completo

Abstract (sommario):

Planar perovskite solar cells were fabricated on F-doped SnO2 (FTO) coated glass substrates, with 4,4’-((1E,1’E)-((1,2,4-thiadiazole-3,5-diyl)bis(azaneylylidene))bis(methaneylylidene))bis(N,N-di-p-tolylaniline) (bTAThDaz) as hole transport material. This imine was synthesized in one step reaction, starting from commercially available and relatively inexpensive reagents. Electrochemical, optical, electrical, thermal and structural studies including thermal images and current-voltage measurements of the full solar cell devices characterize the imine in details. HOMO-LUMO of bTAThDaz were investigated by cyclic voltammetry (CV) and energy-resolved electrochemical impedance spectroscopy (ER-EIS) and were found at −5.19 eV and −2.52 eV (CV) and at −5.5 eV and −2.3 eV (ER-EIS). The imine exhibited 5% weight loss at 156 °C. The electrical behavior and photovoltaic performance of the perovskite solar cell was examined for FTO/TiO2/perovskite/bTAThDaz/Ag device architecture. Constructed devices exhibited good time and air stability together with quite small effect of hysteresis. The observed solar conversion efficiency was 14.4%.

Gli stili APA, Harvard, Vancouver, ISO e altri

21

Kim, Bum Jun, Byung Joo Jeong, Seungbae Oh, Sudong Chae, Kyung Hwan Choi, Tuqeer Nasir, Sang Hoon Lee et al. "Thickness-Dependence Electrical Characterization of the One-Dimensional van der Waals TaSe3 Crystal". Materials 12, n. 15 (2 agosto 2019): 2462. http://dx.doi.org/10.3390/ma12152462.

Testo completo

Abstract (sommario):

Needle-like single crystalline wires of TaSe3 were massively synthesized using the chemical vapor transport method. Since the wedged-shaped single TaSe3 molecular chains were stacked along the b-axis by weak van der Waals interactions, a few layers of TaSe3 flakes could be easily isolated using a typical mechanical exfoliation method. The exfoliated TaSe3 flakes had an anisotropic planar structure, and the number of layers could be controlled by a repeated peeling process until a monolayer of TaSe3 nanoribbon was obtained. Through atomic force and scanning Kelvin probe microscope analyses, it was found that the variation in the work function with the thickness of the TaSe3 flakes was due to the interlayer screening effect. We believe that our results will not only help to add a novel quasi-1D block for nanoelectronics devices based on 2D van der Waals heterostructures, but also provide crucial information for designing proper contacts in device architecture.

Gli stili APA, Harvard, Vancouver, ISO e altri

22

Simonetti, Davide, Loredana Zollo, Luca Vollero, Giulio Iannello e Eugenio Guglielmelli. "A modular telerehabilitation architecture for upper limb robotic therapy". Advances in Mechanical Engineering 9, n. 2 (febbraio 2017): 168781401668725. http://dx.doi.org/10.1177/1687814016687252.

Testo completo

Abstract (sommario):

Several factors may prevent post-stroke subjects from participating in rehabilitation protocols, for example, geographical location of rehabilitation centres, socioeconomic status, economic burden and lack of logistics surrounding transportation. Early supported discharge from hospitals with continued rehabilitation at home represents a well-defined regimen of post-stroke treatment. Information-based technologies coupled with robotics have promoted the development of new technologies for telerehabilitation. In this article, the design and development of a modular architecture for delivering upper limb robotic telerehabilitation with the CBM-Motus, a planar unilateral robotic machine that allows performing state-of-the-art rehabilitation tasks, have been presented. The proposed architecture allows a therapist to set a therapy session on his or her side and send it to the patient’s side with a standardized communication protocol; the user interacts with the robot that provides an adaptive assistance during the rehabilitation tasks. Patient’s performance is evaluated by means of performance indicators, which are also used to update robot behaviour during assistance. The implementation of the architecture is described and a set of validation tests on seven healthy subjects are presented. Results show the reliability of the novel architecture and the capability to be easily tailored to the user’s needs with the chosen robotic device.

Gli stili APA, Harvard, Vancouver, ISO e altri

23

Safari, Zeinab, Mahmood Borhani Zarandi, Antonella Giuri, Francesco Bisconti, Sonia Carallo, Andrea Listorti, Carola Esposito Corcione, Mohamad Reza Nateghi, Aurora Rizzo e Silvia Colella. "Optimizing the Interface between Hole Transporting Material and Nanocomposite for Highly Efficient Perovskite Solar Cells". Nanomaterials 9, n. 11 (16 novembre 2019): 1627. http://dx.doi.org/10.3390/nano9111627.

Testo completo

Abstract (sommario):

The performances of organometallic halide perovskite-based solar cells severely depend on the device architecture and the interface between each layer included in the device stack. In particular, the interface between the charge transporting layer and the perovskite film is crucial, since it represents both the substrate where the perovskite polycrystalline film grows, thus directly influencing the active layer morphology, and an important site for electrical charge extraction and/or recombination. Here, we focus on engineering the interface between a perovskite-polymer nanocomposite, recently developed by our group, and different commonly employed polymeric hole transporters, namely PEDOT: PSS [poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate)], PEDOT, PTAA [poly(bis 4-phenyl}{2,4,6-trimethylphenyl}amine)], Poly-TPD [Poly(N,N′-bis(4-butylphenyl)-N,N′-bis(phenyl)-benzidine] Poly-TPD, in inverted planar perovskite solar cell architecture. The results show that when Poly-TPD is used as the hole transfer material, perovskite film morphology improved, suggesting an improvement in the interface between Poly-TPD and perovskite active layer. We additionally investigate the effect of the Molecular Weight (MW) of Poly-TPD on the performance of perovskite solar cells. By increasing the MW, the photovoltaic performances of the cells are enhanced, reaching power conversion efficiency as high as 16.3%.

Gli stili APA, Harvard, Vancouver, ISO e altri

24

Lee, Jaehoon, Changyeop Jeon, Taehyeong Jeon, Proloy Das, Yongho Lee, Byeonghwa Lim e CheolGi Kim. "Bridge Resistance Compensation for Noise Reduction in a Self-Balanced PHMR Sensor". Sensors 21, n. 11 (21 maggio 2021): 3585. http://dx.doi.org/10.3390/s21113585.

Testo completo

Abstract (sommario):

Advanced microelectromechanical system (MEMS) magnetic field sensor applications demand ultra-high detectivity down to the low magnetic fields. To enhance the detection limit of the magnetic sensor, a resistance compensator integrated self-balanced bridge type sensor was devised for low-frequency noise reduction in the frequency range of 0.5 Hz to 200 Hz. The self-balanced bridge sensor was a NiFe (10 nm)/IrMn (10 nm) bilayer structure in the framework of planar Hall magnetoresistance (PHMR) technology. The proposed resistance compensator integrated with a self-bridge sensor architecture presented a compact and cheaper alternative to marketable MEMS MR sensors, adjusting the offset voltage compensation at the wafer level, and led to substantial improvement in the sensor noise level. Moreover, the sensor noise components of electronic and magnetic origin were identified by measuring the sensor noise spectral density as a function of temperature and operating power. The lowest achievable noise in this device architecture was estimated at ~3.34 nV/Hz at 100 Hz.

Gli stili APA, Harvard, Vancouver, ISO e altri

25

Weikle, Robert M., S. Nadri, C. M. Moore, N. D. Sauber, L. Xie, M. E. Cyberey, N. Scott Barker, A. W. Lichtenberger e M. Zebarjadi. "Thermal Characterization of Quasi-Vertical GaAs Schottky Diodes Integrated on Silicon Using Thermoreflectance and Electrical Transient Measurements". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (1 gennaio 2019): 001293–310. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_tha3_009.

Testo completo

Abstract (sommario):

Thermal management and design have been understood, for many years, as critical factors in the implementation of submillimeter-wave Schottky-diode-based circuits and instruments. Removal of heat is particularly important for frequency multipliers, as these circuits generally exhibit low-to-modest conversion efficiencies, and are usually driven with high-power sources to achieve usable output power in the submillimeter-wave region of the spectrum. Elevated diode junction temperature due to inadequate heat sinking is known to degrade performance, accelerate aging effects (for example, due to electromigration, ohmic contact deterioration, or thermally-induced stress), and can ultimately lead to device failure. The relatively-low thermal conductivity of GaAs (the predominant material technology for submillimeter-wave diodes), coupled with restrictions on diode anode size and geometry needed to minimize parasitics and achieve the device impedances required for high-frequency operation, present significant challenges and trade-offs between electrical and thermal designs of these devices. Recognition that heating is a major factor limiting efficiency and output power has prompted a number of approaches to mitigate excessive temperature rise in the junction of planar Schottky diodes, including the use of AlN or diamond as low-loss substrates that act as heat spreaders. A new diode topology, based on a quasi-vertical geometry that is realized through heterogeneous integration of GaAs with high-resistivity silicon, was recently developed at the University of Virginia for submillimeter-wave applications. Unlike planar diodes, the device structure of the quasi-vertical diode consists of a metal contact that underlies the diode's anode and epitaxial mesa, thus providing a large-area ohmic cathode contact that also serves as an integrated heat sink. Measurement of high-efficiency multipliers based on this technology suggest the quasi-vertical architecture provides an effective approach for heat removal and thermal management in Schottky diodes. This paper presents the first results reporting thermal performances of terahertz quasi-vertical GaAs Schottky diodes integrated on silicon. The devices are characterized using a thermoreflectance measurement technique, a method based on the change in refractive index, and therefore surface reflectivity, with changes in temperature. Heating and cooling temperature profiles and 2-D temperature maps are obtained for 3.5 micron and 5.5 micron diameter diodes. From these measurements, the device thermal resistances, junction temperatures, and thermal time-constants are extracted. Equivalent thermal circuit and finite element models are developed to study the device geometry, and extract material thermal parameters. The devices are also characterized using an electrical transient method, and the temperature and cooling transients found from this technique are found to be comparable to those obtained from thermoreflectance measurements. The quasi-vertical diodes studied in this work are shown to demonstrate a faster transient thermal response compared to flip-chip bonded terahertz diodes reported in the literature.

Gli stili APA, Harvard, Vancouver, ISO e altri

26

DIDUCK, QUENTIN, HIROSHI IRIE e MARTIN MARGALA. "A ROOM TEMPERATURE BALLISTIC DEFLECTION TRANSISTOR FOR HIGH PERFORMANCE APPLICATIONS". International Journal of High Speed Electronics and Systems 19, n. 01 (marzo 2009): 23–31. http://dx.doi.org/10.1142/s0129156409006060.

Testo completo

Abstract (sommario):

The Ballistic Deflection Transistor (BDT) is a novel device that is based upon an electron steering and a ballistic deflection effect. Composed of an InGaAs - InAlAs heterostructure on an InP substrate, this material system provides a large mean free path and high mobility to support ballistic transport at room temperature. The planar nature of the device enables a two step lithography process, as well, implies a very low capacitance design. This transistor is unique in that no doping junction or barrier structure is employed. Rather, the transistor utilizes a two-dimensional electron gas (2DEG) to achieve ballistic electron transport in a gated microstructure, combined with asymmetric geometrical deflection. Motivated by reduced transit times, the structure can be operated such that current never stops flowing, but rather is only directed toward one of two output drain terminals. The BDT is unique in that it possesses both a positive and negative transconductance region. Experimental measurements have indicated that the transconductance of the device increases with applied drain-source voltage. DC measurements of prototype devices have verified small signal voltage gains of over 150, with transconductance values from 45 to 130 mS/mm depending upon geometry and bias. Gate-channel separation is currently 80nm, and allows for higher transconductance through scaling. The six terminal device enables a normally differential mode of operation, and provides two drain outputs. These outputs, depending on gate bias, are either complementary or non-complementary. This facilitates a wide variety of circuit design techniques. Given the ultralow capacitive design, initial estimates of ft, for the device fabricated with a 430nm gate width, are over a THz.

Gli stili APA, Harvard, Vancouver, ISO e altri

27

Liu, Zhuang, Jianlin Chen, Caiyou Huang, Too Gideon Kiprono, Wusong Zhao, Wei Qiu, Zhuoyin Peng e Jian Chen. "Dependence of Precursors on Solution-Processed SnO2 as Electron Transport Layers for CsPbBr3 Perovskite Solar Cells". Nano 15, n. 12 (25 novembre 2020): 2050161. http://dx.doi.org/10.1142/s1793292020501611.

Testo completo

Abstract (sommario):

In this paper, three kinds of SnO2 precursors were comparatively investigated for low temperature solution-processed SnO2 films as electron transport layers (ETL) of CsPbBr3 perovskite solar cells (PSCs). It was found that the precursor state and solvent type played an important role on the crystallinity and film-forming performance of SnO2. All-inorganic hole-transport-layer-free planar CsPbBr3 PSCs with an architecture of FTO/SnO2/CsPbBr3/carbon were fabricated. The best-performing device with SnO2 as ETL by reflux condensation sol spin-coating technique delivered a champion power conversion efficiency (PCE) as high as 6.27%, with a short-circuit current density of 7.36[Formula: see text]mA[Formula: see text]cm[Formula: see text], an open-circuit voltage of 1.29[Formula: see text]V, and a fill factor of 65.9%. It was comparable to the highest PCE record 6.7% of the device with the same structure based on TiO2-ETL so far. Moreover, the CsPbBr3 devices without encapsulation exhibited good stability after being stored under ambient conditions with a relative humidity of [Formula: see text]% at room temperature over 1000[Formula: see text]h and 60[Formula: see text]C for 720[Formula: see text]h, respectively. The results promise the commercial potential of CsPbBr3 PSCs using reflux condensation low-temperature solution-processed SnO2 as ETLs for flexible polymer photovoltaic applications.

Gli stili APA, Harvard, Vancouver, ISO e altri

28

Adjokatse, Sampson, Jane Kardula, Hong‐Hua Fang, Shuyan Shao, Gert H. ten Brink e Maria Antonietta Loi. "Effect of the Device Architecture on the Performance of FA 0.85 MA 0.15 PbBr 0.45 I 2.55 Planar Perovskite Solar Cells". Advanced Materials Interfaces 6, n. 6 (4 febbraio 2019): 1801667. http://dx.doi.org/10.1002/admi.201801667.

Testo completo

Gli stili APA, Harvard, Vancouver, ISO e altri

29

MORENO, MARIO, ANDREY KOSAREV, ALFONSO TORRES e ROBERTO AMBROSIO. "MICROBOLOMETERS FABRICATED WITH SURFACE MICROMACHINING WITH a-Si-Ge: H THERMO-SENSING FILMS". International Journal of High Speed Electronics and Systems 18, n. 04 (dicembre 2008): 1045–54. http://dx.doi.org/10.1142/s0129156408005990.

Testo completo

Abstract (sommario):

In this work we present the process flow for the fabrication of un-cooled IR detectors employing surface micro-machining techniques over silicon substrates. These detectors are based on thin films deposited by plasma at low temperatures. The thermo sensing film used is an intrinsic a - Si x Ge 1- x : H film, which has demonstrated a very high temperature coefficient of resistance (TCR), and a moderated resistivity, these properties are better than those of the a - Si : H intrinsic film, which is commonly used in commercial IR devices. Two device configurations have been designed and fabricated, labeled planar and sandwich. The former is the configuration commonly used in commercial micro-bolometers, while the latter is proposed in order to reduce the high cell resistance observed in this kind of devices, without the necessity of doping the intrinsic film, which results in a decrement of the TCR and therefore in responsivity. Finally some performance characteristics of the devices studied are discussed in comparison with data reported in literature.

Gli stili APA, Harvard, Vancouver, ISO e altri

30

Descamps, Philippe, Olivier Tesson, Magali Duplessis, Daniel Pasquet e Hugues Murray. "Analytic description, measurements, and modeling of 3D-embedded silicon inductance for High-Performance Hybrid Systems Applications". International Journal of Microwave and Wireless Technologies 5, n. 4 (21 marzo 2013): 463–76. http://dx.doi.org/10.1017/s1759078713000111.

Testo completo

Abstract (sommario):

In this paper, the design and the measurements of three-dimensional through silicon vias (TSVs) based-integrated solenoids embedded within high-resistive silicon is presented. Prior to silicon implementation, a rigorous theoretical analysis is proposed to put in obviousness the advantages of using such coil architecture for L and S band applications. This analysis, demonstrates a clear reduction of the footprint passive function lying on the external substrate together with a reduced capacitive coupling with the local environment. Two-port radio frequency measurements have been performed in a wide-frequency range (100 MHz – 50 GHz) in order to support the theoretical investigations. Solenoids exhibit high-quality factors below 4 GHz – Q = 25 @ 2 GHz for a 800 pH device – and clearly outperforms classical planar architecture considered in most of the integrated circuit processes. Two different modeling approaches (compact modeling and EM modeling) are then proposed in order to speed-up their design implementation in a typical CAD design flow. Based on the available data, a good agreement is shown between and simulated data.

Gli stili APA, Harvard, Vancouver, ISO e altri

31

Becker, Markus, e Michael Wark. "Sequentially Deposited Compact and Pinhole-Free Perovskite Layers via Adjusting the Permittivity of the Conversion Solution". Zeitschrift für Naturforschung A 74, n. 8 (27 agosto 2019): 655–63. http://dx.doi.org/10.1515/zna-2019-0141.

Testo completo

Abstract (sommario):

AbstractThe preparation of compact and pinhole-free absorber layers is a major step towards device reproducibility and high performance for planar organic-inorganic perovskite solar cells. It is well known that the sequential deposition method exhibits some advantages over the common one-pot synthesis in terms of controlling the surface coverage. However, it still miscarries to produce pinhole-free layers from solution, mainly due to the occurrence of dissolution and recrystallisation processes. We show that by a careful choice of the permittivity of the alcoholic solvent in the conversion step the surface morphology can be finely modified, thereby yielding pinhole-free and compact absorber films comparable to that from vapour-assisted solution techniques. It is observed that the permittivity controls the intensity of the Ostwald ripening effect and that a low value of the former enables an in situ intercalation of precursor materials into the lead halide framework. We successfully prepared smooth and mirror-like perovskite surfaces that demonstrate enhanced optoelectronic properties and photovoltaic performance compared to films from the native two-step deposition in isopropanol. This strategy provides a facile approach for obtaining high-quality layers in the planar architecture by simple solution processing.

Gli stili APA, Harvard, Vancouver, ISO e altri

32

Veszely, Gyula. "A 3D Nonlinear Poisson Solver". VLSI Design 8, n. 1-4 (1 gennaio 1998): 545–48. http://dx.doi.org/10.1155/1998/16750.

Testo completo

Abstract (sommario):

The Poisson equation is solved in a rectangular prism of semiconductor with the boundary conditions commonly used in semiconductor device modeling. There is a planar heterojunction inside the prism. The finite difference formulation leading to a matrix of seven diagonals is used. The 3D version of the Stone's method is applied for the iterative solution of the matrix equation. The nonlinear dependence of the carrier concentration on the electrostatic potential is taken into account. The heterojunction is modeled by a potential jump. The advantages and limits of the method is presented.

Gli stili APA, Harvard, Vancouver, ISO e altri

33

Seto, Satoru, Rintaro Shimizu e Makoto Tokuda. "Conversion of metal-organic halide perovskite from PbI2 precursor films grown by hot-wall method". MATEC Web of Conferences 192 (2018): 01031. http://dx.doi.org/10.1051/matecconf/201819201031.

Testo completo

Abstract (sommario):

We report on metal-organic halide perovskite CH3NH3PbI3 films converted from PbI2 precursors for planar heterojunction perovskite solar cells. PbI2 films as a precursor were deposited by hot-wall method and conventional vacuum evaporation. The conversion to perovskite phase from the PbI2 films were performed by annealing in methyl ammonium iodine (MAI) vapour at 120-150 °C. We confirmed that no residual PbI2 phase can be detected in the converted perovskite films by x-ray diffraction measurements. The surface morphology of the perovskite films was measured by AFM. Roughness Ra of the films is 17.8 nm, which is comparable value to the reported ones. Using the converted perovskite films we fabricated tentative perovskite solar cells with a device architecture of ITO/PEDOT:PSS/Perovskite/C60/Ag. The power conversion efficiencies of the fabricated solar cells from a conventional evaporation and the hot-wall method exhibited 2.22 and 2.33%, respectively.

Gli stili APA, Harvard, Vancouver, ISO e altri

34

FOBELETS, K., P. W. DING, Y. SHADROKH e J. E. VELAZQUEZ-PEREZ. "ANALOG AND DIGITAL PERFORMANCE OF THE SCREEN-GRID FIELD EFFECT TRANSISTOR (SGRFET)". International Journal of High Speed Electronics and Systems 18, n. 04 (dicembre 2008): 783–92. http://dx.doi.org/10.1142/s012915640800576x.

Testo completo

Abstract (sommario):

The Screen-Grid Field Effect Transistor (SGrFET) is a planar MOSFET-type device with a gating configuration consisting of metal cylindrical fingers inside the channel perpendicular to the current flow. The SGrFET operates in a MESFET mode using oxide insulated gates. The multi-gate configuration offers advantages for both analog and digital applications, whilst the gate cylinder holes can be exploited for bio-applications. In this manuscript TCAD results are presented on the analog and digital performance of the Screen-Grid Field Effect Transistor. The results are compared to the operation of an SOI-MOSFET and a finFET.

Gli stili APA, Harvard, Vancouver, ISO e altri

35

SOOLE, J. B. D., H. P. LeBLANC, N. C. ANDREADAKIS, R. BHAT, C. CANEAU e M. A. KOZA. "MONOLITHIC InP REFLECTION-GRATING MULTIPLEXER/DEMULTIPLEXERS FOR WDM COMPONENTS OPERATING IN THE LONG WAVELENGTH FIBER BAND". International Journal of High Speed Electronics and Systems 05, n. 01 (marzo 1994): 111–33. http://dx.doi.org/10.1142/s0129156494000061.

Testo completo

Abstract (sommario):

We discuss an emerging monolithic “photonic integrated circuit” technology for application in future wavelength division multiplexed (WDM) networks. Based on a planar reflection-grating wavelength multiplexer/demultiplexer, and realized in InP-matched material for the long wavelength fiber band, the WDM optical cavity may be integrated with different active elements to provide a variety of spectrally-matched WDM functional components. We consider the design and performance of the basic mux/demux, and review the current status of both the passive device and integrated active components. We also look to the future and assess prospective near-term advancements.

Gli stili APA, Harvard, Vancouver, ISO e altri

36

Bobeico, Eugenia, Lucia V. Mercaldo, Pasquale Morvillo, Iurie Usatii, Marco Della Noce, Laura Lancellotti, Carmen Sasso, Rosa Ricciardi e Paola Delli Veneri. "Evaporated MoOx as General Back-Side Hole Collector for Solar Cells". Coatings 10, n. 8 (6 agosto 2020): 763. http://dx.doi.org/10.3390/coatings10080763.

Testo completo

Abstract (sommario):

Substoichiometric molybdenum oxide (MoOx) has good potential as a hole-collecting layer in solar cells. In this paper, we report on the application of ultrathin evaporated MoOx as a hole collector at the back side of two distinct photovoltaic technologies: polymeric and silicon heterojunction (SHJ). In the case of polymer solar cells, we test MoOx as a hole transport layer in devices with inverted architecture. The higher transparency of the MoOx film, compared to the commonly used poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS), allows an enhanced back reflected light into the photoactive layer, thus boosting the photogeneration, as found from the illuminated J-V and external quantum efficiency (EQE) curves. The higher fill factor (FF) of the MoOx-based device also suggests an improved charge collection efficiency compared to the cells with PEDOT:PSS. As for SHJ solar cells, we show that MoOx offers the means for dopant-free hole collection with both p-type and n-type Si wafers. In the present comparison over planar test structures with Ag back reflecting electrodes, we observe an efficiency gain of approximately 1% absolute against a baseline with a conventional p-type amorphous silicon hole collector. The gain is linked to the increased VOC, which is likely due to the reduced recombination at the Si wafer.

Gli stili APA, Harvard, Vancouver, ISO e altri

37

Lee, Jongwon, e Myounggon Kang. "TID Circuit Simulation in Nanowire FETs and Nanosheet FETs". Electronics 10, n. 8 (16 aprile 2021): 956. http://dx.doi.org/10.3390/electronics10080956.

Testo completo

Abstract (sommario):

In this study, the effects of the total ionizing dose (TID) on a nanowire (NW) field-effect transistor (FET) and a nanosheet (NS) FET were analyzed. The devices have Gate-all-around (GAA) structure that are less affected by TID effects because GAA structures have better gate controllability than previously proposed structures, such as planar MOSFETs and FinFETs. However, even for GAA devices with the same channel cross-sectional area and equivalent oxide thickness, structural differences can exist, which can result in different tolerances of TID effects. To observe the device and circuit operation characteristics of these GAA devices with structural differences, n-type and p-type devices were designed and simulated. The circuit simulation according to TID effects was conducted using Berkeley short-channel insulated-gate FET model (BSIM) common multi-gate (CMG) parameters. The NS-FET generated more VT shift than the NW-FET because the NS-FET had a wider gate oxide area and channel circumference, resulting in more interface hole traps. The abnormal VT shift leads to causing unstable circuit operation and delays. Therefore, it was confirmed that the ability of the NW-FET to tolerate TID effects was better than that of the NS-FET.

Gli stili APA, Harvard, Vancouver, ISO e altri

38

Chen, Li, Zhifu Yin, Helin Zou, Junshan Liu, Chong Liu e Kehong Li. "A thermal bonding method based on O2 plasma and water treatment for fabrication of PET planar nanofluidic device". Microsystem Technologies 23, n. 5 (4 marzo 2016): 1327–33. http://dx.doi.org/10.1007/s00542-016-2897-0.

Testo completo

Gli stili APA, Harvard, Vancouver, ISO e altri

39

Jacqueline, Sébastien, Catherine Bunel e Laurent Lengignon. "Enhancement of ESD performances of Silicon Capacitors for RFID solutions". International Symposium on Microelectronics 2020, n. 1 (1 settembre 2020): 000085–89. http://dx.doi.org/10.4071/2380-4505-2020.1.000085.

Testo completo

Abstract (sommario):

Abstract Radio-Frequency IDentification devices such as smart cards and RFID tags are based on the presence of a resonant tuned LC circuit associated to the RFID Integrated Circuit (IC). The use of discrete capacitor, external to the IC gives greater flexibility and design freedom. In the race of miniaturization, manufacturers of RFID devices always require smaller electronic components. To save space and in the same time improve performances, capacitors are exposed to height and volume constraints. In the same time, the capacitor has to withstand ESD stresses that can occur during the assembly of the device and during operation. Murata has developed a unique thin capacitor technology in silicon. This paper reports the development of a range of low profile capacitors with enhanced ESD performances. The manufacturing process optimization and the design adjustments will be presented here. The process was optimized by taking into account the main electrical parameters: leakage current, breakdown voltage, capacitance density, capacitance accuracy, Equivalent Series Resistance (ESR) and Self-Resonant Frequency (SRF). The dielectric stack was defined in order to integrate up to 330pF in 0402 case. The process architecture, based on accurate planar capacitor with thick dielectric will be discussed. With this architecture there is no constraint to reach low thickness, such as 100μm or even lower. The ESD threshold of each Silicon Capacitor was investigated with design variations associated to Human Body Model measurements. A Single Project Wafer (SPW) was founded with 36 different capacitor designs. Design modulations specifically addressed the orientation and position of the contacts openings. Special care was taken to maximize the width of the contact holes and metal tracks. A mosaic approach, constructed out of a massive network of parallelized elementary cells was also implemented, so that the charges of the ESD pulse do not concentrate at the same place, leading to electrical failure. Examples of defects due to ESD stress will be shown with failure analysis cross-sections and ways to enhance the ESD threshold by design will be illustrated.

Gli stili APA, Harvard, Vancouver, ISO e altri

40

Mukherjee, Anwesha, e Yossi Rosenwaks. "Recent Advances in Silicon FET Devices for Gas and Volatile Organic Compound Sensing". Chemosensors 9, n. 9 (10 settembre 2021): 260. http://dx.doi.org/10.3390/chemosensors9090260.

Testo completo

Abstract (sommario):

Highly sensitive and selective gas and volatile organic compound (VOC) sensor platforms with fast response and recovery kinetics are in high demand for environmental health monitoring, industry, and medical diagnostics. Among the various categories of gas sensors studied to date, field effect transistors (FETs) have proved to be an extremely efficient platform due to their miniaturized form factor, high sensitivity, and ultra-low power consumption. Despite the advent of various kinds of new materials, silicon (Si) still enjoys the advantages of excellent and reproducible electronic properties and compatibility with complementary metal–oxide–semiconductor (CMOS) technologies for integrated multiplexing and signal processing. This review gives an overview of the recent developments in Si FETs for gas and VOC sensing. We categorised the Si FETs into Si nanowire (NW) FETs; planar Si FETs, in which the Si channel is either a part of the silicon on insulator (SOI) or the bulk Si, as in conventional FETs; and electrostatically formed nanowire (EFN) FETs. The review begins with a brief introduction, followed by a description of the Si NW FET gas and VOC sensors. A brief description of the various fabrication strategies of Si NWs and the several functionalisation methods to improve the sensing performances of Si NWs are also provided. Although Si NW FETs have excellent sensing properties, they are far from practical realisation due to the extensive fabrication procedures involved, along with other issues that are critically assessed briefly. Then, we describe planar Si FET sensors, which are much closer to real-world implementation. Their simpler device architecture combined with excellent sensing properties enable them as an efficient platform for gas sensing. The third category, the EFN FET sensors, proved to be another potential platform for gas sensing due to their intriguing properties, which are elaborated in detail. Finally, the challenges and future opportunities for gas sensing are addressed.

Gli stili APA, Harvard, Vancouver, ISO e altri

41

Springer, Scott L., e Nicola J. Ferrier. "Design and Control of a Force-Reflecting Haptic Interface for Teleoperational Grasping". Journal of Mechanical Design 124, n. 2 (16 maggio 2002): 277–83. http://dx.doi.org/10.1115/1.1470493.

Testo completo

Abstract (sommario):

In this paper the design of a multi-finger force-reflecting haptic interface device for teleoperational grasping is introduced. The haptic interface or “master” controller device is worn on the human operator’s hand and measured human finger positions are used to control the finger positions of a remote grasping manipulator or “slave” device. The slave may be a physical robotic grasping manipulator, or a computer generated representation of a human hand such as used in virtual reality applications. The forces measured by the robotic slave, or calculated for the virtual slave, are presented to the operator’s fingertips through the master providing a means for deeper human sensation of presence and better control of grasping tasks in the slave environments. Design parameters and performance measures for haptic interfaces for teleoperation are discussed. One key performance issue involving the high-speed display of forces during initial contact, especially when interacting with rigid surfaces, is addressed by the present design, reducing slave controller computation requirements and overcoming actuator response time constraints. The design presented utilizes a planar four-bar linkage for each finger, to represent each finger bend motion as a single degree of freedom, and to provide a finger bend resistance force that is substantially perpendicular to the distal finger pad throughout the full 180 degrees of finger bend motion represented. The finger linkage design, in combination with a remote position measurement and force display assembly, provides a very lightweight and low inertia system with a large workspace. The concept of a replicated finger is introduced which, in combination with a decoupled actuator and feed forward control, provides improved performance in transparent free motion, and rapid, stable touch sensation of initial contact with rigid surfaces. A distributed computation architecture with a PC based haptic interface controller and associated control algorithms are also discussed.

Gli stili APA, Harvard, Vancouver, ISO e altri

42

L. ADLER, ERIC. "BULK AND SURFACE ACOUSTIC WAVES IN ANISOTROPIC SOLIDS". International Journal of High Speed Electronics and Systems 10, n. 03 (settembre 2000): 653–84. http://dx.doi.org/10.1142/s0129156400000611.

Testo completo

Abstract (sommario):

In this paper methods for analyzing acoustic propagation characteristics for bulk and surface acoustic waves in anisotropic piezoelectric multilayers are described. The methods's conceptual usefulness is demonstrated by examples showing how problems of guided wave propagation in complicated layered surface acoustic wave device geometries are simplified. The formulation reduces the acoustoelectric equations to a first order ordinary matrix differential equation in the variables that must be continuous across interfaces. The solution to these equations is a transmission matrix that maps the variables from one layer face to the other. Interface boundary conditions for a planar multilayer are automatically satisfied by multiplying the individual transmission matrices in the appropriate order thus reducing the problem to imposing boundary conditions appropriate to the remaining free surface. The dimensionality of the problem being independent of the number of layers is a significant advantage. A classification scheme for reducing problem dimensionality, based on an understanding of crystal symmetry properties, further simplifies surface acoustic wave problems.

Gli stili APA, Harvard, Vancouver, ISO e altri

43

Pawlak, Bartlomiej J., Ray Duffy, Thomas Hoffman, Simone Severi, Susan Felch, Pierre Eyben, Benny Van Daele, Wilfried Vandervorst e Robert J. Lander. "Junction Architectures for Planar Devices". ECS Transactions 6, n. 1 (19 dicembre 2019): 351–64. http://dx.doi.org/10.1149/1.2727420.

Testo completo

Gli stili APA, Harvard, Vancouver, ISO e altri

44

Wang, Hanbin, Jinshun Bi, Mengxin Liu e Tingting Han. "Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure". Electronics 10, n. 13 (30 giugno 2021): 1585. http://dx.doi.org/10.3390/electronics10131585.

Testo completo

Abstract (sommario):

This work investigates the different sensitivities of an ion-sensitive field-effect transistor (ISFET) based on fully depleted silicon-on-insulator (FDSOI). Using computer-aided design (TCAD) tools, the sensitivity of a single-gate FDSOI based ISFET (FDSOI-ISFET) at different temperatures and the effects of the planar dual-gate structure on the sensitivity are determined. It is found that the sensitivity increases linearly with increasing temperature, reaching 890 mV/pH at 75 °C. By using a dual-gate structure and adjusting the control gate voltage, the sensitivity can be reduced from 750 mV/pH at 0 V control gate voltage to 540 mV/pH at 1 V control gate voltage. The above sensitivity changes are produced because the Nernst limit changes with temperature or the electric field generated by different control gate voltages causes changes in the carrier movement. It is proved that a single FDSOI-ISFET can have adjustable sensitivity by adjusting the operating temperature or the control gate voltage of the dual-gate device.

Gli stili APA, Harvard, Vancouver, ISO e altri

45

Abdul Tahrim, ‘Aqilah binti, Huei Chaeng Chin, Cheng Siong Lim e Michael Loong Peng Tan. "Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology". Journal of Nanomaterials 2015 (2015): 1–13. http://dx.doi.org/10.1155/2015/726175.

Testo completo

Abstract (sommario):

The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate (TG), and Hybrid CMOS (HCMOS). The performance of 1-bit FinFET-based full adder in 16-nm technology is benchmarked against conventional MOSFET-based full adder. The Predictive Technology Model (PTM) and Berkeley Shortchannel IGFET Model-Common Multi-Gate (BSIM-CMG) 16 nm low power libraries are used. Propagation delay, average power dissipation, power-delay-product (PDP), and energy-delay-product (EDP) are analysed based on all four types of full adder cell designs of both FETs. The 1-bit FinFET-based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and EDP is evident in the 1-bit FinFET-based full adder of CPL, giving the best overall performance due to its high-speed performance and good current driving capabilities.

Gli stili APA, Harvard, Vancouver, ISO e altri

46

Dean, Robert N., Colin B. Stevens e John J. Tatarchuk. "A Current-Controlled PCB Integrated MEMS Tilt Mirror". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (1 gennaio 2014): 000588–608. http://dx.doi.org/10.4071/2014dpc-ta32.

Testo completo

Abstract (sommario):

Introduction: MEMS Tilt Mirror - a miniature planar micro-mirror that can experience a 1-D or 2-D tilt in response to a control signal. Commonly used technologies- electrostatic, piezoelectric, electrothermal bimorph. Applications - laser beam steering, interferometers, dynamic signal analyzers, opticcal cross-connect switches. This paper describes the design, key features and applications of a System On Chip (SOC) ASIC (Application Specific Integrated Circuit) that has been developed under an Air Force SBIR program. The SOC device has been implemented by Honeywell International using their High Temperature SOI (Silicon On Insulator) Process. The objective of the Air Force SBIR program {1} was to investigate the potential for use of available High Temperature SOI technology devices for aerospace propulsion control system applications. Several prototype designs implemented by Embedded Systems LLC (ES-LLC) using available SOI devices identified significant limitations in the performance capability and level of integration. The diversity of propulsion system interfacing requirements demanded generic solutions so that they could be deployed in multiple applications without changes. The available devices were also not affordable due to the limited size of the market for this technology. It was therefore decided to develop a generic, reconfigurable SOC chipset {2} that could be implemented using Honeywell's HT200 Family of ASIC Gate Arrays. The paper will describe the architecture and key features of the SOC chipset solution which can be reconfigured to interface with most typical aerospace control system sensors and actuators. The SOC chipset captures all of the necessary functions required to interface with sensors such as RTD (resistance Temperature Detectors), Strain Gauges (SG) and thermocouples (TC), mass flow, speed and LVDT (Linear Variable Differential Transducer) position. The excitation circuitry required to power these interfaces is embedded in the chipset and can be reconfigured as required. The SOC chipset also contains all of the pre- and post-processing functions to convert electrical signals into digital words and send them on a data bus under the control of a host microprocessor. The SOC chipset can be powered from a Mil-Std 704F compliant power source or a conditioned DC power source. The SOC chipset when combined with other external devices can be implemented as a “Smart Node” for localized management of sensors and actuators as a part of a distributed architecture or used as a scalable building block in a more complex function such as a FADEC (Full Authority Digital Engine Control). The SOC chipset thus completes the set of all High Temperature SOI Integrated circuits required for implementation of typical Smart Nodes. It is believed that the versatility of the SOC chipset makes it a well suited, affordable, scalable building block for not only aerospace controls but also for diverse applications such as down-hole drilling, energy exploration, wind farms etc. where high temperature electronics is required.

Gli stili APA, Harvard, Vancouver, ISO e altri

47

Lee, Geun Ho, Sungmin Hwang, Junsu Yu e Hyungjin Kim. "Architecture and Process Integration Overview of 3D NAND Flash Technologies". Applied Sciences 11, n. 15 (21 luglio 2021): 6703. http://dx.doi.org/10.3390/app11156703.

Testo completo

Abstract (sommario):

In the past few decades, NAND flash memory has been one of the most successful nonvolatile storage technologies, and it is commonly used in electronic devices because of its high scalability and reliable switching properties. To overcome the scaling limit of planar NAND flash arrays, various three-dimensional (3D) architectures of NAND flash memory and their process integration methods have been investigated in both industry and academia and adopted in commercial mass production. In this paper, 3D NAND flash technologies are reviewed in terms of their architecture and fabrication methods, and the advantages and disadvantages of the architectures are compared.

Gli stili APA, Harvard, Vancouver, ISO e altri

48

Axline, C., M. Reagor, R. Heeres, P. Reinhold, C. Wang, K. Shain, W. Pfaff, Y. Chu, L. Frunzio e R. J. Schoelkopf. "An architecture for integrating planar and 3D cQED devices". Applied Physics Letters 109, n. 4 (25 luglio 2016): 042601. http://dx.doi.org/10.1063/1.4959241.

Testo completo

Gli stili APA, Harvard, Vancouver, ISO e altri

49

Banerjee, Sreetama, Daniel Bülz, Danny Reuter, Karla Hiller, Dietrich R. T. Zahn e Georgeta Salvan. "Light-induced magnetoresistance in solution-processed planar hybrid devices measured under ambient conditions". Beilstein Journal of Nanotechnology 8 (21 luglio 2017): 1502–7. http://dx.doi.org/10.3762/bjnano.8.150.

Testo completo

Abstract (sommario):

We report light-induced negative organic magnetoresistance (OMAR) measured in ambient atmosphere in solution-processed 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene) planar hybrid devices with two different device architectures. Hybrid electronic devices with trench-isolated electrodes (HED-TIE) having a channel length of ca. 100 nm fabricated in this work and, for comparison, commercially available pre-structured organic field-effect transistor (OFET) substrates with a channel length of 20 µm were used. The magnitude of the photocurrent as well as the magnetoresistance was found to be higher for the HED-TIE devices because of the much smaller channel length of these devices compared to the OFETs. We attribute the observed light-induced negative magnetoresistance in TIPS-pentacene to the presence of electron–hole pairs under illumination as the magnetoresistive effect scales with the photocurrent. The magnetoresistance effect was found to diminish over time under ambient conditions compared to a freshly prepared sample. We propose that the much faster degradation of the magnetoresistance effect as compared to the photocurrent was due to the incorporation of water molecules in the TIPS-pentacene film.

Gli stili APA, Harvard, Vancouver, ISO e altri

50

van der Elst, Louis, Camila Faccini de Lima, Meve Gokce Kurtoglu, Veda Narayana Koraganji, Mengxin Zheng e Alexander Gumennik. "3D Printing in Fiber-Device Technology". Advanced Fiber Materials 3, n. 2 (8 febbraio 2021): 59–75. http://dx.doi.org/10.1007/s42765-020-00056-6.

Testo completo

Abstract (sommario):

Abstract Recent advances in additive manufacturing enable redesigning material morphology on nano-, micro-, and meso-scale, for achieving an enhanced functionality on the macro-scale. From non-planar and flexible electronic circuits, through biomechanically realistic surgical models, to shoe soles individualized for the user comfort, multiple scientific and technological areas undergo material-property redesign and enhancement enabled by 3D printing. Fiber-device technology is currently entering such a transformation. In this paper, we review the recent advances in adopting 3D printing for direct digital manufacturing of fiber preforms with complex cross-sectional architectures designed for the desired thermally drawn fiber-device functionality. Subsequently, taking a recursive manufacturing approach, such fibers can serve as a raw material for 3D printing, resulting in macroscopic objects with enhanced functionalities, from optoelectronic to bio-functional, imparted by the fiber-devices properties. Graphic abstract

Gli stili APA, Harvard, Vancouver, ISO e altri

Articoli di riviste sul tema "Planar device architecture"

Cita una fonte nei formati APA, MLA, Chicago, Harvard e in molti altri stili