Tesi: "Linear integrated circuits"

1

Devarayanadurg, Giri V. "Test selection and fault simulation for analog integrated circuits /". Thesis, Connect to this title online; UW restricted, 2001. http://hdl.handle.net/1773/6040.

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2

Zhang, Yue. "A fourth order current-mode sigma-delta modulator /". free to MU campus, to others for purchase, 1997. http://wwwlib.umi.com/cr/mo/fullcit?p9841350.

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3

Mantooth, Homer Alan. "Higher level modeling of analog integrated circuits". Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/14951.

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4

Bhattacharya, Sambuddha. "Template-driven parasitic-aware optimization of analog/RF IC layouts /". Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6121.

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5

Natarajan, Ekanathan Palamadai. "KLU--a high performance sparse linear solver for circuit simulation problems". [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0011721.

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6

Lui, Siu-hong. "Analog circuit design by nonconvex polynomial optimization two design examples /". Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39557418.

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7

Li, Harry W. "A noniterative DC analysis program for analog integrated circuits". Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/15977.

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8

Hum, Herbert Hing-Jing. "A linear unification processor /". Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63790.

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9

Jangkrajarng, Nuttorn. "Analog/RF VLSI layout generation : layout retargeting via symbolic template /". Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6084.

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10

Thomsen, Axel. "High speed high accuracy signal processing with parallel analog circuits". Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/13846.

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11

Baskaya, Ismail Faik. "Physical design automation for large scale field programmable analog arrays". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31810.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: David V Anderson; Committee Co-Chair: Sung Kyu Lim; Committee Member: Aaron Lanterman; Committee Member: Abhijit Chatterjee; Committee Member: Daniel Foty; Committee Member: Paul Hasler. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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12

Guimarães, Homero Luz. "Uma arquitetura de processamento paralelo para implementação de um trigger nível zero para instrumentação nuclear". [s.n.], 2013. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260880.

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Orientador: José Antonio Siqueira Dias
Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação
Made available in DSpace on 2018-08-22T02:05:02Z (GMT). No. of bitstreams: 1 Guimaraes_HomeroLuz_D.pdf: 8320554 bytes, checksum: cbec86ea8c9ee3ad275baa5f37860192 (MD5) Previous issue date: 2013
Resumo: Os experimentos em Física de alta energia tem se beneficiado enormemente do progresso alcançado na área de Microeletrônica, pois isto tem proporcionado a criação de detectores mais acurados e circuitos de processamento de sinais analógico/digitais cada vez mais rápidos e precisos. A redução no comprimento mínimo de canal dos processos CMOS além de proporcionar maior velocidade e precisão também reduz a área usada por cada canal, o que permite a implementação de mais canais numa mesma pastilha. Com um numero maior de canais por pastilha, com um mesmo numero de chips podemos programar um numero maior de canais do que anteriormente possível e com isso os físicos podem realizar uma reconstrução da trajetória de maneira mais precisa. Este Trabalho descreve uma proposta para o Trigger de nível zero baseando-se nas especificações disponíveis do Experimento Dzero no Fermi National Accelerator Laboraty (FERMILAB). Este trabalho descreve o projeto e implementação de um front-end analógico que detecta a carga provida pelo VLPC (detector luminoso usado no Dzero) seguida por um comparador de alta velocidade que fornece um nível lógico para um processador digital. O processador digital por sua vez usa uma arquitetura de processadores paralelos que, comunicando-se entre si são capazes de estimar a trajetória de partículas baseando-se em dados inicias programados a partir de simulações do detector feitas em computadores pelos Físicos. Tanto o bloco analógico quanto o processador digital foram implementados usando-se o processo CMOS90 da IBM
Abstract: The experiments in high-energy physics has benefited greatly from the progress made in the area of Microelectronics, since it has provided the creation of more accurate detectors and analog / digital signal processing circuits that are increasingly fast and accurate. The reduction in the minimum length of the channel in modern CMOS processes while providing greater speed and precision also reduces the area used by each channel, which enables the implementation of more channels on the same chip. With a larger number of channels per chip, we can with the same number of chips implement a larger number of channels than previously possible and with that physicists can perform a reconstruction of the trajectory more accurately. This work describes a proposal for a Trigger level zero based on the available specifications of the DZero experiment at the Fermi National Accelerator Laboraty (FERMILAB). In the following pages the design and implementation of an analog front-end that detects the charge provided by the VLPC detector followed by a high-speed comparator that provides a logical level to a digital processor are described. The digital processor in turn uses an architecture of parallel processors that communicate with each other are able in order to estimate the trajectory of particles based on initial data loaded in RAM based on simulations of the detector geometry made by physicists. Both the analog block and the digital processor are implemented using the IBM CMOS90 process
Doutorado
Eletrônica, Microeletrônica e Optoeletrônica
Doutor em Engenharia Elétrica

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13

Bridges, Seth. "Low-power visual pattern classification in analog VLSI /". Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6984.

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14

Lui, Siu-hong, e 呂小康. "Analog circuit design by nonconvex polynomial optimization: two design examples". Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39557418.

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15

Shana'a, Osama K. "Circuit Implementation of a High-speed Continuous-time Current-mode Field Programmable Analog Array (FPAA)". PDXScholar, 1996. https://pdxscholar.library.pdx.edu/open_access_etds/5103.

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The growing interest in programmable analog circuits has led to the development of Field Programmable Analog Arrays (FPAAs). An FPAA consists of: 1) a programmable cell that can be reconfigured to perform several analog functions. 2) an architecture that interconnects a number of copies of the programmable cell. In this thesis, the full monolithic circuit implementation of the analog part of the programmable cell is presented. Chapter I gives an introduction to the idea of FPAA and introduces the FPAA architecture and the cell block diagram. Chapter II deals with the design and verification of a differential current-mode four-quadrant multiplier. The weighting-summing circuit with the normalizing stage is discussed in Chapter III. Chapter IV presents the design of a current-mode low-voltage programmable integratorgain circuit. Programmability was achieved by changing the bias current in the designed circuits; no analog switches were used in the signal path. This shows no effect on the performance of the circuits. The presented programming method, however, relies on the availability of a programmable current source with a storage capability. The design of this current source is discussed in chapter V. Conclusions are summarized in Chapter VI. The presented designs throughout the whole thesis were supported by detailed analytical derivations with the necessary SPICE simulations to verify the performance.

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16

CARLSON, GERRARD MERRILL. "THE QUALITY OF SYNTHESIZED SPEECH USING LINEAR PREDICTIVE CODING ON FINITE WORDLENGTH INTEGRATED CIRCUITS". Diss., The University of Arizona, 1985. http://hdl.handle.net/10150/188024.

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This paper studies the quality of synthetic speech produced by integrated circuit (IC) hardware using fixed-point arithmetic and Linear Predictive Coding (LPC). A theoretical model explaining the combined effects of finite wordlength and parametric model order is developed. This model is used to predict the results obtained in the experimental phase of this study. In the experimental phase, selected model utterances are synthesized under finite wordlength constraints using LPC parameters. The synthetic speech is evaluated in terms of the log area ratios which define objective speech quality as a parametric distance. A theoretical model is developed to predict the experimental results. Simulations of this model produce data that predict the experimental results. The same information is extracted from the model as that obtained from actually running the fixed-point synthesizer simulator. Since the predictions of the theoretical model agree quite well with the experimental measurements, it is concluded that fixed-point synthesizer performance can be predicted without actually running a complicated and expensive fixed-point synthesizer. Secondly, results obtained from either method clearly indicate that for 15 or 16 bits, ten is the best number of poles to use. Eight useable poles are indicated for 14 bits, while seven are indicated for 13 bits. Based on the results of this study, the use of less than 13 bits for fixed-point calculations is not recommended.

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17

Zhang, Mingyang 1981. "Macromodeling and simulation of linear components characterized by measured parameters". Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=112589.

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Recently, microelectronics designs have reached extremely high operating frequencies as well as very small die and package sizes. This has made signal integrity an important bottleneck in the design process, and resulted in the inclusion of signal integrity simulation in the computer aided design flow. However, such simulations are often difficult because in many cases it is impossible to derive analytical models for certain passive elements, and the only available data are frequency-domain measurements or full-wave simulations. Furthermore, at such high frequencies these components are distributed in nature and require a large number of poles to be properly characterized. Simple lumped equivalent circuits are therefore difficult to obtain, and more systematic approaches are required. In this thesis we study the Vector Fitting techniques for obtaining such equivalent model and propose a more streamlined approach for preserving passivity while maintaining accuracy.

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18

Manney, Sanjay (Sanjay Leela) Carleton University Dissertation Engineering Electrical. "Transient analysis of nonuniform high-speed interconnects". Ottawa, 1992.

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19

Schaeffer, Ben. "Synthesis of Linear Reversible Circuits and EXOR-AND-based Circuits for Incompletely Specified Multi-Output Functions". PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3783.

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At this time the synthesis of reversible circuits for quantum computing is an active area of research. In the most restrictive quantum computing models there are no ancilla lines and the quantum cost, or latency, of performing a reversible form of the AND gate, or Toffoli gate, increases exponentially with the number of input variables. In contrast, the quantum cost of performing any combination of reversible EXOR gates, or CNOT gates, on n input variables requires at most O(n2/log2n) gates. It was under these conditions that EXOR-AND-EXOR, or EPOE, synthesis was developed. In this work, the GF(2) logic theory used in EPOE is expanded and the concept of an EXOR-AND product transform is introduced. Because of the generality of this logic theory, it is adapted to EXOR-AND-OR, or SPOE, synthesis. Three heuristic spectral logic synthesis algorithms are introduced, implemented in a program called XAX, and compared with previous work in classical logic circuits of up to 26 inputs. Three linear reversible circuit methods are also introduced and compared with previous work in linear reversible logic circuits of up to 100 inputs.

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20

Schaeffer, Ben. "Computer Aided Design of Permutation, Linear, and Affine-Linear Reversible Circuits in the General and Linear Nearest-Neighbor Models". Thesis, Portland State University, 2013. http://pqdtopen.proquest.com/#viewpdf?dispub=1541050.

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With the probable end of Moore's Law in the near future, and with advances in nanotechnology, new forms of computing are likely to become available. Reversible computing is one of these possible future technologies, and it employs reversible circuits. Reversible circuits in a classical form have the potential for lower power consumption than existing technology, and in a quantum form permit new types of encryption and computation.

One fundamental challenge in synthesizing the most general type of reversible circuit is that the storage space for fully specifying input-output descriptions becomes exponentially large as the number of inputs increases linearly. Certain restricted classes of reversible circuits, namely affine-linear, linear, and permutation circuits, have much more compact representations. The synthesis methods which operate on these restricted classes of reversible circuits are capable of synthesizing circuits with hundreds of inputs. In this thesis new types of synthesis methods are introduced for affine-linear, linear, and permutation circuits, as well as a synthesizable HDL design for a scalable, systolic processor for linear reversible circuit synthesis.

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21

Digvadekar, Ashish A. "A sub 1 V bandgap reference circuit /". Online version of thesis, 2005. https://ritdml.rit.edu/dspace/handle/1850/2595.

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22

Murty, Anjali. "Highly linear, rail-to-rail ICMR, low voltage CMOS operational amplifer". Thesis, Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/14884.

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23

Petre, Csaba. "Sim2spice a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits /". Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31820.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: Paul Hasler; Committee Member: Christopher Rozell; Committee Member: David Anderson. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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24

Subramanian, Shyam. "Methods for synthesis of multiple-input translinear element networks". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22591.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008.
Committee Chair: Anderson, David; Committee Member: Habetler, Thomas; Committee Member: Hasler, Paul; Committee Member: McClellan, James; Committee Member: Minch, Bradley.

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25

Wu, Pan. "The Design of High-Frequency Continuous-Time Integrated Analog Signal Processing Circuits". PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/1162.

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High-performance, high-frequency operational transconductance amplifiers (OTAs) are very important elements in the design of high-frequency continuous-time integrated analog signal processing circuits, because resistors, inductors, integrators, mutators, buffers, multipliers, and filters can be built by OTAs and capacitors. The critical considerations for OTA design are linearity, tuning, frequency response, output impedance, power supply rejection (PSR) and common-mode rejection (CMR). For linearity considerations, two different methods are proposed. One uses cross-coupled pairs (CMOS or NMOS), producing OTAs with very high linearity but either the input range is relatively small or the CMR to asymmetrical inputs is poor. Another employs multiple differential pairs (current addition or subtraction), producing OTAs with high linearity over a very large input range. So, there are tradeoffs among the critical considerations. For different applications, different OTAs should be selected. For consideration of frequency response, the first reported GaAs OTA was designed for achieving very-high-frequency performance, instead of using AC compensation techniques. GaAs is one of the fastest available technologies, but it was new and less mature than silicon when we started the design in 1989. So, there were several issues, such as low output impedance, no P-channel devices, and Schottky clamp. To overcome these problems, new techniques are proposed, and the designed OTA has comparable performance to a CMOS OTA. For PSR and CMR considerations, a fully balanced circuit structure is employed with a common-mode feedback (CMF) circuit used to stabilize the DC output voltages. To reduce the interaction of the operation of CMF and tuning of OTAs, three improved versions of the CMF circuits used in operational amplifiers are proposed. With the designed OTAs, a I GHz GaAs inductor with small parasitics is designed using the proposed procedure to reduce high-frequency effects. Two CMOS high-order, high-frequency filters are designed: one in cascade structure and one in LC ladder form. Also, a 200 MHz third-order elliptic GaAs filter is designed with special consideration of very-high-frequency parasitics. All circuits were fabricated and measured. The experimental results were used to verify the designs.

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26

Chan, kwong Fu. "Large-signal characterization/modeling and linearization techniques for RF power amplifiers /". View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20CHANK.

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27

Liu, Zhi-Hong. "Mixed-signal testing of integrated analog circuits and modules". Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1181174339.

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28

Asibal, Romeo Lim. "Limitations of high speed sigma-delta A/D converter in GaAs technology". Diss., Georgia Institute of Technology, 1991. http://hdl.handle.net/1853/15445.

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29

Zhang, Zheng, e 张政. "Passivity assessment and model order reduction for linear time-invariant descriptor systems in VLSI circuit simulation". Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2010. http://hub.hku.hk/bib/B44909056.

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The Best MPhil Thesis in the Faculties of Dentistry, Engineering, Medicine and Science (University of Hong Kong), Li Ka Shing Prize,2009-2010
published_or_final_version
Electrical and Electronic Engineering
Master
Master of Philosophy

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30

Ko, Yus. "Design and optimization of 5GHz CMOS power amplifiers with the differential load-pull techniques". [Gainesville, Fla.] : University of Florida, 2005. http://purl.fcla.edu/fcla/etd/UFE0013036.

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31

Lo, Ernest Sze-Yuen. "Differential OFDM with iterative detection and signal space diversity for broadband wireless communication /". View Abstract or Full-Text, 2002. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202002%20LO.

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Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002.
Includes bibliographical references (leaves 67-69). Also available in electronic version. Access restricted to campus users.

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32

Twigg, Christopher M. "Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing". Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11601.

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Large-scale reconfigurable and programmable analog devices provide a new option for prototyping and synthesizing analog circuits for analog signal processing and beyond. Field-programmable analog arrays (FPAAs) built upon floating gate transistor technologies provide the analog reconfigurability and programmability density required for large-scale devices on a single integrated circuit (IC). A wide variety of synthesized circuits, such as OTA followers, band-pass filters, and capacitively coupled summation/difference circuits, were measured to demonstrate the flexibility of FPAAs. Three generations of devices were designed and tested to verify the viability of such floating gate based large-scale FPAAs. Various architectures and circuit topologies were also designed and tested to explore the trade-offs present in reconfigurable analog systems. In addition, large-scale FPAAs have been incorporated into class laboratory exercises, which provide students with a much broader range of circuit and IC design experiences than have been previously possible. By combining reconfigurable analog technologies with an equivalent large-scale digital device, such as a field-programmable gate array (FPGA), an extremely powerful and flexible mixed signal development system can be produced that will enable all of the benefits possible through cooperative analog/digital signal processing (CADSP).

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33

Grover, Samir. "Solving layout compaction and wire-balancing problem using linear programming on the Monsoon multiprocessor". Thesis, Connect to online version, 1995. http://0-wwwlib.umi.com.mercury.concordia.ca/cr/concordia/fullcit?pMQ90885.

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34

Yu, Chi Sun. "Effectiveness of parallel diode linearizers on bipolar junction transistor and its use in dynamic linearization /". access full-text access abstract and table of contents, 2009. http://libweb.cityu.edu.hk/cgi-bin/ezdb/thesis.pl?phd-ee-b23749362f.pdf.

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Thesis (Ph.D.)--City University of Hong Kong, 2009.
"Submitted to Department of Electronic Engineering in partial fulfillment of the requirements for the degree of Doctor of Philosophy." Includes bibliographical references (leaves 129-134)

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35

Xiong, Zhijie. "Radio Frequency Low Noise and High Q Integrated Filters in Digital CMOS Processes". Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5043.

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Radio Frequency Low Noise and High Q Integrated Filters in Digital CMOS Processes Zhijie Xiong 149 pages Directed by Dr. Phillip E. Allen Presented in this work is a novel design technique for CMOS integration of RF high Q integrated filters using positive feedback and current mode approach. Two circuits are designed in this work: a 100MHz low-noise and high Q bandpass filter suited for an FM radio front-end, and a 2.4GHz low-noise and high-Q bandpass filter suited for a Bluetooth front-end. Current-mode approach and positive feedback design techniques are successfully used in the design of both circuits. Both circuits are fabricated through a 0.18um CMOS process provided by National Semiconductor Corp. The 100MHz circuit achieves 3.15uV RF sensitivity with 26dB SNR, and the total current consumption is 12mA. The center frequency of the filter is tunable from 80MHz to 110MHz, and the Q value is tunable from 0.5 to 28.9. 1 dB compression point is measured as -34.0dBm, combined with noise measurement results, a dynamic range of 54.1 dB results. Silicon area of the core circuit is 0.4 square millimeters. The center frequency of the 2.4GHz circuit is tunable from 2.4GHz to 2.5GHz, and the Q value is tunable from 20 to 120. The 1 dB compression dynamic range of the circuit is 50dB. Integrated spiral inductors are developed for this design. Patterned ground shields are laid out to reduce inductor loss through substrate, especially eddy current loss when the circuit is fabricated on epi wafers. Accumulation mode MOS varactors are designed to tune the frequency response. Silicon area of the core circuit is 1 square millimeter.

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Omer, Mohammad. "Towards harmonious coexistence : linear and nonlinear techniques for interference management in RFICs". Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/51938.

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This thesis has sought to provide another look at RF interference at the fundamental level. While previous interference control and regulation methods have existed in the literature, they were more focused on preventing the interference from happening. On the contrary, we have taken a different approach of correcting the interference once it has happened. This allows the transmitters to be more nonlinear, passive filter design to be eased, and receivers to be aware of interference problems. Under this unifying theme of building intelligent radios where receivers are more cognizant of the transmission environment, we have presented a number of architectures.

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37

U, Seng-Pan. "Tecnicas de interpolacao em filtros multiritmo com condensadores comutados para Interfaces Analogicas com filtragem de alta-frequencia = Multirate Switched-Capacitor interpolation techniques for very high-frequency Analog Front-End filtering". Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1873496.

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38

Qureshi, Muhammad Shakeel. "Integrated front-end analog circuits for mems sensors in ultrasound imaging and optical grating based microphone". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29613.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Hasler, Paul; Committee Co-Chair: Degertekin, Levent; Committee Member: Anderson, David; Committee Member: Ayazi, Farrokh; Committee Member: Brand, Oliver; Committee Member: Hesketh, Peter. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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Park, Yunseo. "Direct Conversion RF Front-End Implementation for Ultra-Wideband (UWB) and GSM/WCDMA Dual-Band Applications in Silicon-Based Technologies". Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7563.

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This dissertation focuses on wideband circuit design and implementation issues up to 10GHz based on the direct conversion architecture in the CMOS and SiGe BiCMOS technologies. The dissertation consists of two parts: One, implementation of a RF front-end receiver for an ultra-wideband system and, two, implementation of a local oscillation (LO) signal for a GSM/WCDMA multiband application. For emerging ultra-wideband (UWB) applications, the key active components in the RF front-end receiver were designed and implemented in 0.18um SiGe BiCMOS process. The design of LNA, which is the critical circuit block for both systems, was analyzed in terms of noise, linearity and group delay variation over an extemely wide bandwidth. Measurements are demonstrated for an energy-thrifty UWB receiver based on an MB-OFDM system covering the full FCC-allowed UWB frequency range. For multiband applications such as a GSM/WCDMA dual-band application, the design of wideband VCO and various frequency generation blocks are investigated as alternatives for implementation of direct conversion architecture. In order to reduce DC-offset and LO pulling phenomena that degrade performance in a typical direct conversion scheme, an innovative fractional LO signal generator was implemented in a standard CMOS process. A simple analysis is provided for the loop dynamics and operating range of the design as well as for the measured results of the factional LO signal generator.

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40

Killens, Jacob. "Utilizing standard CMOS process floating gate devices for analog design". Master's thesis, Mississippi State : Mississippi State University, 2001. http://library.msstate.edu/etd/show.asp?etd=etd-04092001-110957.

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41

Belkadi, Djilali. "Contribution à la modélisation et à la simulation des circuits intégrés analogiques : application aux systèmes échantillonnés et aux circuits linéaires de haute fréquence". Grenoble INPG, 1997. http://www.theses.fr/1997INPG0062.

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Ce travail est une contribution a la modelisation et la simulation temporelle des circuits integres analogiques. Suite au besoin de la conception descendante et aux limites de la simulation electrique, la conception sur differents niveaux d'abstraction est devenue necessaire. Puisque les circuits integres analogiques sont divers, nous en avons choisi deux types : les systemes echantillonnes et les circuits lineaires de haute frequence. Dans le premier genre, une methode de simulation est proposee. Elle est basee sur la linearisation du circuit par phase d'horloge et la resolution analytique des equations differentielles. La nouveaute qu'elle porte est de rendre la simulation transitoire du bruit physique possible en utilisant la notion du bruit gele. Quant aux circuits lineaires de haute frequence, une nouvelle methode appelee cifft est proposee afin de calculer une reponse impulsionnelle causale a partir des donnees frequentielles tabulees. En concretisation de ce travail, nous avons developpe deux modules delta sigma design kit et s-model (integre dans le simulateur eldo) pour la simulation transitoire des modulateurs - de type mash et les circuits definis par des donnees frequentielles tabulees.

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42

Sengupta, Susanta. "Technology-independent CMOS op amp in minimum channel length". Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07092004-101204/unrestricted/sengupta%5Fsusanta%5F200407%5Fphd.pdf.

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Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by Phillip Allen.
Morley, Thomas, Committee Member ; Leach, Marshall, Committee Member ; Ayazi, Farrokh, Committee Member ; Rincon-Mora, Gabriel, Committee Member ; Allen, Phillip, Committee Chair. Includes bibliographical references.

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Srirattana, Nuttapong. "High-Efficiency Linear RF Power Amplifiers Development". Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6899.

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Next generation mobile communication systems require the use of linear RF power amplifier for higher data transmission rates. However, linear RF power amplifiers are inherently inefficient and usually require additional circuits or further system adjustments for better efficiency. This dissertation focuses on the development of new efficiency enhancement schemes for linear RF power amplifiers. The multistage Doherty amplifier technique is proposed to improve the performance of linear RF power amplifiers operated in a low power level. This technique advances the original Doherty amplifier scheme by improving the efficiency at much lower power level. The proposed technique is supported by a new approach in device periphery calculation to reduce AM/AM distortion and a further improvement of linearity by the bias adaptation concept. The device periphery adjustment technique for efficiency enhancement of power amplifier integrated circuits is also proposed in this work. The concept is clearly explained together with its implementation on CMOS and SiGe RF power amplifier designs. Furthermore, linearity improvement technique using the cancellation of nonlinear terms is proposed for the CMOS power amplifier in combination with the efficiency enhancement technique. In addition to the efficiency enhancement of power amplifiers, a scalable large-signal MOSFET model using the modified BSIM3v3 approach is proposed. A new scalable substrate network model is developed to enhance the accuracy of the BSIM3v3 model in RF and microwave applications. The proposed model simplifies the modeling of substrate coupling effects in MOS transistor and provides great accuracy in both small-signal and large-signal performances.

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Gray, Jordan D. "Large scale reconfigurable analog system design enabled through floating-gate transistors". Diss., Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/34660.

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This work is concerned with the implementation and implication of non-volatile charge storage on VLSI system design. To that end, the floating-gate pFET (fg-pFET) is considered in the context of large-scale arrays. The programming of the element in an efficient and predictable way is essential to the implementation of these systems, and is thus explored. The overhead of the control circuitry for the fg-pFET, a key scalability issue, is examined. A light-weight, trend-accurate model is absolutely necessary for VLSI system design and simulation, and is also provided. Finally, several reconfigurable and reprogrammable systems that were built are discussed.

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Wei, He Gong. "High speed power/area optimized multi-bit/cycle SAR ADCs". Thesis, University of Macau, 2011. http://umaclib3.umac.mo/record=b2489844.

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46

Voigtmann, Steffen. "General linear methods for integrated circuit design". Doctoral thesis, Berlin Logos-Verl, 2006. http://deposit.d-nb.de/cgi-bin/dokserv?id=2850248&prov=M&dok_var=1&dok_ext=htm.

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47

Evans, Peter Sidney Albert. "Transient response testing of linear components within mixed-signal systems". Thesis, University of Huddersfield, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239743.

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Coimbra, Ricardo Pureza. "Geração de tensão de referencia e sinal de sensoriamento termico usando transistores MOS em forte inversão". [s.n.], 2009. http://repositorio.unicamp.br/jspui/handle/REPOSIP/262029.

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Orientador: Carlos Alberto dos Reis Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-14T00:43:32Z (GMT). No. of bitstreams: 1 Coimbra_RicardoPureza_M.pdf: 4991793 bytes, checksum: 2b5fb9293ae9abe4c248964485ff74e3 (MD5) Previous issue date: 2009
Resumo: Fontes de referência de tensão e sensores de temperatura são blocos extensivamente utilizados em sistemas microeletrônicos. Como alternativa à aplicação de estruturas consolidadas, mas protegidas por acordos de propriedade intelectual, é permanente a demanda pelo desenvolvimento de novas técnicas e estruturas originais destes circuitos. Também se destaca o crescente interesse por soluções de baixa tensão, baixo consumo e compatíveis com processos convencionais de fabricação. Este trabalho descreve o desenvolvimento de um circuito que atende a estas exigências, fornecendo uma tensão de referência e um sinal de sensoriamento térmico, obtidos a partir de um arranjo adequado de transistores MOS, que operam em regime de forte inversão. O princípio de operação do circuito desenvolvido foi inspirado no conceito de que é possível empilhar n transistores MOS, polarizados com corrente adequada, de tal forma que a queda de tensão sobre a pilha de transistores, com amplitude nVGS, apresente a mesma taxa de variação térmica que a tensão VGS produzida por um único transistor. Nesta condição, a diferença entre as duas tensões é constante em temperatura, constituindo-se em uma referência de tensão. No entanto, o empilhamento de dois ou mais transistores impossibilita a operação do circuito sob baixa tensão. Isto motivou a adaptação da técnica, obtendo a tensão nVGS com o auxílio de um arranjo de resistores, sem o empilhamento de transistores. Desta forma, o potencial limitante da tensão mínima de alimentação tornou-se a própria tensão de referência, cuja amplitude é próxima de um único VGS. A estrutura desenvolvida fornece também um sinal de tensão com dependência aproximadamente linear com a temperatura absoluta, que pode ser aplicado para sensoriamento térmico. Foram fabricados protótipos correspondentes a diversas versões de dimensionamento do circuito para comprovação experimental de seu princípio de operação. O melhor desempenho verificado corresponde à geração de uma tensão de referência com coeficiente térmico de 8,7ppm/ºC, no intervalo de -40ºC a 120ºC, operando com tensão de 1V. Embora o estado da arte seja representado por índices tão baixos quanto 1ppm/ºC, para a mesma faixa de temperatura, a característica compacta do circuito e seu potencial de aplicação sob as condições de baixa tensão e baixo consumo lhe conferem valor como contribuição para este campo de pesquisa e desenvolvimento.
Abstract: Voltage references and temperature sensors are blocks extensively used in microelectronic systems. As an alternative to the use of consolidated structures that are protected by intellectual property agreements, there is a permanent demand for the development of new techniques and structures for these circuits. It can be also highlighted the growing interest for low-voltage and low-power solutions, implemented in conventional IC technologies. This work describes the development of a circuit that meets these requirements by providing a voltage reference and temperature sensing signal obtained from a suitable arrangement of MOS transistors biased in strong inversion. The operation principle of the circuit developed is based on the concept that it is possible for a stack of n MOS transistors, biased by an appropriate current, to show a voltage drop, equal to nVGS, with the same thermal variation rate as a VGS voltage produced by a single transistor. Hence, the difference between the two voltage signals is temperature independent, characterizing a voltage reference. However, the stacking of two or more transistors prevents the operation of the circuit under low voltage. This fact motivated to adapt the technique by obtaining the voltage nVGS with the aid of an array of resistors and no stacked transistors. The minimum supply voltage becomes limited only by the reference voltage itself, whose amplitude is close to a single VGS. The circuit developed also provides a voltage signal almost linearly dependent with the absolute temperature, which can be applied for thermal sensing. Prototypes corresponding to various dimensional versions of the circuit were produced to experimentally verify the principle of operation. The best performance corresponds to the generation of a voltage reference signal with 8.7ppm/ºC thermal coefficient, from -40ºC to 120ºC, under a 1V supply voltage. Although the state of the art is represented by values as low as 1ppm/ºC, at the same temperature range, the circuit's compact aspect together with the possibility to attend low-voltage and low-power requirements grants it value as contribution to this field of research and development
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica

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49

Khoshniat, Ali. "A Linearly and Circularly Polarized Active Integrated Antenna". DigitalCommons@USU, 2011. https://digitalcommons.usu.edu/etd/881.

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This thesis work presents a new harmonic suppression technique for microstrip patch antennas. Harmonic suppression in active integrated antennas is known as an effective method to improve the efficiency of amplifiers in transmitter side. In the proposed design, the antenna works as the radiating element and, at the same time, as the tuning load for the amplifier circuit that is directly matched to the antenna. The proposed active antenna architecture is easy to fabricate and is symmetric, so it can be conveniently mass-produced and designed to have circular polarization, which is preferred in many applications such as satellite communications. The antenna simulations were performed using Ansoft High Frequency System Simulator (HFSS) and all amplifier design steps were simulated by Advanced Design System (ADS). The final prototypes of the linearly polarized active integrated antenna and the circularly polarized active integrated antenna were fabricated using a circuit board milling machine. The antenna radiation pattern was measured inside Utah State University's anechoic chamber and the results were satisfactory. Power measurements for the amplifiers' performance were carried out inside the chamber and calculated by using the Friis transmission equation. It is seen that a significant improvement in the efficiency is achieved compared to the reference antenna without harmonic suppression. Based on the success in the single element active antenna design, the thesis also presents a feasibility of applying the active integrated antenna in array configuration, in particular, in scanning array design to yield a low-profile, low-cost alternative to the parabolic antenna transmitter of satellite communication systems.

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Guimarães, Gabriel Teófilo Neves. "CMOS linear RF power amplifier with fully integrated power combining transformer". reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/169084.

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Este trabalho apresenta o projeto de um amplificador de potência (PA) de rádio-frequência (RF) linear em tecnologia complementar metal-oxido silício (CMOS). Nele são analisados os desafios encontrados no projeto de PAs CMOS assim como soluções encontradas no estado-da-arte. Um destes desafios apresentados pela tecnologia é a baixa tensão de alimentação e passivos com alta perda, o que limita a potência de saída e a eficiência possível de ser atingida com métodos tradicionais de projeto de PA e suas redes de transformação de impedância. Este problema é solucionado através do uso de redes de combinação de impedância integradas, como a usada neste trabalho chamada transformador combinador em série (SCT). Os problemas com o uso de tecnologia CMOS se tornam ainda mais críticos para padrões de comunicação que requerem alta linearidade como os usados para redes sem-fio locais (WLAN) ou padrões de telefonia móvel 3G e 4G. Tais protocolos requerem que o PA opere em uma potência menor do que seu ponto de operação ótimo, degradando sua eficiência. Técnicas de linearização como pré-distorção digital são usadas para aumentar a potência média transmitida. Uma ténica analógica de compensação de distorção AM-PM através da linearização da capacitância de porta dos transistores é usada neste trabalho. O processo de projeto é detalhado e evidencia as relações de compromisso em cada passo, particularmente o impacto da terminação de harmônicos e a qualidade dos passivos na rede de transformação de carga. O projeto do SCT é otimizado para sintonia da impedância de modo comum que é usada para terminar o segundo harmonico de tensão do amplificador. O amplificador projetado tem um único estágio devido a área do chip ser limitada a 1:57 x 1:57 mm2, fato que impacta seu desempenho. O PA foi analisado através de simulação numérica sob várias métricas. Ele atinge uma potência máxima de saída de 24:4 dBm com uma eficiência de dreno de 24:53% e Eficiência em adição de potência (PAE) de 22%. O PA possui uma curva de ganho plana em toda faixa ISM de 2.4 GHz, com magnitude de 15:8 0:1dB. O PA tem um ponto de compressão de OP1dB = 20:03 dBm e o sinal tem um defasamento não-linear de = 1:2o até esta potência de saída. Um teste de intermodulação de dois tons com potência 3dB abaixo do OP1dB tem como resultado uma relação entre intermodulação de terceira ordem e fundamental de IMD3 = 24:22 dB, e de quinta ordem inferior e superior e fundamental de IMD5Inferior = 48:16 dB e IMD5Superior = 49:8 dB. Por fim, mostra-se que o PA satisfaz os requerimentos para operar no padrão IEEE 802.11g. Ele atinge uma potência média de saída de 15:4 dBm apresentando uma magnitude do vetor erro (EVM) de 5:43%, ou 25:3 dB e satisfazendo a máscara de saída para todos os canais.
This work presents the design of a fully integrated Radio-frequency (RF) linear Power Amplifier( PA) in complementary metal-oxide silicon (CMOS) technology. In this work we analyse the challenges in CMOS PA design as well as the state-of-the-art solutions. One such challenge presented by this technology is the low supply voltage and high-loss passives, which pose severe limits on the output power and efficiency achieved with traditional PA design methods and load impedance transformation networks. This issue is addressed by the use of on-chip, highly efficient power combining networks such as the one in this work: A series combining transformer (SCT). The problem of using CMOS becomes even more critical for recent communications standards that require high transmitter linearity such as the ones used for wireless local area network (WLAN) or 3G and 4G mobile communications. This requirement is such that the PA operate at a high power back-off from its optimum operating point, degrading efficiency. To address this problem linearization techniques such as digital pre-distortion can be used in order to decrease the necessary power back-off. In this work an analog technique of AM-PM distortion compensation is used to linearize the capacitance at the input of the amplifier’s transistors and reduce this type of distortion that severely impacts the error vector magnitude (EVM) of the signal. The design process is detailed and aims to make evident the trade-offs of PA design and particularly the impact of harmonic termination and the quality of passives on the load transformation network, the series combining transformer design is optimized for common-mode impedance tuning used for 2nd harmonic termination. The circuit has only a single amplifying stage due to its area being limited to 1:57 x 1:57 mm2 and the design is very constrained by this fact. The PA simulated performance is analyzed under various metrics. It achieves a simulated maximum output power of 24:4 dBm with a drain efficiency of 24:53% and power added efficiency (PAE) of 22%. The PA has a very flat power gain of 15:8 0:1 dB throughout the 2.4 GHz industrial, scientific and medical (ISM) band and is unconditionally stable with 4:9. The PA has a compression point of OP1dB = 20:03 dBm and the signal has a non-linear phase shift of = 1:2o up to this output power. A two-tone intermodulation test with 3dB back-off from OP1dB has a ratio of third-order intermodulation to fundamental of IMD3 = 24:22 dB, and lower and upper fifth order intermodulation to fundamental of IMD5Lower = 48:16 dB and IMD5Upper = 49:8 dB. Finally the PA is shown to satisfy the requirements for operation within the institute of electrical and electronic engineers (IEEE) 802.11g standard. It achieves an average output power of 15:4 dBm while having an EVM of 5:43% or 25:3 dB while satisfying the output spectrum mask for all channels.

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