Tesi sul tema "Integrated circuits Very large scale integration Design and construction Data processing"

An implementation of an interactive design rule checker is described in this thesis. Corner-based design rule checking algorithm is used for the implementation. Due to the locality of checking mechanism of the corner-based algorithm, it is suitable for hierarchical and interactive local design rule checking. It also allows the various design rules to be specified very easily. Interactive operations are devised so that the design rule checker can be invoked from inside the layout editor. All the information about the violation, such as position, type of violation, and symbol definition name are provided in an interactive manner. In order to give full freedom to the user to choose the scope of checking, three options, "Flattening", "Unflattening" and "User-defined window" are implemented in creating the database to be checked. The "User-defined window" option allows hierarchical design rule checking on a design which contains global rectangles. Using these three options, very efficient hierarchical checking can be performed.<br>Master of Science<br>incomplete_metadata

BIDES (A BIST Design Expert System) is an expert system for incorporating BIST into a digital circuit described with VHDL. BIDES modifies a circuit to produce a self-testable circuit by inserting BIST hardware such as pseudorandom pattern generators and signature analysis registers. In inserting BIST hardware, BIDES not only makes a circuit self-testable, but also incorporates the appropriate type of BIST structure so that a set of user-specified constraints on hardware overhead and testing time can be satisfied. This flexibility comes from the formulation of the BIST design problem as a search problem. A satisfactory BIST structure is explored through an iterative process of evaluation and regeneration of BIST structure. The process of regeneration is performed by a problem solving technique called hierarchical planning. In order to apply a hierarchical planning technique, we introduce an abstraction hierarchy in BIST design. Using the abstraction hierarchy, the knowledge of the BIST design process is represented with several operators defined on the abstraction levels. This type of knowledge representation in conjunction with hierarchical planning led to an easy implementation of the system and results in an easily modifiable system. In this dissertation, we also study a BIST scheme called cascade testing. ln cascade testing, a signature analysis register is used concurrently as a test pattern generator in order to reduce the overall testing time by improving testing parallelism. The characteristics of the patterns generated by the signature analysis register are investigated through analysis as well as experiments. lt is shown that the patterns generated by signature analysis registers are rarely repeated when the number of patterns generated is relatively small compared to the number of all possible patterns. It is also shown that the patterns generated by signature analysis registers are almost random. Therefore, signature analysis registers can be used effectively as pseudorandom pattern generators. The practicality of cascade testing is investigated by fault simulation experiments using an example circuit.<br>Ph. D.

Recently, microelectronics designs have reached extremely high operating frequencies as well as very small die and package sizes. This has made signal integrity an important bottleneck in the design process, and resulted in the inclusion of signal integrity simulation in the computer aided design flow. However, such simulations are often difficult because in many cases it is impossible to derive analytical models for certain passive elements, and the only available data are frequency-domain measurements or full-wave simulations. Furthermore, at such high frequencies these components are distributed in nature and require a large number of poles to be properly characterized. Simple lumped equivalent circuits are therefore difficult to obtain, and more systematic approaches are required. In this thesis we study the Vector Fitting techniques for obtaining such equivalent model and propose a more streamlined approach for preserving passivity while maintaining accuracy.

The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. One of the key challenges today is to select appropriate CAD or EDA tools which are open-source for academic purposes. This thesis provides a detailed examination of an open-source EDA tool called Electric VLSI Design system. An excellent and efficient CAD tool useful for students and teachers to implement ideas by modifying the source code, Electric fulfills these requirements. This thesis' primary objective is to explain the Electric software features and architecture and to provide various digital and analog designs that are implemented by this software for educational purposes. Since the choice of an EDA tool is based on the efficiency and functions that it can provide, this thesis explains all the analysis and synthesis tools that electric provides and how efficient they are. Hence, this thesis is of benefit for students and teachers that choose Electric as their open-source EDA tool for educational purposes.

Bibliography: leaves 233-259<br>xii, 259 leaves : ill ; 30 cm.<br>Title page, contents and abstract only. The complete thesis in print form is available from the University Library.<br>Thesis (Ph.D.)--University of Adelaide, 1991

由於特徵尺寸不斷縮小，集成電路在生產過程中的工藝偏差在運行環境中溫度和電壓等參數的波動以及在使用過程中的老化等效應越來越嚴重，導致芯片的時序行為出現很大的不確定性。多數情況下，芯片的關鍵路徑會不時出現時序錯誤。加入更多的時序餘量不是一種很好的解決方案，因為這種保守的設計方法會抵消工藝進步帶來的性能上的好處。這就為設計一個時序可靠的系統提出了極大的挑戰，其中的一些關鍵問題包括：(一)如何有效地分配有限的功率預算去優化那些正爆炸式增加的關鍵路徑的時序性能；(二)如何產生能夠捕捉準確的最壞情況時延的高品質測試向量；(三)為了能夠取得更好的功耗和性能上的平衡，我們將不得不允許芯片在使用過程中出現一些頻率很低的時序錯誤。隨之而來的問題是如何做到在線的檢錯和糾錯。<br>為了解決上述問題，我們首先發明了一種新的技術用於識別所謂的虛假路徑，該方法使我們能夠發現比傳統方法更多的虛假路徑。當將所提取的虛假路徑集成到靜態時序分析工具里以後，我們可以得到更為準確的時序分析結果，同時也能節省本來用於優化這些路徑的成本。接著，考慮到現有的延時自動向量生成(ATPG) 方法會產生功能模式下無法出現的測試向量，這種向量可能會造成測試過程中在被激活的路徑周圍出現過多(或過少)的電源噪聲(PSN) ，從而導致測試過度或者測試不足情況。為此，我們提出了一種新的偽功能ATPG工具。通過同時考慮功能約束以及電路的物理佈局信息，我們使用類似ATPG 的算法產生狀態跳變使其能最大化已激活的路徑周圍的PSN影響。最後，基於近似電路的原理，我們提出了一種新的在線原位校正技術，即InTimeFix，用於糾正時序錯誤。由於實現近似電路的綜合僅需要簡單的電路結構分析，因此該技術能夠很容易的擴展到大型電路設計上去。<br>With technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and aging effects. In most cases, these reliability threats manifest themselves as timing errors on speed-paths (i.e., critical or near-critical paths) of the circuit. Embedding a large design guard band to prevent timing errors to occur is not an attractive solution, since this conservative design methodology diminishes the benefit of technology scaling. This creates several challenges on build a reliable systems, and the key problems include (i) how to optimize circuit’s timing performance with limited power budget for explosively increased potential speed-paths; (ii) how to generate high quality delay test pattern to capture ICs’ accurate worst-case delay; (iii) to have better power and performance tradeoff, we have to accept some infrequent timing errors in circuit’s the usage phase. Therefore, the question is how to achieve online timing error resilience.<br>To address the above issues, we first develop a novel technique to identify so-called false paths, which facilitate us to find much more false paths than conventional methods. By integrating our identified false paths into static timing analysis tool, we are able to achieve more accurate timing information and also save the cost used to optimize false paths. Then, due to the fact that existing delay automated test pattern generation (ATPG) methods may generate test patterns that are functionally-unreachable, and such patterns may incur excessive (or limited) power supply noise (PSN) on sensitized paths in test mode, thus leading to over-testing or under-testing of the circuits, we propose a novel pseudo-functional ATPG tool. By taking both circuit layout information and functional constrains into account, we use ATPG like algorithm to justify transitions that pose the maximized functional PSN effects on sensitized critical paths. Finally, we propose a novel in-situ correction technique to mask timing errors, namely InTimeFix, by introducing redundant approximation circuit with more timing slack for speed-paths into the design. The synthesis of the approximation circuit relies on simple structural analysis of the original circuit, which is easily scalable to large IC designs.<br>Detailed summary in vernacular field only.<br>Detailed summary in vernacular field only.<br>Yuan, Feng.<br>Thesis (Ph.D.)--Chinese University of Hong Kong, 2012.<br>Includes bibliographical references (leaves 88-100).<br>Abstract also in Chinese.<br>Abstract --- p.i<br>Acknowledgement --- p.iv<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Challenges to Solve Timing Uncertainty Problem --- p.2<br>Chapter 1.2 --- Contributions and Thesis Outline --- p.5<br>Chapter 2 --- Background --- p.7<br>Chapter 2.1 --- Sources of Timing Uncertainty --- p.7<br>Chapter 2.1.1 --- Process Variation --- p.7<br>Chapter 2.1.2 --- Runtime Environment Fluctuation --- p.9<br>Chapter 2.1.3 --- Aging Effect --- p.10<br>Chapter 2.2 --- Technical Flow to Solve Timing Uncertainty Problem --- p.10<br>Chapter 2.3 --- False Path --- p.12<br>Chapter 2.3.1 --- Path Sensitization Criteria --- p.12<br>Chapter 2.3.2 --- False Path Aware Timing Analysis --- p.13<br>Chapter 2.4 --- Manufacturing Testing --- p.14<br>Chapter 2.4.1 --- Functional Testing vs. Structural Testing --- p.14<br>Chapter 2.4.2 --- Scan-Based DfT --- p.15<br>Chapter 2.4.3 --- Pseudo-Functional Testing --- p.17<br>Chapter 2.5 --- Timing Error Tolerance --- p.19<br>Chapter 2.5.1 --- Timing Error Detection --- p.19<br>Chapter 2.5.2 --- Timing Error Recover --- p.20<br>Chapter 3 --- Timing-Independent False Path Identification --- p.23<br>Chapter 3.1 --- Introduction --- p.23<br>Chapter 3.2 --- Preliminaries and Motivation --- p.26<br>Chapter 3.2.1 --- Motivation --- p.27<br>Chapter 3.3 --- False Path Examination Considering Illegal States --- p.28<br>Chapter 3.3.1 --- Path Sensitization Criterion --- p.28<br>Chapter 3.3.2 --- Path-Aware Illegal State Identification --- p.30<br>Chapter 3.3.3 --- Proposed Examination Procedure --- p.31<br>Chapter 3.4 --- False Path Identification --- p.32<br>Chapter 3.4.1 --- Overall Flow --- p.34<br>Chapter 3.4.2 --- Static Implication Learning --- p.35<br>Chapter 3.4.3 --- Suspicious Node Extraction --- p.36<br>Chapter 3.4.4 --- S-Frontier Propagation --- p.37<br>Chapter 3.5 --- Experimental Results --- p.38<br>Chapter 3.6 --- Conclusion and Future Work --- p.42<br>Chapter 4 --- PSN Aware Pseudo-Functional Delay Testing --- p.43<br>Chapter 4.1 --- Introduction --- p.43<br>Chapter 4.2 --- Preliminaries and Motivation --- p.45<br>Chapter 4.2.1 --- Motivation --- p.46<br>Chapter 4.3 --- Proposed Methodology --- p.48<br>Chapter 4.4 --- Maximizing PSN Effects under Functional Constraints --- p.50<br>Chapter 4.4.1 --- Pseudo-Functional Relevant Transitions Generation --- p.51<br>Chapter 4.5 --- Experimental Results --- p.59<br>Chapter 4.5.1 --- Experimental Setup --- p.59<br>Chapter 4.5.2 --- Results and Discussion --- p.60<br>Chapter 4.6 --- Conclusion --- p.64<br>Chapter 5 --- In-Situ Timing Error Masking in Logic Circuits --- p.65<br>Chapter 5.1 --- Introduction --- p.65<br>Chapter 5.2 --- Prior Work and Motivation --- p.67<br>Chapter 5.3 --- In-Situ Timing Error Masking with Approximate Logic --- p.69<br>Chapter 5.3.1 --- Equivalent Circuit Construction with Approximate Logic --- p.70<br>Chapter 5.3.2 --- Timing Error Masking with Approximate Logic --- p.72<br>Chapter 5.4 --- Cost-Efficient Synthesis for InTimeFix --- p.75<br>Chapter 5.4.1 --- Overall Flow --- p.76<br>Chapter 5.4.2 --- Prime Critical Segment Extraction --- p.77<br>Chapter 5.4.3 --- Prime Critical Segment Merging --- p.79<br>Chapter 5.5 --- Experimental Results --- p.81<br>Chapter 5.5.1 --- Experimental Setup --- p.81<br>Chapter 5.5.2 --- Results and Discussion --- p.82<br>Chapter 5.6 --- Conclusion --- p.85<br>Chapter 6 --- Conclusion and Future Work --- p.86<br>Bibliography --- p.100

Sze, Chin Ngai.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.<br>Includes bibliographical references (leaves 80-84) and index.<br>Abstracts in English and Chinese.<br>Abstract --- p.i<br>Acknowledgments --- p.iii<br>Curriculum Vitae --- p.iv<br>List of Figures --- p.ix<br>List of Tables --- p.xii<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Motivation and Aims --- p.1<br>Chapter 1.2 --- Contribution --- p.8<br>Chapter 1.3 --- Organization of Dissertation --- p.10<br>Chapter 2 --- Definitions and Notations --- p.11<br>Chapter 3 --- Literature Review --- p.15<br>Chapter 3.1 --- Logic Reconstruction --- p.15<br>Chapter 3.1.1 --- SIS: A System for Sequential and Combinational Logic Synthesis --- p.16<br>Chapter 3.2 --- ATPG-based Alternative Wiring --- p.17<br>Chapter 3.2.1 --- Redundancy Addition and Removal for Logic Optimization --- p.18<br>Chapter 3.2.2 --- Perturb and Simplify Logic Optimization --- p.18<br>Chapter 3.2.3 --- REWIRE --- p.21<br>Chapter 3.2.4 --- Implication-tree Based Alternative Wiring Logic Trans- formation --- p.22<br>Chapter 3.3 --- Graph-based Alternative Wiring --- p.24<br>Chapter 4 --- Implication Based Alternative Wiring Logic Transformation --- p.25<br>Chapter 4.1 --- Source Node Implication --- p.25<br>Chapter 4.1.1 --- Introduction --- p.25<br>Chapter 4.1.2 --- Implication Relationship and Implication-tree --- p.25<br>Chapter 4.1.3 --- Selection of Alternative Wire Based on Implication-tree --- p.29<br>Chapter 4.1.4 --- Implication-tree Based Logic Transformation --- p.32<br>Chapter 4.2 --- Destination Node Implication --- p.35<br>Chapter 4.2.1 --- Introduction --- p.35<br>Chapter 4.2.2 --- Destination Node Relationship --- p.35<br>Chapter 4.2.3 --- Destination Node Implication-tree --- p.39<br>Chapter 4.2.4 --- Selection of Alternative Wire --- p.41<br>Chapter 4.3 --- The Algorithm --- p.43<br>Chapter 4.3.1 --- IB AW Implementation --- p.43<br>Chapter 4.3.2 --- Experimental Results --- p.43<br>Chapter 4.4 --- Conclusion --- p.45<br>Chapter 5 --- Graph Based Alternative Wiring Logic Transformation --- p.47<br>Chapter 5.1 --- Introduction --- p.47<br>Chapter 5.2 --- Notations and Definitions --- p.48<br>Chapter 5.3 --- Alternative Wire Patterns --- p.50<br>Chapter 5.4 --- Construction of Minimal Patterns --- p.54<br>Chapter 5.4.1 --- Minimality of Patterns --- p.54<br>Chapter 5.4.2 --- Minimal Pattern Formation --- p.56<br>Chapter 5.4.3 --- Pattern Extraction --- p.61<br>Chapter 5.5 --- Experimental Results --- p.63<br>Chapter 5.6 --- Conclusion --- p.63<br>Chapter 6 --- Logic Optimization by GBAW --- p.66<br>Chapter 6.1 --- Introduction --- p.66<br>Chapter 6.2 --- Logic Simplification --- p.67<br>Chapter 6.2.1 --- Single-Addition-Multiple-Removal by Pattern Feature . . --- p.67<br>Chapter 6.2.2 --- Single-Addition-Multiple-Removal by Combination of Pat- terns --- p.68<br>Chapter 6.2.3 --- Single-Addition-Single-Removal --- p.70<br>Chapter 6.3 --- Incremental Perturbation Heuristic --- p.71<br>Chapter 6.4 --- GBAW Optimization Algorithm --- p.73<br>Chapter 6.5 --- Experimental Results --- p.73<br>Chapter 6.6 --- Conclusion --- p.76<br>Chapter 7 --- Conclusion --- p.78<br>Bibliography --- p.80<br>Chapter A --- VLSI Design Cycle --- p.85<br>Chapter B --- Alternative Wire Patterns in [WLFOO] --- p.87<br>Chapter B.1 --- 0-local Pattern --- p.87<br>Chapter B.2 --- 1-local Pattern --- p.88<br>Chapter B.3 --- 2-local Pattern --- p.89<br>Chapter B.4 --- Fanout-reconvergent Pattern --- p.90<br>Chapter C --- New Alternative Wire Patterns --- p.91<br>Chapter C.1 --- Pattern Cluster C1 --- p.91<br>Chapter C.1.1 --- NAND-NAND-AND/NAND;AND/NAND --- p.91<br>Chapter C.1.2 --- NOR-NOR-OR/NOR;AND/NAND --- p.92<br>Chapter C.1.3 --- AND-NOR-OR/NOR;OR/NOR --- p.95<br>Chapter C.1.4 --- OR-NAND-AND/NAND;AND/NAND --- p.95<br>Chapter C.2 --- Pattern Cluster C2 --- p.98<br>Chapter C.3 --- Pattern Cluster C3 --- p.99<br>Chapter C.4 --- Pattern Cluster C4 --- p.104<br>Chapter C.5 --- Pattern Cluster C5 --- p.105<br>Glossary --- p.106<br>Index --- p.108

Synchronization is one of the important issues in digital system design. While other approaches have been intriguing, up until now a globally clocked timing discipline has been the dominant design philosophy. However, we have reached the point, with advances in technology, where other options should be given serious consideration. VLSI promises great processing power at low cost. This increase in computation power has been obtained by scaling the digital IC process. But as this scaling continues, it is doubtful that the advantages of faster devices can be fully exploited. This is because the clock periods are getting much smaller in relation to the interconnect propagation delays, even within a single chip and certainly at the board and backplane level. In this thesis, some alternative approaches to synchronization in digital system design are described and developed. We owe these techniques to a long history of effort in both digital computational system design as well as digital communication system design. The latter field is relevant because large propagation delays have always been a dominant consideration in its design methods. Asynchronous design gives better performance than comparable synchronous design in situations for which a global synchronization with a high speed clock becomes a constraint for greater system throughput. Asynchronous circuits with unbounded gate delays, or self-timed digital circuit can be designed by employing either of two request-acknowledge protocols 4-cycle and 2-cycle. We will also present an alternative approach to the problem of mapping computation algorithms directly into asynchronous circuits. Data flow graph or language is used to describe the computation algorithms. The data flow primitives have been designed using both the 2-cycle and 4-cycle signaling schemes which are compared in terms of performance and transistor count. The 2-cycle implementations prove to be better than their 4-cycle counterparts. A promising application of self-timed design is in high performance DSP systems. Since there is no global constraint of clock distribution, localized forwardonly connection allows computation to be extended and sped up using pipelining. A decimation filter was designed and simulated to check the system level performance of the two protocols. Simulations were carried out using VHDL for high level definition of the design. The simulation results will demonstrate not only the efficacy of our synthesis procedure but also the improved efficiency of the 2-cycle scheme over the 4- cycle scheme.<br>Graduation date: 1994

Lee Chi-wai.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2002.<br>Includes bibliographical references (leaves 191-196).<br>Abstracts in English and Chinese.<br>Abstract of this thesis entitled: --- p.i<br>摘要 --- p.iii<br>Acknowledgements --- p.v<br>Table of Contents --- p.vii<br>List of Tables --- p.x<br>List of Figures --- p.xi<br>Chapter Chapter1 --- Introduction --- p.1<br>Chapter 1.1 --- Synchronous Design --- p.1<br>Chapter 1.2 --- Asynchronous Design --- p.2<br>Chapter 1.3 --- Discrete Cosine Transform --- p.4<br>Chapter 1.4 --- Motivation --- p.5<br>Chapter 1.5 --- Organization of the Thesis --- p.6<br>Chapter Chapter2 --- Asynchronous Design Methodology --- p.7<br>Chapter 2.1 --- Overview --- p.7<br>Chapter 2.2 --- Background --- p.8<br>Chapter 2.3 --- Past Designs --- p.10<br>Chapter 2.4 --- Micropipeline --- p.12<br>Chapter 2.5 --- New Asynchronous Architecture --- p.15<br>Chapter Chapter3 --- DCT/IDCT Processor Design Methodology --- p.24<br>Chapter 3.1 --- Overview --- p.24<br>Chapter 3.2 --- Hardware Architecture --- p.25<br>Chapter 3.3 --- DCT Algorithm --- p.26<br>Chapter 3.4 --- Used Architecture and DCT Algorithm --- p.30<br>Chapter 3.4.1 --- Implementation on Programmable DSP Processor --- p.31<br>Chapter 3.4.2 --- Implementation on Dedicated Processor --- p.33<br>Chapter Chapter4 --- New Techniques for Operating Dynamic Logic in Low Frequency --- p.36<br>Chapter 4.1 --- Overview --- p.36<br>Chapter 4.2 --- Background --- p.37<br>Chapter 4.3 --- Traditional Technique --- p.39<br>Chapter 4.4 --- New Technique - Refresh Control Circuit --- p.40<br>Chapter 4.4.1 --- Principle --- p.41<br>Chapter 4.4.2 --- Voltage Sensor --- p.42<br>Chapter 4.4.3 --- Ring Oscillator --- p.43<br>Chapter 4.4.4 --- "Counter, Latch and Comparator" --- p.46<br>Chapter 4.4.5 --- Recalibrate Circuit --- p.47<br>Chapter 4.4.6 --- Operation Monitoring Circuit --- p.48<br>Chapter 4.4.7 --- Overall Circuit --- p.48<br>Chapter Chapter5 --- DCT Implementation on Programmable DSP Processor --- p.51<br>Chapter 5.1 --- Overview --- p.51<br>Chapter 5.2 --- Processor Architecture --- p.52<br>Chapter 5.2.1 --- Arithmetic Unit --- p.53<br>Chapter 5.2.2 --- Switching Network --- p.56<br>Chapter 5.2.3 --- FIFO Memory --- p.59<br>Chapter 5.2.4 --- Instruction Memory --- p.60<br>Chapter 5.3 --- Programming --- p.62<br>Chapter 5.4 --- DCT Implementation --- p.63<br>Chapter Chapter6 --- DCT Implementation on Dedicated DCT Processor --- p.66<br>Chapter 6.1 --- Overview --- p.66<br>Chapter 6.2 --- DCT Chip Architecture --- p.67<br>Chapter 6.2.1 --- ID DCT Core --- p.68<br>Chapter 6.2.1.1 --- Core Architecture --- p.74<br>Chapter 6.2.1.2 --- Flow of Operation --- p.76<br>Chapter 6.2.1.3 --- Data Replicator --- p.79<br>Chapter 6.2.1.4 --- DCT Coefficients Memory --- p.80<br>Chapter 6.2.2 --- Combination of IDCT to 1D DCT core --- p.82<br>Chapter 6.2.3 --- Accuracy --- p.85<br>Chapter 6.3 --- Transpose Memory --- p.87<br>Chapter 6.3.1 --- Architecture --- p.89<br>Chapter 6.3.2 --- Address Generator --- p.91<br>Chapter 6.3.3 --- RAM Block --- p.94<br>Chapter Chapter7 --- Results and Discussions --- p.97<br>Chapter 7.1 --- Overview --- p.97<br>Chapter 7.2 --- Refresh Control Circuit --- p.97<br>Chapter 7.2.1 --- Implementation Results and Performance --- p.97<br>Chapter 7.2.2 --- Discussion --- p.100<br>Chapter 7.3 --- Programmable DSP Processor --- p.102<br>Chapter 7.3.1 --- Implementation Results and Performance --- p.102<br>Chapter 7.3.2 --- Discussion --- p.104<br>Chapter 7.4 --- ID DCT/IDCT Core --- p.107<br>Chapter 7.4.1 --- Simulation Results --- p.107<br>Chapter 7.4.2 --- Measurement Results --- p.109<br>Chapter 7.4.3 --- Discussion --- p.113<br>Chapter 7.5 --- Transpose Memory --- p.122<br>Chapter 7.5.1 --- Simulated Results --- p.122<br>Chapter 7.5.2 --- Measurement Results --- p.123<br>Chapter 7.5.3 --- Discussion --- p.126<br>Chapter Chapter8 --- Conclusions --- p.130<br>Appendix --- p.133<br>Operations of switches in DCT implementation of programmable DSP processor --- p.133<br>C Program for evaluating the error in DCT/IDCT core --- p.135<br>Pin Assignments of the Programmable DSP Processor Chip --- p.142<br>Pin Assignments of the 1D DCT/IDCT Core Chip --- p.144<br>Pin Assignments of the Transpose Memory Chip --- p.147<br>Chip microphotograph of the 1D DCT/IDCT core --- p.150<br>Chip Microphotograph of the Transpose Memory --- p.151<br>Measured Waveforms of 1D DCT/IDCT Chip --- p.152<br>Measured Waveforms of Transpose Memory Chip --- p.156<br>Schematics of Refresh Control Circuit --- p.158<br>Schematics of Programmable DSP Processor --- p.164<br>Schematics of 1D DCT/IDCT Core --- p.180<br>Schematics of Transpose Memory --- p.187<br>References --- p.191<br>Design Libraries - CD-ROM --- p.197

by Johnson, Tin-Chak Pang.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.<br>Includes bibliographical references.<br>Acknowledgments<br>Abstract<br>List of figures<br>List of tables<br>Chapter 1. --- Introduction --- p.1-1<br>Chapter 1.1 --- Introduction --- p.1-1<br>Chapter 1.2 --- Introduction to asynchronous system --- p.1-5<br>Chapter 1.2.1 --- Motivation --- p.1-5<br>Chapter 1.2.2 --- Hazards --- p.1-7<br>Chapter 1.2.3 --- Classes of Asynchronous circuits --- p.1-8<br>Chapter 1.3 --- Introduction to Transform Coding --- p.1-9<br>Chapter 1.4 --- Organization of the Thesis --- p.1-16<br>Chapter 2. --- Asynchronous Design Methodologies --- p.2-1<br>Chapter 2.1 --- Introduction --- p.2-1<br>Chapter 2.2 --- Self-timed system --- p.2-2<br>Chapter 2.3 --- DCVSL Methodology --- p.2-4<br>Chapter 2.3.1 --- DCVSL gate --- p.2-5<br>Chapter 2.3.2 --- Handshake Control --- p.2-7<br>Chapter 2.4 --- Micropipeline Methodology --- p.2-11<br>Chapter 2.4.1 --- Summary of previous design --- p.2-12<br>Chapter 2.4.2 --- New Micropipeline structure and improvements --- p.2-17<br>Chapter 2.4.2.1 --- Asymmetrical delay --- p.2-20<br>Chapter 2.4.2.2 --- Variable Delay and Delay Value Selection --- p.2-22<br>Chapter 2.5 --- Comparison between DCVSL and Micropipeline --- p.2-25<br>Chapter 3. --- Self-timed Multipliers --- p.3-1<br>Chapter 3.1 --- Introduction --- p.3-1<br>Chapter 3.2 --- Design Example 1 : Bit-serial matrix multiplier --- p.3-3<br>Chapter 3.2.1 --- DCVSL design --- p.3-4<br>Chapter 3.2.2 --- Micropipeline design --- p.3-4<br>Chapter 3.2.3 --- The first test chip --- p.3-5<br>Chapter 3.2.4 --- Second test chip --- p.3-7<br>Chapter 3.3 --- Design Example 2 - Modified Booth's Multiplier --- p.3-9<br>Chapter 3.3.1 --- Circuit Design --- p.3-10<br>Chapter 3.3.2 --- Simulation result --- p.3-12<br>Chapter 3.3.3 --- The third test chip --- p.3-14<br>Chapter 4. --- Current-Sensing Completion Detection --- p.4-1<br>Chapter 4.1 --- Introduction --- p.4-1<br>Chapter 4.2 --- Current-sensor --- p.4-2<br>Chapter 4.2.1 --- Constant current source --- p.4-2<br>Chapter 4.2.2 --- Current mirror --- p.4-4<br>Chapter 4.2.3 --- Current comparator --- p.4-5<br>Chapter 4.3 --- Self-timed logic using CSCD --- p.4-9<br>Chapter 4.4 --- CSCD test chips and testing results --- p.4-10<br>Chapter 4.4.1 --- Test result --- p.4-11<br>Chapter 5. --- Self-timed ICT processor architecture --- p.5-1<br>Chapter 5.1 --- Introduction --- p.5-1<br>Chapter 5.2 --- Comparison of different architecture --- p.5-3<br>Chapter 5.2.1 --- General purpose Digital Signal Processor --- p.5-5<br>Chapter 5.2.1.1 --- Hardware and speed estimation : --- p.5-6<br>Chapter 5.2.2 --- Micropipeline without fast algorithm --- p.5-7<br>Chapter 5.2.2.1 --- Hardware and speed estimation : --- p.5-8<br>Chapter 5.2.3 --- Micropipeline with fast algorithm (I) --- p.5-8<br>Chapter 5.2.3.1 --- Hardware and speed estimation : --- p.5-9<br>Chapter 5.2.4 --- Micropipeline with fast algorithm (II) --- p.5-10<br>Chapter 5.2.4.1 --- Hardware and speed estimation : --- p.5-11<br>Chapter 6. --- Implementation of self-timed ICT processor --- p.6-1<br>Chapter 6.1 --- Introduction --- p.6-1<br>Chapter 6.2 --- Implementation of Self-timed 2-D ICT processor (First version) --- p.6-3<br>Chapter 6.2.1 --- 1-D ICT module --- p.6-4<br>Chapter 6.2.2 --- Self-timed Transpose memory --- p.6-5<br>Chapter 6.2.3 --- Layout Design --- p.6-8<br>Chapter 6.3 --- Implementation of Self-timed 1-D ICT processor with fast algorithm (final version) --- p.6-9<br>Chapter 6.3.1 --- I/O buffers and control units --- p.6-10<br>Chapter 6.3.1.1 --- Input control --- p.6-11<br>Chapter 6.3.1.2 --- Output control --- p.6-12<br>Chapter 6.3.1.2.1 --- Self-timed Computational Block --- p.6-13<br>Chapter 6.3.1.3 --- Handshake Control Unit --- p.6-14<br>Chapter 6.3.1.4 --- Integer Execution Unit (IEU) --- p.6-18<br>Chapter 6.3.1.5 --- Program memory and Instruction decoder --- p.6-20<br>Chapter 6.3.2 --- Layout Design --- p.6-21<br>Chapter 6.4 --- Specifications of the final version self-timed ICT chip --- p.6-22<br>Chapter 7. --- Testing of Self-timed ICT processor --- p.7-1<br>Chapter 7.1 --- Introduction --- p.7-1<br>Chapter 7.2 --- Pin assignment of Self-timed 1 -D ICT chip --- p.7-2<br>Chapter 7.3 --- Simulation --- p.7-3<br>Chapter 7.4 --- Testing of Self-timed 1-D ICT processor --- p.7-5<br>Chapter 7.4.1 --- Functional test --- p.7-5<br>Chapter 7.4.1.1 --- Testing environment and results --- p.7-5<br>Chapter 7.4.2 --- Transient Characteristics --- p.7-7<br>Chapter 7.4.3 --- Comments on speed and power --- p.7-10<br>Chapter 7.4.4 --- Determination of optimum delay control voltage --- p.7-12<br>Chapter 7.5 --- Testing of delay element and other logic cells --- p.7-13<br>Chapter 8. --- Conclusions --- p.8-1<br>Bibliography<br>Appendices

Includes bibliographical references (leaves 277-284) Presents and discusses new design techniques for mixed analog-digital circuits with emphases on low power and small area for standard low-cost CMOS VLSI technology.

Bibliography: leaves 188-203.<br>xxii, 203 leaves : ill. ; 30 cm.<br>Title page, contents and abstract only. The complete thesis in print form is available from the University Library.<br>In this thesis insect vision principles are applied to the main mechanism for motion detection. Advanced VLSI technologies are employed for designing smart micro-sensors in which the imager and processor are integrated into one monolithic device.<br>Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1996

Bibliography: leaves 188-203.<br>xxii, 203 leaves : ill. ; 30 cm.<br>In this thesis insect vision principles are applied to the main mechanism for motion detection. Advanced VLSI technologies are employed for designing smart micro-sensors in which the imager and processor are integrated into one monolithic device.<br>Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1996