Letteratura scientifica selezionata sul tema "Hot-Carrier Degradation (HCD)"
Cita una fonte nei formati APA, MLA, Chicago, Harvard e in molti altri stili
Consulta la lista di attuali articoli, libri, tesi, atti di convegni e altre fonti scientifiche attinenti al tema "Hot-Carrier Degradation (HCD)".
Accanto a ogni fonte nell'elenco di riferimenti c'è un pulsante "Aggiungi alla bibliografia". Premilo e genereremo automaticamente la citazione bibliografica dell'opera scelta nello stile citazionale di cui hai bisogno: APA, MLA, Harvard, Chicago, Vancouver ecc.
Puoi anche scaricare il testo completo della pubblicazione scientifica nel formato .pdf e leggere online l'abstract (il sommario) dell'opera se è presente nei metadati.
Articoli di riviste sul tema "Hot-Carrier Degradation (HCD)":
1
Макаров, А. А., С. Э. Тягинов, B. Kaczer, M. Jech, A. Chasin, A. Grill, G. Hellings, М. И. Векслер, D. Linten e T. Grasser. "Анализ особенностей деградации, вызываемой горячими носителями, в транзисторах с каналом в форме плавника". Физика и техника полупроводников 52, n. 10 (2018): 1177. http://dx.doi.org/10.21883/ftp.2018.10.46457.8820.
Abstract (sommario):
AbstractFor the first time, hot-carrier degradation (HCD) is simulated in non-planar field-effect transistors with a fin-shaped channel (FinFETs). For this purpose, a physical model considering single-carrier and multiple-carrier silicon–hydrogen bond breaking processes and their superpositions is used. To calculate the bond-dissociation rate, carrier energy distribution functions are used, which are determined by solving the Boltzmann transport equation. A HCD analysis shows that degradation is localized in the channel region adjacent to the transistor drain in the top channel-wall region. Good agreement between the experimental and calculated degradation characteristics is achieved with the same model parameters which were used for HCD reproduction in planar short-channel transistors and high-power semiconductor devices.
2
Yu, Zhuoqing, Zhe Zhang, Zixuan Sun, Runsheng Wang e Ru Huang. "On the Trap Locations in Bulk FinFETs After Hot Carrier Degradation (HCD)". IEEE Transactions on Electron Devices 67, n. 7 (luglio 2020): 3005–9. http://dx.doi.org/10.1109/ted.2020.2994171.
3
Tyaginov, Stanislav, Erik Bury, Alexander Grill, Zhuoqing Yu, Alexander Makarov, An De Keersgieter, Mikhail Vexler et al. "Compact Physics Hot-Carrier Degradation Model Valid over a Wide Bias Range". Micromachines 14, n. 11 (30 ottobre 2023): 2018. http://dx.doi.org/10.3390/mi14112018.
Abstract (sommario):
We develop a compact physics model for hot-carrier degradation (HCD) that is valid over a wide range of gate and drain voltages (Vgs and Vds, respectively). Special attention is paid to the contribution of secondary carriers (generated by impact ionization) to HCD, which was shown to be significant under stress conditions with low Vgs and relatively high Vds. Implementation of this contribution is based on refined modeling of carrier transport for both primary and secondary carriers. To validate the model, we employ foundry-quality n-channel transistors and a broad range of stress voltages {Vgs,Vds}.
4
Kim, Jongsu, Kyushik Hong, Hyewon Shim, HwaSung Rhee e Hyungcheol Shin. "Comparative Analysis of Hot Carrier Degradation (HCD) in 10-nm Node nMOS/pMOS FinFET Devices". IEEE Transactions on Electron Devices 67, n. 12 (dicembre 2020): 5396–402. http://dx.doi.org/10.1109/ted.2020.3031246.
5
Makarov, Alexander, Philippe Roussel, Erik Bury, Michiel Vandemaele, Alessio Spessot, Dimitri Linten, Ben Kaczer e Stanislav Tyaginov. "Correlated Time-0 and Hot-Carrier Stress Induced FinFET Parameter Variabilities: Modeling Approach". Micromachines 11, n. 7 (30 giugno 2020): 657. http://dx.doi.org/10.3390/mi11070657.
Abstract (sommario):
We identify correlation between the drain currents in pristine n-channel FinFET transistors and changes in time-0 currents induced by hot-carrier stress. To achieve this goal, we employ our statistical simulation model for hot-carrier degradation (HCD), which considers the effect of random dopants (RDs) on HCD. For this analysis we generate a set of 200 device instantiations where each of them has its own unique configuration of RDs. For all “samples” in this ensemble we calculate time-0 currents (i.e., currents in undamaged FinFETs) and then degradation characteristics such as changes in the linear drain current and device lifetimes. The robust correlation analysis allows us to identify correlation between transistor lifetimes and drain currents in unstressed devices, which implies that FinFETs with initially higher currents degrade faster, i.e., have more prominent linear drain current changes and shorter lifetimes. Another important result is that although at stress conditions the distribution of drain currents becomes wider with stress time, in the operating regime drain current variability diminishes. Finally, we show that if random traps are also taken into account, all the obtained trends remain the same.
6
Liu, Minghao, Zixuan Sun, Haoran Lu, Cong Shen, Lining Zhang, Runsheng Wang e Ru Huang. "A Coupling Mechanism between Flicker Noise and Hot Carrier Degradations in FinFETs". Nanomaterials 13, n. 9 (28 aprile 2023): 1507. http://dx.doi.org/10.3390/nano13091507.
Abstract (sommario):
A coupling mechanism between flicker noise and hot carrier degradation (HCD) is revealed in this work. Predicting the flicker noise properties of fresh and aged devices is becoming essential for circuit designs, requiring an understanding of the fundamental noise behaviors. While certain models for fresh devices have been proposed, those for aged devices have not been reported yet because of the lack of a clear mechanism. The flicker noise of aged FinFETs is characterized based on the measure-stress-measure (MSM) method and analyzed from the device physics. It is found that both the mean and deviations of the noise power spectral density increase compared with the fresh counterparts. A coupling mechanism is proposed to explain the trap time constants, leading to the trap characterizations in their energy profiles. The amplitude and number of contributing traps are also changing and are dependent on the mode of HCD and determined by the position of the induced traps. A microscopic picture is developed from the perspective of trap coupling, reproducing well the measured noise of advanced nanoscale FinFETs. The finding is important for accurate flicker noise calculations and aging-aware circuit designs.
7
Kuo, Ting-Tzu, Ying-Chung Chen, Ting-Chang Chang, Kai-Chun Chang, Chien-Hung Yeh, Fong-Min Ciou, Yu-Shan Lin et al. "Abnormal trend in hot carrier degradation with fin profile in short channel FinFET devices at 14 nm node". Semiconductor Science and Technology 37, n. 4 (25 febbraio 2022): 045010. http://dx.doi.org/10.1088/1361-6641/ac557f.
Abstract (sommario):
Abstract This study investigates the impact of fin profiles under hot carrier stress, which defines different base widths: wide-base samples with the smallest slope, medium-base samples, and narrow-base samples with a larger slope. The performance of the narrow samples is better than the medium samples, regardless of transconductance, on-state current, subthreshold swing or drain-induced barrier lowering, demonstrating that the narrow profile samples’ mobility and gate control are better. In long channel devices, the trend of hot carrier degradation (HCD) is in agreement with previous references, and is dependent on the transverse electric field and the fin shapes. However, this trend does not exist for short-channel devices. Positive bias stress and technology computer aided design simulation are applied for investigation and to clarify the reasons for this abnormal HCD trend. Finally, by fitting the multiple vibrational excitation (MVE) mechanism, the slope of the trend lines in the short channel devices are found to indeed match the bending mode. In other words, the disappearance of the general trend between the HCD and fin profiles is caused by the change in the mechanism in the short-channel device. Because the MVE mechanism is independent from the electric field, the narrow profile fin shape more effectively promotes gate control and better performance without affecting the reliability in short channel devices. These results can provide a clear direction for fin shape designers in the future.
8
Sun, Zixuan, Sihao Chen, Lining Zhang, Ru Huang e Runsheng Wang. "The Understanding and Compact Modeling of Reliability in Modern Metal–Oxide–Semiconductor Field-Effect Transistors: From Single-Mode to Mixed-Mode Mechanisms". Micromachines 15, n. 1 (12 gennaio 2024): 127. http://dx.doi.org/10.3390/mi15010127.
Abstract (sommario):
With the technological scaling of metal–oxide–semiconductor field-effect transistors (MOSFETs) and the scarcity of circuit design margins, the characteristics of device reliability have garnered widespread attention. Traditional single-mode reliability mechanisms and modeling are less sufficient to meet the demands of resilient circuit designs. Mixed-mode reliability mechanisms and modeling have become a focal point of future designs for reliability. This paper reviews the mechanisms and compact aging models of mixed-mode reliability. The mechanism and modeling method of mixed-mode reliability are discussed, including hot carrier degradation (HCD) with self-heating effect, mixed-mode aging of HCD and Bias Temperature Instability (BTI), off-state degradation (OSD), on-state time-dependent dielectric breakdown (TDDB), and metal electromigration (EM). The impact of alternating HCD-BTI stress conditions is also discussed. The results indicate that single-mode reliability analysis is insufficient for predicting the lifetime of advanced technology and circuits and provides guidance for future mixed-mode reliability analysis and modeling.
9
Chang, Hao, Guilei Wang, Hong Yang, Qianqian Liu, Longda Zhou, Zhigang Ji, Ruixi Yu et al. "Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique". Nanomaterials 13, n. 7 (3 aprile 2023): 1259. http://dx.doi.org/10.3390/nano13071259.
Abstract (sommario):
In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found that increasing GIDL bias from 3 V to 4 V achieves a 114.7% VT recovery ratio from HCD. This over-repair phenomenon of HCD by UFM GIDL is deeply discussed through oxide trap behaviors. When the applied gate-to-drain GIDL bias reaches 4 V, a significant electron trapping and interface trap generation of the fresh device with GIDL repair is observed, which greatly contributes to the approximate 114.7% over-repair VT ratio of the device under worst HCD stress (−2.0 V, 200 s). Based on the TCAD simulation results, the increase in the vertical electric field on the surface of the channel oxide layer is the direct cause of an extraordinary electron trapping effect accompanied by the over-repair phenomenon. Under a high positive electric field, a part of channel electrons is captured by oxide traps in the gate dielectric, leading to further VT recovery. Through the discharge-based multi-pulse (DMP) technique, the energy distribution of oxide traps after GIDL recovery is obtained. It is found that over-repair results in a 34% increment in oxide traps around the conduction energy band (Ec) of silicon, which corresponds to a higher stabilized VT shift under multi-cycle HCD-GIDL tests. The results provide a trap-based understanding of the transistor repairing technique, which could provide guidance for the reliable long-term operation of ICs.
10
Diaz-Fortuny, Javier, Pablo Saraza-Canflanca, Erik Bury, Robin Degraeve e Ben Kaczer. "An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage". Micromachines 15, n. 6 (8 giugno 2024): 769. http://dx.doi.org/10.3390/mi15060769.
Abstract (sommario):
The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC.
Tesi sul tema "Hot-Carrier Degradation (HCD)":
1
Mazzoli, Andrea. "TCAD analysis of hot-carrier-stress degradation in p-channel LDMOS power devices". Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021.
Abstract (sommario):
Nowadays, there is an increasing need to develop, reliable and low-cost power devices able to withstand high voltage drops and currents during the off-state and on-state operation, respectively. A useful strategy is represented by the integration on-chip of power devices with CMOS logic and analog technologies. This kind of solution is named BCD (BIPOLAR-CMOS-DMOS) technology.
One of the fundamental power device on which the BCD technology is based is the LDMOS (Laterally-Diffused Metal-Oxide Semiconductor) transistor. The study and understanding of the degradation mechanisms affecting their long-term reliability is of great interest because of the stringent requirements in terms of safety, robustness, etc., basing on the field of application of the circuit in which the devices are integrated.
This work, in collaboration with STMicroelectronics, focuses on the optimization of the p-channel LDMOS transistors and aims at studying and understanding how the Hot Carrier Stress (HCS) degradation impacts their performance for long working times. The behavior of the device is simulated through the Sentaurus TCAD where a HCS degradation model is employed to understand which are the dominant effects of the hot particles within the semiconductor, applying stress conditions aimed at accelerating the degradation mechanisms causing the drift of key parameters.
In this work the focus is on the on-resistance, since it results to be the main parameter affected by degradation. The goal is to understand exactly which is the main cause of such variation in order to be able to allow a technology improvement. The simulations have been calibrated against experimental data.
The on-resistance curve are correctly calibrated under certain stress conditions. The goal of the thesis activity has been achieved with accurate results, bringing to a more detailed description of a p-channel LDMOS power device through the development of a first version of the predictive simulation tool.
2
Sicre, Mathieu. "Study of the noise aging mechanisms in single-photon avalanche photodiode for time-of-flight imaging". Electronic Thesis or Diss., Lyon, INSA, 2023. http://www.theses.fr/2023ISAL0104.
Abstract (sommario):
Les diodes à avalanche à photon unique (SPAD) sont utilisées pour les capteurs à temps de vol afin de déterminer la distance d'une cible. Cependant, ils sont sujets à des déclenchements parasites par des porteurs de charge générés de manière parasitaire, quantifiés en tant que taux de comptage dans l’obscurité (DCR), ce qui peut compromettre la précision de la distance mesurée. Pour résoudre ce problème, une méthodologie de simulation a été mise en place pour évaluer le DCR. Cela est réalisé en simulant la probabilité de claquage d'avalanche, intégrée avec le taux de génération de porteurs de charge à partir de défauts. Cette méthodologie permet d'identifier les sources potentielles de DCR avant stress. Pour garantir l'intégrité des mesures de distance sur une longue période, il est nécessaire de prédire le niveau de DCR dans diverses conditions d'exploitation. La méthodologie de simulation susmentionnée est utilisée pour identifier les sources potentielles de DCR après stress. Pour un modèle cinétique précis de dégradation de type porteurs chauds (HCD), il est essentiel de considérer non seulement la distribution d'énergie des porteurs, mais également la distribution de l'énergie de dissociation de la liaison Si-H à l'interface Si/SiO2. La probabilité de dissociation d'ionisation d'impact est utilisée pour modéliser le processus de création de défauts, qui présente une dépendance temporelle sous-linéaire en raison de l'épuisement progressif des précurseurs de défauts. Une mesure précise de la distance nécessite de distinguer le signal du bruit ambiant et du plancher de DCR. L'impact de DCR peut être estimé en considérant la réflectance de la cible et les conditions d'éclairage ambiant. En résumé, ce travail utilise une méthodologie de caractérisation et de simulation approfondie pour prédire le DCR dans les dispositifs de type SPAD le long de sa durée de vie, permettant ainsi d'évaluer son impact sur les mesures de distanceSingle-Photon Avalanche Diode (SPAD) are used for Time-of-Flight (ToF) sensors to determine distance from a target by measuring the travel time of an emitted pulsed signal. These photodetectors work by triggering an avalanche of charge carriers upon photon absorption, resulting in a substantial amplification which can be detected. However, they are subject to spurious triggering by parasitic generated charge carriers, quantified as Dark Count Rate (DCR), which can compromise the accuracy of the measured distance. Therefore, it is crucial to identify and eliminate the potential source of DCR. To tackle this issue, a simulation methodology has been implemented to assess the DCR. This is achieved by simulating the avalanche breakdown probability, integrated with the carrier generation rate from defects. The breakdown probability can be simulated either in a deterministically, based on electric-field streamlines, or stochastically, by means of drift-diffusion simulation of the random carrier path. This methodology allows for the identification of the potential sources of pre-stress DCR by comparing simulation results to experimental data over a wide range of voltage and temperature. To ensure the accuracy of distance range measurements over time, it is necessary to predict the DCR level under various operating conditions. The aforementioned simulation methodology is used to identify the potential sources of post-stress DCR by comparing simulation results to stress experiments that evaluate the principal stress factors, namely temperature, voltage and irradiance. Furthermore, a Monte-Carlo study has been conducted to examine the device-to-device variation along stress duration. For an accurate Hot-Carrier Degradation (HCD) kinetics model, it is essential to consider not only the carrier energy distribution function but also the distribution of Si−H bond dissociation energy distribution at the Si/SiO2 interface. The number of available hot carriers is estimated from the carrier current density according to the carrier energy distribution simulated by means of a full-band Monte-Carlo method. The impact-ionization dissociation probability is employed to model the defect creation process, which exhibits sub-linear time dependence due to the gradual exhaustion of defect precursors. Accurate distance ranging requires distinguishing the signal from ambient noise and the DCR floor, and ensuring the target’s accumulated photon signal dominates over other random noise sources. An analytical formula allows to estimate the maximum distance ranging using the maximum signal strength, ambient noise level, and confidence levels. The impact of DCR can be estimated by considering the target’s reflectance and the ambient light conditions. In a nutshell, this work makes use of a in-depth characterization and simulation methodology to predict DCR in SPAD devices along stress duration, thereby allowing the assessment of its impact on distance range measurements
3
Arfaoui, Wafa. "Fiabilité Porteurs Chauds (HCI) des transistors FDSOI 28nm High-K grille métal". Thesis, Aix-Marseille, 2015. http://www.theses.fr/2015AIXM4335.
Abstract (sommario):
Au sein de la course industrielle à la miniaturisation et avec l’augmentation des exigences technologiques visant à obtenir plus de performances sur moins de surface, la fiabilité des transistors MOSFET est devenue un sujet d’étude de plus en plus complexe. Afin de maintenir un rythme de miniaturisation continu, des nouvelles architectures de transistors MOS en été introduite, les technologies conventionnelles sont remplacées par des technologies innovantes qui permettent d'améliorer l'intégrité électrostatique telle que la technologie FDSOI avec des diélectriques à haute constante et grille métal. Malgré toutes les innovations apportées sur l’architecture du MOS, les mécanismes de dégradations demeurent de plus en plus prononcés. L’un des mécanismes le plus critique des technologies avancées est le mécanisme de dégradation par porteurs chauds (HCI). Pour garantir les performances requises tout en préservant la fiabilité des dispositifs, il est nécessaire de caractériser et modéliser les différents mécanismes de défaillance au niveau du transistor élémentaire. Ce travail de thèse porte spécifiquement sur les mécanismes de dégradations HCI des transistors 28nm FDSOI. Basé sur l’énergie des porteurs, le modèle en tension proposé dans ce manuscrit permet de prédire la dégradation HC en tenant compte de la dépendance en polarisation de substrat incluant les effets de longueur, d’épaisseur de l’oxyde de grille ainsi que l’épaisseur du BOX et du film de silicium. Ce travail ouvre le champ à des perspectives d’implémentation du model HCI pour les simulateurs de circuits, ce qui représente une étape importante pour anticiper la fiabilité des futurs nœuds technologiquesAs the race towards miniaturization drives the industrial requirements to more performances on less area, MOSFETs reliability has become an increasingly complex topic. To maintain a continuous miniaturization pace, conventional transistors on bulk technologies were replaced by new MOS architectures allowing a better electrostatic integrity such as the FDSOI technology with high-K dielectrics and metal gate. Despite all the architecture innovations, degradation mechanisms remains increasingly pronounced with technological developments. One of the most critical issues of advanced technologies is the hot carrier degradation mechanism (HCI) and Bias Temperature Instability (BTI) effects. To ensure a good performance reliability trade off, it is necessary to characterize and model the different failure mechanisms at device level and the interaction with Bias Temperature Instability (BTI) that represents a strong limitation of scaled CMOS nodes. This work concern hot carrier degradation mechanisms on 28nm transistors of the FDSOI technology. Based on carrier’s energy, the energy driven model proposed in this manuscript can predict HC degradation taking account of substrate bias dependence (VB) including the channel length effects (L), gate oxide thickness (TOX) , back oxide BOX (TBox) and silicon film thickness (TSI ). This thesis opens up new perspectives of the model Integration into a circuit simulator, to anticipate the reliability of future technology nodes and check out circuit before moving on to feature design steps
4
Ndiaye, Cheikh. "Etude de la fiabilité de type negative bias temperature instability (NBTI) et par porteurs chauds (HC) dans les filières CMOS 28nm et 14nm FDSOI". Thesis, Aix-Marseille, 2017. http://www.theses.fr/2017AIXM0182/document.
Abstract (sommario):
L’avantage de cette architecture FDSOI par rapport à l’architecture Si-bulk est qu’elle possède une face arrière qui peut être utilisée comme une deuxième grille permettant de moduler la tension de seuil Vth du transistor. Pour améliorer les performances des transistors canal p (PMOS), du Germanium est introduit dans le canal (SiGe) et au niveau des sources/drain pour la technologie 14nm FDSOI. Par ailleurs, la réduction de la géométrie des transistors à ces dimensions nanométriques fait apparaître des effets de design physique qui impactent à la fois les performances et la fiabilité des transistors.Ce travail de recherche est développé sur quatre chapitres dont le sujet principal porte sur les performances et la fiabilité des dernières générations CMOS soumises aux mécanismes de dégradation BTI (Bias Temperature Instability) et par injections de porteurs chauds (HCI) dans les dernières technologies 28nm et 14nm FDSOI. Dans le chapitre I, nous nous intéressons à l’évolution de l’architecture du transistor qui a permis le passage des nœuds Low-Power 130-40nm sur substrat silicium à la technologie FDSOI (28nm et 14nm). Dans le chapitre II, les mécanismes de dégradation BTI et HCI des technologies 28nm et 14nm FDSOI sont étudiés et comparés avec les modèles standards utilisés. L’impact des effets de design physique (Layout) sur les paramètres électriques et la fiabilité du transistor sont traités dans le chapitre III en modélisant les contraintes induites par l’introduction du SiGe. Enfin le vieillissement et la dégradation des performances en fréquence ont été étudiés dans des circuits élémentaires de type oscillateurs en anneau (ROs), ce qui fait l’objet du chapitre IVThe subject of this thesis developed on four chapters, aims the development of advanced CMOS technology nodes fabricated by STMicroelectronics in terms of speed performance and reliability. The main reliability issues as Bias Temperature Instability (BTI) and Hot-Carriers (HC) degradation mechanisms have been studied in the most recent 28nm and 14nm FDSOI technologies nodes. In the first chapter, we presents the evolution of transistor architecture from the low-power 130-40nm CMOS nodes on silicon substrate to the recent FDSOI technology for 28nm and 14nm CMOS nodes. The second chapter presents the specificity of BTI and HCI degradation mechanisms involved in 28nm and 14nm FDSOI technology nodes. In the third chapter, we have studied the impact of layout effects on device performance and reliability comparing symmetrical and asymmetrical geometries. Finally the trade-off between performance and reliability is studied in the fourth chapter using elementary circuits. The benefit of using double gate configuration with the use of back bias VB in FDSOI devices to digital cells, allows to compensate partially or totally the aging in ring oscillators (ROs) observed by the frequency reduction. This new compensation technique allows to extend device and circuit lifetime offering a new way to guaranty high frequency performance and long-term reliability
5
Ndiaye, Cheikh. "Etude de la fiabilité de type negative bias temperature instability (NBTI) et par porteurs chauds (HC) dans les filières CMOS 28nm et 14nm FDSOI". Electronic Thesis or Diss., Aix-Marseille, 2017. http://www.theses.fr/2017AIXM0182.
Abstract (sommario):
L’avantage de cette architecture FDSOI par rapport à l’architecture Si-bulk est qu’elle possède une face arrière qui peut être utilisée comme une deuxième grille permettant de moduler la tension de seuil Vth du transistor. Pour améliorer les performances des transistors canal p (PMOS), du Germanium est introduit dans le canal (SiGe) et au niveau des sources/drain pour la technologie 14nm FDSOI. Par ailleurs, la réduction de la géométrie des transistors à ces dimensions nanométriques fait apparaître des effets de design physique qui impactent à la fois les performances et la fiabilité des transistors.Ce travail de recherche est développé sur quatre chapitres dont le sujet principal porte sur les performances et la fiabilité des dernières générations CMOS soumises aux mécanismes de dégradation BTI (Bias Temperature Instability) et par injections de porteurs chauds (HCI) dans les dernières technologies 28nm et 14nm FDSOI. Dans le chapitre I, nous nous intéressons à l’évolution de l’architecture du transistor qui a permis le passage des nœuds Low-Power 130-40nm sur substrat silicium à la technologie FDSOI (28nm et 14nm). Dans le chapitre II, les mécanismes de dégradation BTI et HCI des technologies 28nm et 14nm FDSOI sont étudiés et comparés avec les modèles standards utilisés. L’impact des effets de design physique (Layout) sur les paramètres électriques et la fiabilité du transistor sont traités dans le chapitre III en modélisant les contraintes induites par l’introduction du SiGe. Enfin le vieillissement et la dégradation des performances en fréquence ont été étudiés dans des circuits élémentaires de type oscillateurs en anneau (ROs), ce qui fait l’objet du chapitre IVThe subject of this thesis developed on four chapters, aims the development of advanced CMOS technology nodes fabricated by STMicroelectronics in terms of speed performance and reliability. The main reliability issues as Bias Temperature Instability (BTI) and Hot-Carriers (HC) degradation mechanisms have been studied in the most recent 28nm and 14nm FDSOI technologies nodes. In the first chapter, we presents the evolution of transistor architecture from the low-power 130-40nm CMOS nodes on silicon substrate to the recent FDSOI technology for 28nm and 14nm CMOS nodes. The second chapter presents the specificity of BTI and HCI degradation mechanisms involved in 28nm and 14nm FDSOI technology nodes. In the third chapter, we have studied the impact of layout effects on device performance and reliability comparing symmetrical and asymmetrical geometries. Finally the trade-off between performance and reliability is studied in the fourth chapter using elementary circuits. The benefit of using double gate configuration with the use of back bias VB in FDSOI devices to digital cells, allows to compensate partially or totally the aging in ring oscillators (ROs) observed by the frequency reduction. This new compensation technique allows to extend device and circuit lifetime offering a new way to guaranty high frequency performance and long-term reliability
Atti di convegni sul tema "Hot-Carrier Degradation (HCD)":
1
Zhang, Jiayang, Zixuan Sun, Runsheng Wang, Zhuoqing Yu, Pengpeng Ren e Ru Huang. "Body Bias Dependence of Hot Carrier Degradation (HCD) in Advanced FinFET Technology". In 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM). IEEE, 2018. http://dx.doi.org/10.1109/edtm.2018.8421470.
2
Sun, Zixuan, Yongkang Xue, Haoran Lu, Pengpeng Ren, Zirui Wang, Zhigang Ji, Runsheng Wang e Ru Huang. "Investigation of Interplays between Body Biasing and Hot Carrier Degradation (HCD) in Advanced NMOS FinFETs". In 2024 IEEE International Reliability Physics Symposium (IRPS). IEEE, 2024. http://dx.doi.org/10.1109/irps48228.2024.10529482.
3
Yu, Zhuoqing, Runsheng Wang, Peng Hao, Shaofeng Guo, Pengpeng Ren e Ru Huang. "Non-Universal Temperature Dependence of Hot Carrier Degradation (HCD) in FinFET: New Observations and Physical Understandings". In 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM). IEEE, 2018. http://dx.doi.org/10.1109/edtm.2018.8421469.
4
Yu, Zhuoqing, Jiayang Zhang, Runsheng Wang, Shaofeng Guo, Changze Liu e Ru Huang. "New insights into the hot carrier degradation (HCD) in FinFET: New observations, unified compact model, and impacts on circuit reliability". In 2017 IEEE International Electron Devices Meeting (IEDM). IEEE, 2017. http://dx.doi.org/10.1109/iedm.2017.8268344.
5
Varghese, Dhanoop, Muhammad Ashraful Alam e Bonnie Weir. "A generalized, IB-independent, physical HCI lifetime projection methodology based on universality of hot-carrier degradation". In 2010 IEEE International Reliability Physics Symposium. IEEE, 2010. http://dx.doi.org/10.1109/irps.2010.5488666.
6
Changze Liu, Kyong Taek Lee, Sangwoo Pae e Jongwoo Park. "New observations on hot carrier induced dynamic variation in nano-scaled SiON/poly, HK/MG and FinFET devices based on on-the-fly HCI technique: The role of single trap induced degradation". In 2014 IEEE International Electron Devices Meeting (IEDM). IEEE, 2014. http://dx.doi.org/10.1109/iedm.2014.7047170.