Tesi sul tema "Gate array circuits"
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Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /". Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.
Testo completoBaweja, Gunjeetsingh. "Gate level coverage of a behavioral test generator". Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-11102009-020104/.
Testo completoTan, Zhou. "Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing". Thesis, North Dakota State University, 2011. https://hdl.handle.net/10365/29176.
Testo completoHu, Jhy-Fang 1961. "AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY". Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276948.
Testo completoBalog, Michael Rosen Warren A. "The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration /". Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1770.
Testo completoHall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach". Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.
Testo completoPrvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.
Qi, Wen-jie. "Study on high-k dielectrics as alternative gate insulators for 0.1[mu] and beyond ULSI applications /". Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
Testo completoMao, Yu-lung. "Novel high-K gate dielectric engineering and thermal stability of critical interface /". Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
Testo completoLee, Jian-hung. "Strontium titanate thin films for ULSI memory and gate dielectric applications /". Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
Testo completoKucic, Matthew R. "Analog programmable filters using floating-gate arrays". Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13755.
Testo completoLee, Byoung Hun. "Technology development and process integration of alternative gate dielectric material : hafnium oxide /". Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004316.
Testo completoLuo, Tien-ying. "Electrical and physical analysis of ultra-thin in-situ steam generated (ISSG) SiO₂ and nitride/oxide stacks for ULSI application /". Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
Testo completoYin, Chunshan. "Source/drain and gate design of advanced MOSFET devices /". View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20YIN.
Testo completoZhuo, Yue. "Timing and Congestion Driven Algorithms for FPGA Placement". Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5423/.
Testo completoGray, Jordan D. "Application of Floating-Gate Transistors in Field Programmable Analog Arrays". Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7540.
Testo completoBlum, Thomas. "Modular exponentiation on reconfigurable hardware". Digital WPI, 1999. http://www.wpi.edu/Pubs/ETD/Available/etd-090399-090413/unrestricted/thesis.pdf.
Testo completoHooper, Mark S. "Submicron CMOS programmable analog floating-gate circuits and arrays using DC-DC converters". Diss., Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-12032004-155022/unrestricted/Hooper%5FMark%5FS%5F200505%5Fphd.pdf.
Testo completoKucic, Matthew, Committee Member ; Hasler, Paul, Committee Chair ; Heck, Bonnie, Committee Member ; Cressler, John, Committee Member ; Anderson, David, Committee Member. Vita. Includes bibliographical references.
Fourie, Coenrad Johann. "A tool kit for the design of superconducting programmable gate arrays". Thesis, Stellenbosch : University of Stellenbosch, 2004. http://hdl.handle.net/10019.1/16048.
Testo completoENGLISH ABSTRACT: The development of a tool kit for the design of superconducting programmable gate arrays (SPGAs) is discussed. A circuit optimizer using genetic algorithms is developed and evaluated. Techniques and a program are also developed for the generation of segmentized 3D models with which to calculate inductance in circuit structures through FastHenry. The ability to add random variations to the dimensions of the models is included. These tools are then used to design novel latching elements that allow the construction of reprogrammable Rapid Single Flux Quantum (RSFQ) circuits. A circular process is used, whereby layouts are converted back to circuit diagrams through element extraction, and reoptimized if necessary. Two programmable frequency dividers are then designed; one for testing the routing and switch structures and programming architecture of an SPGA, and another compact one for testing the latching elements and off-chip interface. The dissertation concludes with an overview of the circuits necessary for the implementation of a fully functional SPGA.
AFRIKAANSE OPSOMMING: Die ontwikkeling van ’n gereedskapstel vir die ontwerp van supergeleier FPGA’s (SPGA’s) word bespreek. Eerstens word ’n stroombaanoptimeerder, wat met genetiese algoritmes funksioneer, ontwikkel en geëvalueer. Daarna word tegnieke en ’n program ontwikkel om driedimensionele segmentmodelle te genereer waaruit FastHenry die induktansie van stroombaanstrukture kan bepaal. Die vermoë om toevalsveranderinge by die dimensies van die modelle te voeg, is ook ingesluit. Hierdie gereedskap word dan gebruik om nuwe grendelelemente te ontwerp waarmee herprogrammeerbare Rapid Single Flux Quantum (RSFQ) stroombane gebou kan word. ’n Sirkulêre proses word gevolg, waarvolgens uitlegte na stroombaandiagramme teruggeskakel kan word (deur elementonttrekkings) en, indien nodig, heroptimeer kan word. Twee programmeerbare frekwensiedelers word daarna ontwerp; een om die pulsvervoer- en skakelstrukture, asook programmeringsargitektuur van ’n SPGA te toets, en ’n ander, kompakter een om die grendelelemente en warmlogika koppelvlakke mee te toets. Die proefskrif sluit af met ’n oorsig oor die stroombane benodig vir die implementering van ’n volledig funksionele SPGA.
Coyne, Jack W. "FPGA-based co-processor for singular value array reconciliation tomography". Worcester, Mass. : Worcester Polytechnic Institute, 2007. http://www.wpi.edu/Pubs/ETD/Available/etd-090507-114502/.
Testo completoSchafer, Ingo. "Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping". PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/1339.
Testo completoJeon, Yongjoo. "High-k gate dielectric for 100 nm MOSFET application /". Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004296.
Testo completoChen, Yuh-yue. "Enhanced hot-hole degradation and negative bias temperature instability (NBTI) in p⁺-poly PMOSFETs with oxynitride gate dielectrics /". Digital version accessible at:, 2000. http://wwwlib.umi.com/cr/utexas/main.
Testo completoMulfinger, G. Robert. "Investigation of induced charge damage on self-aligned metal-gate MOS devices /". Online version of thesis, 2006. http://hdl.handle.net/1850/2036.
Testo completoLin, Limin. "A study of gate dielectrics for wide-bandgap semiconductors GaN & SiC /". Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/hkuto/record/B3932252X.
Testo completoLin, Limin, e 林立旻. "A study of gate dielectrics for wide-bandgap semiconductors: GaN & SiC". Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B3932252X.
Testo completoChawla, Ravi. "Power-efficient analog systems to perform signal-processing using floating-gate MOS device for portable applications". Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-01052005-144937/unrestricted/chawla%5Fravi%5F200505%5Fphd.pdf.
Testo completoPaul Hasler, Committee Member ; Joy Laskar, Committee Chair ; Phil Allen, Committee Member ; Dave Anderson, Committee Member ; Mark T. Smith, Committee Member. Includes bibliographical references.
Deng, Linfeng, e 邓林峰. "A study on pentacene organic thin-film transistors with Hf-based oxideas gate dielectric". Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2011. http://hub.hku.hk/bib/B47244513.
Testo completopublished_or_final_version
Electrical and Electronic Engineering
Doctoral
Doctor of Philosophy
Kang, Laeugu. "Study of HFO₂ as a future gate dielectric and implementation of polysilicon electrodes for HFO₂ films /". Full text (PDF) from UMI/Dissertation Abstracts International, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p3004301.
Testo completoZaghloul, Yasser A. "Polarization based digital optical representation, gates, and processor". Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/43675.
Testo completoWu, Lifei. "Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays". PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4745.
Testo completoOberdorf, Michael Craig. "Power losses and thermal modeling of a voltage source inverter". Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2006. http://library.nps.navy.mil/uhtbin/hyperion/06Mar%5FOberdorf.pdf.
Testo completoThesis Advisor(s): Alexander Julian. "March 2006." Includes bibliographical references (p. 103-104). Also available online.
Lodaya, Bhaveen. "On-Board Memory Extension on Reconfigurable Integrated Circuits using External DDR3 Memory". Master's thesis, Universitätsbibliothek Chemnitz, 2018. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-233196.
Testo completoBlanchardon, Adrien. "Synthèse d'architectures de circuits FPGA tolérants aux défauts". Thesis, Paris 6, 2015. http://www.theses.fr/2015PA066274/document.
Testo completoThe increasing integration density according to Moore’s law is being slowed due to economic and physical limits. However, this technological evolution involves an higher number of physical defects after manufacturing circuit. As yield goes down, one of the future challenges is to find a way to use a maximum of fabricated circuits while tolerating physical defects spread all over the chip. Fiel Programmable Gate Array (FPGA) are integrated circuits that contain logic blocks and reconfigurable interconnect. Their ability to integrate more complex applications, their flexibility and good performance make FPGAs the perfect target architecture. The aim of this thesis is to propose an FPGA architecture containing mechanisms to tolerate more than 20% of defective resources after manufacture. The first part of the manuscript studies the different FPGA architectures (mesh and tree) and different defects bypass techniques. In the second part of this thesis, we present the target architecture called Mesh of Clusters (MoC). This architecture combines the advantages of mesh architectures (genericity) and tree (reduction of the interconnect). The third contribution of this thesis is the development of a method to identify the most critical blocks in the FPGA and the impact of all bypass techniques on the architecture and on the criticality. Finally, we define the performance of all bypass techniques in terms of defect tolerance, timing and area overhead. Finally, thanks to these local redundancy techniques, we are able to tolerate more than 20% of defect on the FPGA architecture. In addition, the designer can fix his own metric in terms of area, timing and defect tolerance
Zhou, Jing 1959. "LOVERD--a logic design verification and diagnosis system via test generation". Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/291686.
Testo completoBlanchardon, Adrien. "Synthèse d'architectures de circuits FPGA tolérants aux défauts". Electronic Thesis or Diss., Paris 6, 2015. http://www.theses.fr/2015PA066274.
Testo completoThe increasing integration density according to Moore’s law is being slowed due to economic and physical limits. However, this technological evolution involves an higher number of physical defects after manufacturing circuit. As yield goes down, one of the future challenges is to find a way to use a maximum of fabricated circuits while tolerating physical defects spread all over the chip. Fiel Programmable Gate Array (FPGA) are integrated circuits that contain logic blocks and reconfigurable interconnect. Their ability to integrate more complex applications, their flexibility and good performance make FPGAs the perfect target architecture. The aim of this thesis is to propose an FPGA architecture containing mechanisms to tolerate more than 20% of defective resources after manufacture. The first part of the manuscript studies the different FPGA architectures (mesh and tree) and different defects bypass techniques. In the second part of this thesis, we present the target architecture called Mesh of Clusters (MoC). This architecture combines the advantages of mesh architectures (genericity) and tree (reduction of the interconnect). The third contribution of this thesis is the development of a method to identify the most critical blocks in the FPGA and the impact of all bypass techniques on the architecture and on the criticality. Finally, we define the performance of all bypass techniques in terms of defect tolerance, timing and area overhead. Finally, thanks to these local redundancy techniques, we are able to tolerate more than 20% of defect on the FPGA architecture. In addition, the designer can fix his own metric in terms of area, timing and defect tolerance
Pimenta, Valdiney Alves. "Metodologia Brazil-IP : registro do metodo e analise de casos de uso e experiencias ocorridas durante os trabalhos deste consorcio". [s.n.], 2008. http://repositorio.unicamp.br/jspui/handle/REPOSIP/276080.
Testo completoDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação
Made available in DSpace on 2018-08-11T08:21:02Z (GMT). No. of bitstreams: 1 Pimenta_ValdineyAlves_M.pdf: 5178774 bytes, checksum: 75a2335b2db0969f79ae380d7479bff2 (MD5) Previous issue date: 2008
Resumo: Contrariando as projeções para crescimento da economia mundial, o mercado de semicondutores cresce de forma acelerada, a uma taxa superior a 10% ao ano, movimentando anualmente mais de 270 bilhões de dólares. Acompanhando este crescimento, a importação de componentes eletrônicos pelo Brasil é um dos ítens que mais contribuem negativamente em sua balança comercial, deixando claro que o país não tem atuado de forma econômicamente interessante neste mercado. Um consórcio formado por 8 das principais universidades brasileiras, chamado BrazilIP, foi criado tendo como principal intuito inserir o Brasil no seleto grupo de países produtores de artefatos em semicondutores, em especial, na produção de componentes na forma de propriedade intelectual (IPs). Este grupo tem alcançado considerável sucesso ao longo dos últimos anos e é o foco da presente dissertação. O autor, que participou dos três primeiros anos de vida deste consór.cio, buscou registrar, na forma de método, as propostas, cursos, documentos e experiências ocorridas durante seu envolvimento. São também apresentados casos reais de aplicação da metodologia no desenvolvimento de um decoder de áudio MP3 e um codificador RSA. Uma das intenções deste trabalho é evitar que todo o conhecimento, adquirido e gerado pelo consórcio, se volatilize, além de permitir, através deste registro e exemplos de seu uso, que o método seja facilmente reaplicado em outras instituições de pesquisa. Somando-se a estas contribuições, didáticas e documentais, a dissertação ainda analisa vários pontos, positivos e negativos, sobre sua utilização e pioneirismo, propondo complementações e aprimoramentos
Abstract: Contrary to the projections ofthe worldwide economy's growth rate, the semiconductor market, estimated in 270 billions of dollars, grows over 10% each year. The electronic components market in Brazil has been growing at the same rate and poses a huge payout for the country in this area, leading to efforts in semiconductor training. The Brazil-IP consortium, formed by 8 of the major universities in Brazil, was created to try to insert the .country into the select group of countries that design semiconductors, focusing on intellectual property (IP) market. This group has achieved a considerable success over the past years and the systematization of its methodology is the focus of this dissertation. The contributions of this work are divided into three groups: (1) It registers the methodology in a reproducible way since the proposals, courses, documents and experiences that took place during the fist years were not put together. Since the author participated in the first three years, he is one of the recommended persons to do that. (2) It also exemplifies the methodology with real case studies, MP3 decoder and RSA, which is small enough to be used as first case exercise for new designers to be trained. (3) Finally it comments, makes suggestions and analyses the positive and negative points of the methodology as applied in the Institute of Computing, proposing enhancements and complementation
Mestrado
Sistemas de Computação
Mestre em Ciência da Computação
Srinivasan, Venkatesh. "Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning". Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11588.
Testo completoDoré, Jean-Baptiste. "Optimisation conjointe de codes LDPC (Low Density Parity Check) et de leurs architectures de décodage et mise en oeuvre sur FPGA (Field Programmable Gate Array)". Rennes, INSA, 2007. https://tel.archives-ouvertes.fr/tel-00191155v2.
Testo completoThe introduction of Turbo-codes in the early 90's and, more generally the iterative principle, has deeply modified the methods for the design of communication systems. This breakthrough has also resurrected the Low Density Parity Check (LDPC) codes invented by R. Gallager in 1963. Advanced channel coding techniques such as Turbo-codes and LDPC, are now increasingly considered for introduction into communication systems and standards. This evolution towards industrialization motivates the definition of new flexible and efficient decoding architecture for LDPC codes. In this thesis, we focus our research on the iterative decoding of LDPC codes and their hardware implementation. We first introduce basic concepts and notations for LDPC codes, which are necessary for a good comprehension. This introduction underlines the interest of jointly designing codes, decoding algorithm and architecture. From this perspective, a family of LDPC codes is described. We define some design rules to constrain the distance spectrum of the code. These constraints are introduced into a new algorithm for the design of the code working on a compact representation of the code graph. A new decoding algorithm is also defined, taking advantage of the intrinsic properties of the code structure. Convergence of the decoding algorithm is increased compared to classical decoding algorithm for LDPC codes. Performance and flexibility of this algorithm is discussed. Different architectures are then described and studied. Some constraints on the codes are derived to target an architecture. The last part of the thesis illustrates the implementation of one of the architectures discussed into a field-programmable gate array (FPGA). Performance and complexity measures are presented for various contexts, showing the interest of the concept for all these cases
Foote, David W. "The Design, Realization and Testing of the ILU of the CCM2 Using FPGA Technology". PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4703.
Testo completoHer, Shyang-Kuen. "Improved I/O pad positions assignment algorithm for sea-of-gates placement". PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/4316.
Testo completoChoudhary, Aarti. "A process variation tolerant self compensation sense amplifier design". Connect to this title, 2008. http://scholarworks.umass.edu/theses/166/.
Testo completoChoy, C. S. O. "A bipolar multilevel differential logic gate array". Thesis, University of Manchester, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.378029.
Testo completoMashayekhi, Mohammad. "Inkjet-configurable gate arrays: towards application specific printed electronic circuits". Doctoral thesis, Universitat Autònoma de Barcelona, 2016. http://hdl.handle.net/10803/402272.
Testo completoHonoré, Francis. "Energy-aware architectures, circuits and CAD for field programmable gate arrays". Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37911.
Testo completoIncludes bibliographical references (p. 113-117).
Field Programmable Gate Arrays (FPGAs) are a class of hardware reconfigurable logic devices based on look-up tables (LUTs) and programmable interconnect that have found broad acceptance for a wide range of applications. However, power consumption is one of the leading obstacles to broader adoption of FPGAs in energy-constrained applications. This thesis addresses active power consumption in FPGAs through the introduction of fine grain configurable power domains. By introducing fine grain power controls, sections of the design that have excess timing margins are able to run at reduced voltage thereby saving power. Delay critical sections can continue to operate at full voltage to maintain the overall performance of the design. A design flow was developed for the analysis and implementation of these configurable power domains. A test chip using dual core voltages fabricated in a 0.18 /m CMOS process features these power reduction techniques. The test chip includes an 8x8 array of logic tiles and a 9x9 switch matrix grid. The chip design flow utilizes a mix of synthesized logic and custom cells. 'The layout required a customized approach to overcome some of the challenges of implementing a fine granularity multiple voltage design.
(cont.) A set of benchmark circuits shows a measured average energy-delay improvement of nearly 2X. Additionally, enhancements for the implementation of finite impulse response filters provide a 2.5x improvement in the energy-delay product relative to standard FPGA architectures. This thesis also addresses static: power consumption by reducing sub-threshold leakage through the use of distributed multi-threshold CMOS. A separate test chip using a 0.13 m dual VT process demonstrates the advantages of distributed power gating for sub-threshold leakage reduction by achieving over 10X reduction in static power.
by Francis A. Honoré.
Ph.D.
Stamoulis, Iakovos. "Computer graphics hardware using ASICs, FPGAs and embedded logic". Thesis, University of Sussex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313943.
Testo completoGreen, A. D. P. "A percolation model for VLSI routing processes and its application in analysis and design of channelled structures". Thesis, University of Essex, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234181.
Testo completoZhang, Chengjin. "An investigation into the realisation and testing of a universal logic primitive gate array". Thesis, University of Bath, 1988. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.384137.
Testo completoClark, Christopher R. "A Unified Model of Pattern-Matching Circuits for Field-Programmable Gate Arrays". Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14138.
Testo completoSubramanian, Shyam. "Methods for synthesis of multiple-input translinear element networks". Diss., Atlanta, Ga. : Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22591.
Testo completoCommittee Chair: Anderson, David; Committee Member: Habetler, Thomas; Committee Member: Hasler, Paul; Committee Member: McClellan, James; Committee Member: Minch, Bradley.
MAL, PROSENJIT. "DESIGN AND DEMONSTRATION OF A MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE". University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1081274672.
Testo completo