Bibliografie tematiche / Field Programmable Gate Arrays

Indice

  1. Articoli di riviste
  2. Tesi
  3. Libri
  4. Capitoli di libri
  5. Atti di convegni
  6. Rapporti di organizzazioni

Letteratura scientifica selezionata sul tema "Field Programmable Gate Arrays"

Autore: Grafiati
Pubblicato: 4 giugno 2021
Ultima modifica: 29 luglio 2024

Cita una fonte nei formati APA, MLA, Chicago, Harvard e in molti altri stili

Scegli il tipo di fonte:

Consulta la lista di attuali articoli, libri, tesi, atti di convegni e altre fonti scientifiche attinenti al tema "Field Programmable Gate Arrays".

Accanto a ogni fonte nell'elenco di riferimenti c'è un pulsante "Aggiungi alla bibliografia". Premilo e genereremo automaticamente la citazione bibliografica dell'opera scelta nello stile citazionale di cui hai bisogno: APA, MLA, Harvard, Chicago, Vancouver ecc.

Puoi anche scaricare il testo completo della pubblicazione scientifica nel formato .pdf e leggere online l'abstract (il sommario) dell'opera se è presente nei metadati.

Articoli di riviste sul tema "Field Programmable Gate Arrays"

1

Marchal, Pierre. "Field-programmable gate arrays". Communications of the ACM 42, n. 4 (aprile 1999): 57–59. http://dx.doi.org/10.1145/299157.299594.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
2

Verma, H. "Field programmable gate arrays". IEEE Potentials 18, n. 4 (1999): 34–36. http://dx.doi.org/10.1109/45.796099.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
3

Lombardi, F. "Field Programmable Gate-Arrays". IEEE Design & Test of Computers 15, n. 1 (gennaio 1998): 8–9. http://dx.doi.org/10.1109/mdt.1998.655176.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
4

Bhatia, Dinesh. "Field-Programmable Gate Arrays". VLSI Design 4, n. 4 (1 gennaio 1996): i—ii. http://dx.doi.org/10.1155/1996/87608.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
5

Hurst, S. L. "Field programmable gate arrays". Microelectronics Journal 28, n. 1 (gennaio 1997): 102. http://dx.doi.org/10.1016/s0026-2692(97)87854-8.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
6

Hurst, S. L. "Field-programmable gate arrays". Microelectronics Journal 25, n. 1 (febbraio 1994): 77–78. http://dx.doi.org/10.1016/0026-2692(94)90166-x.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
7

Jay, Christopher. "Field programmable gate arrays". Microprocessors and Microsystems 17, n. 7 (settembre 1993): 370. http://dx.doi.org/10.1016/0141-9331(93)90058-f.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
8

Greene, J., E. Hamdy e S. Beal. "Antifuse field programmable gate arrays". Proceedings of the IEEE 81, n. 7 (luglio 1993): 1042–56. http://dx.doi.org/10.1109/5.231343.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
9

Leon, A. F. "Field programmable gate arrays in space". IEEE Instrumentation & Measurement Magazine 6, n. 4 (dicembre 2003): 42–48. http://dx.doi.org/10.1109/mim.2003.1251482.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
10

Rose, J., A. El Gamal e A. Sangiovanni-Vincentelli. "Architecture of field-programmable gate arrays". Proceedings of the IEEE 81, n. 7 (luglio 1993): 1013–29. http://dx.doi.org/10.1109/5.231340.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
Più fonti

Tesi sul tema "Field Programmable Gate Arrays"

1

Howard, Neil John. "Defect-tolerant Field-Programmable Gate Arrays". Thesis, University of York, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.359290.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
2

Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach". Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.

Testo completo
Abstract (sommario):
Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.
Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.
Gli stili APA, Harvard, Vancouver, ISO e altri
3

Leong, David Chin Kuang. "Incremental placement for field-programmable gate arrays". Thesis, University of British Columbia, 2006. http://hdl.handle.net/2429/31671.

Testo completo
Abstract (sommario):
As the logic capacity of FPGAs continues to increase with deep submicron technology, performing a full recompilation for small iterative changes in a large design is an extremely time-consuming and costly process. To address this issue, this thesis presents a new incremental placement algorithm for FPGAs named "iPlace" that significantly reduces the time required for recompilation. The iPlace algorithm is based on shifting, compaction, and annealing. Key ideas from the algorithm include a placement super-grid that is larger than the physical size of the FPGA. The super-grid allows insertion of additional CLBs into areas with no free locations by CPU-efficient shifting. This is followed by a compaction scheme to re-legalize CLBs that are shifted to illegal locations outside of the physical size of the FPGA. The algorithm ends with a low-temperature anneal to improve quality. This algorithm is capable of handling multiple design changes across large regions of a FPGA. This is especially useful for hierarchical designs where sub-circuits are re-used multiple times. If one such sub-circuit is modified, iPlace can quickly produce a high quality incremental placement solution. For a single region of design change, we found that iPlace is 34 to 260 times faster than the academic tool Versatile Place and Route (VPR) in default mode. Compared to VPR's reduced-quality "-fast" placement option, iPlace is 3 to 28 times faster with equivalent quality. For multiple regions of design changes, iPlace is still 50-70 times faster compared to VPR in default mode when up to 2/3 of the CLBs are modified; Compared to the "-fast" placement option, iPlace is still 5-8 times faster. We believe that iPlace is the first academically available incremental placement algorithm capable of handling significant changes to a netlist for very large circuits.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
Gli stili APA, Harvard, Vancouver, ISO e altri
4

Messa, Norman C. "Design implementation into field programmable gate arrays". Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/26451.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
5

Niu, Jianyong. "Digital control using field programmable gate arrays". Thesis, University of Sheffield, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.434507.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
6

Lu, Aiguo. "Logic synthesis for field programmable gate arrays". Thesis, University of Bristol, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295061.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
7

Newalkar, Aditya. "Alternative techniques for Built-In Self-Test of Field Programmable Gate Arrays". Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Summer/master's/NEWALKAR_ADITYA_6.pdf.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
8

Карнаушенко, В. П., e А. В. Бородин. "Field Programmable Counter Arrays Integration with Field Programmable Gates Arrays". Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-004.

Testo completo
Abstract (sommario):
Field Programmable Counter Arrays (FPCAs) have been recently introduced to close the gap between Field Programmable Gates Arrays (FPGA) and Application Specified Integrated Circuits (ASICs) for arithmetic dominated applications. FPCAs are reconfigurable lattices that can be embedded into FPGAs to efficiently compute the result of multi-operand additions.
Gli stili APA, Harvard, Vancouver, ISO e altri
9

Vachranukunkiet, Petya Nagvajara Prawat Johnson Jeremy. "Power flow computation using field programmable gate arrays /". Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1789.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
10

Camus, Dominic Roger. "Improved logic optimisation for field programmable gate arrays". Thesis, University of Oxford, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301840.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
Più fonti

Libri sul tema "Field Programmable Gate Arrays"

1

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. Field-Programmable Gate Arrays. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
2

D, Brown Stephen, a cura di. Field-programmable gate arrays. Boston: Kluwer Academic Publishers, 1992.

Cerca il testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
3

Brown, Stephen D. Field-Programmable Gate Arrays. Boston, MA: Springer US, 1992.

Cerca il testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
4

1955-, Trimberger Stephen, a cura di. Field-programmable gate array technology. Boston: Kluwer Academic Publishers, 1994.

Cerca il testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
5

Murgai, Rajeev. Logic synthesis for field-programmable gate arrays. Boston: Kluwer Academic Publishers, 1995.

Cerca il testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
6

Ukeiley, Richard Larry. Field programmable gate arrays (FPGAs): The 3000 series. Englewood Cliffs, N.J: PTR Prentice Hall, 1993.

Cerca il testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
7

Murgai, Rajeev, Robert K. Brayton e Alberto Sangiovanni-Vincentelli. Logic Synthesis for Field-Programmable Gate Arrays. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2345-1.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
8

Vuillamy, Jean-Michel. Performance enhancement in field-programmable Gate Arrays. Ottawa: National Library of Canada, 1991.

Cerca il testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
9

Messa, Norman C. Design implementation into field programmable gate arrays. Monterey, Calif: Naval Postgraduate School, 1991.

Cerca il testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
10

Murgai, Rajeev. Logic Synthesis for Field-Programmable Gate Arrays. Boston, MA: Springer US, 1995.

Cerca il testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
Più fonti

Capitoli di libri sul tema "Field Programmable Gate Arrays"

1

Gu, Changyi. "Field-Programmable Gate Arrays". In Building Embedded Systems, 191–231. Berkeley, CA: Apress, 2016. http://dx.doi.org/10.1007/978-1-4842-1919-5_9.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
2

Barkalov, Alexander, Larysa Titarenko e Małgorzata Mazurkiewicz. "Field Programmable Gate Arrays". In Foundations of Embedded Systems, 81–106. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-11961-4_4.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
3

de Dinechin, Florent, e Martin Kumm. "Field Programmable Gate Arrays". In Application-Specific Arithmetic, 87–100. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-42808-1_4.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
4

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. "Introduction to FPGAs". In Field-Programmable Gate Arrays, 1–11. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_1.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
5

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. "Commercially Available FPGAs". In Field-Programmable Gate Arrays, 13–43. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_2.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
6

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. "Technology Mapping for FPGAs". In Field-Programmable Gate Arrays, 45–86. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_3.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
7

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. "Logic Block Architecture". In Field-Programmable Gate Arrays, 87–115. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_4.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
8

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. "Routing for FPGAs". In Field-Programmable Gate Arrays, 117–45. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_5.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
9

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. "Flexibility of FPGA Routing Architectures". In Field-Programmable Gate Arrays, 147–67. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_6.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
10

Brown, Stephen D., Robert J. Francis, Jonathan Rose e Zvonko G. Vranesic. "A Theoretical Model for FPGA Routing". In Field-Programmable Gate Arrays, 169–90. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0_7.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri

Atti di convegni sul tema "Field Programmable Gate Arrays"

1

Jyothi, Vinayaka, Ashik Poojari, Richard Stern e Ramesh Karri. "Fingerprinting Field Programmable Gate Arrays". In 2017 IEEE 35th International Conference on Computer Design (ICCD). IEEE, 2017. http://dx.doi.org/10.1109/iccd.2017.58.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
2

DeHon, A. "Entropy, Counting, and Programmable Interconnect". In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242346.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
3

Pérez López, Daniel, Aitor López Hernández, Andrés Macho Ortiz, Prometheus DasMahapatra e José Capmany Francoy. "Towards field-programmable photonic gate arrays". In Smart Photonic and Optoelectronic Integrated Circuits XXII, a cura di Sailing He e Laurent Vivien. SPIE, 2020. http://dx.doi.org/10.1117/12.2551289.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
4

Chow, P., P. G. Gulak e P. Chow. "A Field-Programmable Mixed-Analog-Digital Array". In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.242048.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
5

Lombardi, F., D. Ashen, Xiaotao Chen e Wei Kang Huang. "Diagnosing Programmable Interconnect Systems for FPGAs". In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242436.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
6

Tong Liu, Wei Kang Huang e F. Lombardi. "Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays". In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.242145.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
7

Vi Cuong Chan e D. M. Lewis. "Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays". In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242343.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
8

Lamoureux, Julien, e Steven Wilton. "Activity Estimation for Field-Programmable Gate Arrays". In 2006 International Conference on Field Programmable Logic and Applications. IEEE, 2006. http://dx.doi.org/10.1109/fpl.2006.311199.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
9

Bratt, A., e I. Macbeth. "Design and Implementation of a Field Programmable Analogue Array". In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242434.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
10

Chan, Pak K., e Martine D. F. Schlag. "Parallel placement for field-programmable gate arrays". In the 2003 ACM/SIGDA eleventh international symposium. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/611817.611825.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri

Rapporti di organizzazioni sul tema "Field Programmable Gate Arrays"

1

Mumbru, Jose, George Panotopoulos e Demetri Psaltis. Optically Programmable Field Programmable Gate Arrays (FPGA) Systems. Fort Belvoir, VA: Defense Technical Information Center, gennaio 2004. http://dx.doi.org/10.21236/ada421336.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
2

Stepaniak, Michael J., Maarten Uijt de Haag e Frank Van Graas. Field Programmable Gate Array-Based Attitude Stabilization. Fort Belvoir, VA: Defense Technical Information Center, luglio 2008. http://dx.doi.org/10.21236/ada485525.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
3

Manohar, Rajit. Experimental 3D Asynchronous Field Programmable Gate Array (FPGA). Fort Belvoir, VA: Defense Technical Information Center, marzo 2015. http://dx.doi.org/10.21236/ada614130.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
4

Wawrzynek, J., e K. Asanovic. Field-Programmable Gate Array (FPGA) Emulation for Computer Architecture. Fort Belvoir, VA: Defense Technical Information Center, agosto 2009. http://dx.doi.org/10.21236/ada519578.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
5

Tyler, Stephen C. The Design of a Frequency Domain Interference Excision Processor Using Field Programmable Gate Arrays. Fort Belvoir, VA: Defense Technical Information Center, gennaio 2005. http://dx.doi.org/10.21236/ada432369.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
6

Wirthlin, Michael, Brent Nelson, Brad Hutchings, Peter Athanas e Shawn Bohner. Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows. Fort Belvoir, VA: Defense Technical Information Center, luglio 2008. http://dx.doi.org/10.21236/ada492273.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
7

Manohar, Rajit. A Secure and Reliable High-Performance Field Programmable Gate Array for Information Processing. Fort Belvoir, VA: Defense Technical Information Center, marzo 2012. http://dx.doi.org/10.21236/ada559184.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
8

Learn, Mark Walter. Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array. Office of Scientific and Technical Information (OSTI), aprile 2011. http://dx.doi.org/10.2172/1013229.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
9

Lin, Chun-Shin. High Speed Publication Subscription Brokering Through Highly Parallel Processing on Field Programmable Gate Array (FPGA). Fort Belvoir, VA: Defense Technical Information Center, gennaio 2010. http://dx.doi.org/10.21236/ada514601.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
10

Bobrek, Miljko, Don Bouldin, David Eugene Holcomb, Stephen M. Killough, Stephen Fulton Smith e Christina D. Ward. Survey of Field Programmable Gate Array Design Guides and Experience Relevant to Nuclear Power Plant Applications. Office of Scientific and Technical Information (OSTI), settembre 2007. http://dx.doi.org/10.2172/991174.

Testo completo
Gli stili APA, Harvard, Vancouver, ISO e altri
Ti possono interessare anche gli elenchi estesi di opere sul tema "Field Programmable Gate Arrays":
Articoli di riviste Tesi Libri
Offriamo sconti su tutti i piani premium per gli autori le cui opere sono incluse in raccolte letterarie tematiche. Contattaci per ottenere un codice promozionale unico!

Vai alla bibliografia