Tesi sul tema "Electronic board design"
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1
McCalib, David Jr. "Design method of a modular electronic printed circuit board testing system". Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/85790.
Testo completoAbstract (sommario):
Thesis: M. Eng. in Manufacturing, Massachusetts Institute of Technology, Department of Mechanical Engineering, 2013.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 52-54).
The failure rate of the printed circuit board electronic testing process is higher than acceptable at a Lenze Americas factory. This thesis will understand the root causes of failure, and use system engineering methods to decide what course of action should be taken. A Tradespace analysis is used to help decompose some of the complexity into a visualization that simplifies the decision process. The Tradespace analysis suggests that more utility can be achieved by upgrading the design of existing test fixtures versus purchasing off of the shelf solutions. The second phase will identify a design concept, offer specific design solutions, and finally a fully designed system that is capable of improving the performance of the test fixtures in electronic board test area by 50%. The system is then upgradable with in-line conveyors to run autonomously decoupling the operator from the process.
by David McCalib, Jr.
M. Eng. in Manufacturing
2
Andersson, Peter. "Design of a channel board used in an electronic warfare target simulator". Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7529.
Testo completoAbstract (sommario):
A channel board was designed for a DRFM circuit. The DRFM is implemented in a Virtex-4 FPGA from Xilinx. In the future a similar channel board is intended to be used for target echo generation in ELSI which is an electronic warfare simulator at Saab Bofors Dynamics in Linköping.
Besides the DRFM circuit the channel board consists of analog-to-digital converters, digital-to-analog converters, Ethernet plug-in board with a microcontroller, voltage regulators, FPGA configuration memory, voltage amplifiers, current amplifiers, oscillator, buffers/drivers and bus transceivers. The sample rate is 200 MHz and LVDS signalling standard is used between the DRFM circuit and the converters.
The channel board has a JTAG interface which enables in-system programming of the FPGA. This implies that the DRFM can easily be redesigned. An external computer can manage the channel board via Ethernet. Software was developed for the microcontroller on the channel board and for the external computer. The function of the channel board is heavily dependent on the DRFM circuit.
The channel board design resulted in the assembly of a prototype circuit board. Measurements were performed in a lab and the channel board was approved to be integrated in ELSI for further tests.
3
Shina, Sammy G. "A design quality and cost model for printed circuit board assembly /". Thesis, Connect to Dissertations & Theses @ Tufts University, 1998.
Cerca il testo completoAbstract (sommario):
Thesis (Ph.D.)--Tufts University, 1998.Adviser: Anil Saigal. Submitted to the Dept. of Mechanical Engineering. Includes bibliographical references. Access restricted to members of the Tufts University community. Also available via the World Wide Web;
4
Alalait, Suliman. "The design and implementation of a video compression development board". Thesis, Stellenbosch : University of Stellenbosch, 2011. http://hdl.handle.net/10019.1/6547.
Testo completoAbstract (sommario):
Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2011.This thesis describes the design and implementation of a video compression development board as a standalone embedded system. The board can capture images, encode them and stream out a video to a destination over a wireless link. This project was done to allow users to test and develop video compression encoders that are designed for UAV applications. The board was designed to use an ADSP-BF533 Blackfin DSP from Analog Devices with the purpose of encoding images, which were captured by a camera module and then streamed out a video through a WiFi module. Moreover, an FPGA that has an interface to a logic analyzer, the DSP, the camera and the WiFi module, was added to accommodate other future uses, and to allow for the debugging of the board. The board was tested by loading a H.264 BP/MP encoder from Analog Devices to the DSP, where the DSP was integrated with the camera and the WiFi module. The test was successful and the board was able to encode a 2 MegaPixel picture at about 2 frames per second with a data rate of 186 Kbps. However, as the frame rate was only 2 frames per second, the video was somewhat jerky. It was found that the encoding time is a system limitation and that it has to be improved in order to increase the frame rate. A proposed solution involves dividing the captured picture into smaller segments and encoding each segment in parallel. Thereafter, the segments can be packed and streamed out. Further performance issues about the proposed structure are presented in the thesis.
5
Chen, Ruijun. "Fixturing analysis and synthesis for flexible circuit board assembly". Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/17866.
Testo completo
6
Brownlee, Kellee Renee. "Evaluation of low stress dielectrics for board applications". Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/20040.
Testo completo
7
Arn, Krissa Elizabeth 1980. "Design of a non-contact vibration measurement and analysis system for electronic board testing". Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/18070.
Testo completoAbstract (sommario):
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2004.Includes bibliographical references (p. 107).
Traditional vibration measurement methods involve placing accelerometers at discrete locations on a test object. In cases where the test specimen is small in mass, the addition of these measurement transducers can alter its dynamic behavior and lead to erroneous test data. In this thesis a Non-Contact Vibration Measurement and Analysis System has been designed, built, and tested for electronic board testing. Through a product design process, all feasible methods were considered and three optically based concepts were explored: holographic interferometry, area scaling, and displacement sensor grid. Through concept testing and analysis, the displacement sensor grid method was chosen for the design. The final system incorporates four laser displacement sensors with a vertical scrolling mechanism that attaches to the vibration table's side rails. This manual scanning system provides a quick, low cost method for capturing multiple points on the test object during vibration testing. The MATLAB based software package acquires the raw sensor output and processes it with a five step analysis program. With this software, an 8x4 grid of electronic board displacements were easily transformed into a movie showing the board displacing through its first mode. The system requires the sensors be positioned lcm away from the test object with the sensors reading up to [plus-minus]lmm of movement. The sensors have a maximum sample rate of 7.8 kHz and can be used to measure the displacements of any surface type or material. The measurement grid resolution is 0.7 inches horizontally 0.4 inches vertically. Testing showed that the system captured the natural frequency and peak displacement of the board's first mode within 1.5% accuracy and 0.7% accuracy respectively
(cont.) when compared with previous accelerometer grid testing. Exceeding its design goals, this non-contact measurement and analysis device provides a highly versatile, accurate, and low cost optical alternative to accelerometers. Also it shows numerous benefits over more complex and costly optical measurement methods. The use of this system eliminates any question of whether mass loading effects are tainting vibration test data. A hardware and software manual are included for reference at the end of this thesis along with a software CD.
by Krissa Elizabeth Arn.
S.M.
8
Grobler, H. "Aspects affecting the design of a low earth orbit satellite on-board computer". Thesis, Stellenbosch : Stellenbosch University, 2000. http://hdl.handle.net/10019.1/51621.
Testo completoAbstract (sommario):
Thesis (MEng)--University of Stellenbosch, 2000.ENGLISH ABSTRACT: Satellites are not all made equal. The large number of possible orbits, desired functionality and budget constraints are but a few of the factors that influence the design of a satellite. Given a particular set of design requirements, a number of designs may meet these requirements. Each of these designs will typically entail a trade-off between a number of (conflicting) parameters, whilst still satisfying the system requirements. The On-Board Computer (OBC) of a satellite, the satellite subsystem primarily responsible for the operational control of a satellite, can consequently be designed in any of a number of different ways. As the factors that influence the flight performance of an OBC differs to those of a terrestrial computer, the OBC design will therefore be significantly different. A high-level overview of the factors that impact OBC design and operation is presented. Improvements to the existing designs are proposed. In conclusion, a number of guidelines for a future OBC design also are given.
AFRIKAANSE OPSOMMING: Elke satelliet het unieke eienskappe wat bepaal word deur onderandere, die teiken wentelbaan, verwagte funksionaliteit en koste oorweegings. Vir 'n spesefieke stelselontwerp bestaan daar 'n aantal moontlike ontwerpe wat aan die stelsel vereistes voldoen. Elk van hierdie ontwerpe sal tipies behels dat verskillende parameters teen mekaar afgespeel word, terwyl die stelsel vereistes steeds aan voldoen word. Die Aanboord Rekenaar (AR) van 'n satelliet, die satelliet substelsel hoofsaaklik verantwoordelik vir die beheer van die satelliet, kan vervolgens uit een van veele moontlike ontwerpe bestaan. Aangesien die faktore wat die werkverrigting van 'n AR beinvloed verskil van die van 'n rekenaar wat op die aard oppervlak gebruik word, sal die AR ontwerp dienooreenkomstig verskil. 'n Hoevlak oorsig van die faktore wat AR ontwerp beinvloed sal gegee word. Verbeteringe wat aan die huidige AR ontwerpe gedoen kan word sal bespreek word. Ter afsluiting sal 'n aantal riglyne vir toekomstige AR ontwerpe gegee word.
9
Rajagopal, Abhilash. "Printed circuit board (PCB) loss characterization up-to 20 GHz and modeling, analysis and validation". Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Rajagopal_09007dcc803bf920.pdf.
Testo completoAbstract (sommario):
Thesis (M.S.)--University of Missouri--Rolla, 2007.Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 26, 2007) Includes bibliographical references (p. 112-113).
10
Hari, Krishnan Prem Kumar. "Design and Analysis of a Dynamic SpaceWire Routing Protocol for Reconfigurable and Distributed On-Board Computing Systems". Thesis, Luleå tekniska universitet, Rymdteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-76534.
Testo completoAbstract (sommario):
Future spacecrafts will require more computational and processing power to keep up with the growing demand in requirements and complexity. ScOSA is the next generation on-board computer developed by the German Aerospace Centre (DLR). The main motivation behind ScOSA is to replace the conventional on-board computer with distributed and reconfigurable computing nodes which provides higher performance, reliability, availability and stability by using a combination of the COTS components and reliable computing processors that are space qualified. In the current ScOSA system reconfiguration and routing of data between nodes are based on a static decision graph. SpaceWire protocol is used to communicate between nodes to provide reliability. The focus of the thesis is to design and implement a dynamic routing protocol for ScOSA which can be used in future for not only communicating between the nodes but also for reconfiguration. SpaceWire IPC is a customized protocol developed by DLR to provide communication between the nodes in a distributed network and to support monitoring, management and reconfiguration services. The dynamic routing protocol proposed in this thesis is primarily derived from the monitoring mechanism used in the SpaceWire IPC. PULL type monitoring mechanism is modelled and simulated using OMNeT++. The results obtained provide a qualitative outlook of the dynamic routing protocol implemented.
11
Rosenkvist, Daniel, e Johan Eriksson. "Design and test of SiC circuit board for MIST satellite : KTH Student Satellite MIST". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-210666.
Testo completoAbstract (sommario):
This paper describes work related to the “Miniature Student Satellite” (MIST) project and the ”SiC in Space” project, located at KTH, Stockholm, Sweden. The goal of the MIST project is to launch KTH’s first student satellite into space, carrying multiple scientific experiments where SiC in Space is included. This thesis contains a compilation of three MIST-related bachelor theses that were carried out at KTH in the spring of 2016, primarily consisting of constructing and testing circuits for power supply and measurements for the SiC in Space part of the satellite. A printed circuit board has been developed, which accommodates experiment circuits to evaluate the features and functionality of silicon carbide components in a space environment, and power the supply to the SiC in Space and the Piezo LEGS projects. The development includes designing, assembling and testing the PCB according to the MIST team’s demands and requirements. Emphasis has been laid on electrical safety to ensure that the design can not short circuit the satellite battery, as well as EMC considerations to minimize the EMI between different parts of the satellite. Final testing of the hardware has not been executed due to an ordering error and time shortage, wherefore the planned test protocol has been included for future work.Denna kandidatuppsats beskriver arbete relaterat till “Miniature Student Satellite” (MIST)-, samt SiC in Space-projekten, vid KTH, Stockholm, Sverige. MIST-projektets mål är att skicka KTH:s första studentsatellit till rymden, där SiC in Space är ett av flera medföljande vetenskapliga experiment. Detta projekt sammanställer tre examensarbeten relaterade till MIST som genomfördes vid KTH under våren 2016, huvudsakligen bestående av att konstruera och testa kretsar för strömförsörjning samt mätningar för SiC in Space-delen av satelliten. Ett kretskort som innehåller experimentkretsar för att utvärdera egenskaper och funktionalitet för komponenter av materialet kiselkarbid i en rymdmiljö, samt strömförsörjningskretsar till SiC in Space- och Piezo LEGS-projekten har utvecklats. Utvecklingen omfattar design, montering and testning av kretskortet enligt MIST-gruppens krav. Tonvikt har lagts på elsäkerhet för att säkerställa att designen inte kan kortsluta satellitens batteri, såväl som EMC för att minimera EMI mellan olika delar av satelliten. Slutgiltig testning av hårdvaran har ej kunnat genomföras på grund av tidsbrist beroende på ett beställningsfel. Därför har det planerade testprotokollet inkluderats för framtida arbete.
12
Machuca, Julían, e Thomas Tuvesson. "PCB design of Power Distributor Unit (PDU)". Thesis, Uppsala universitet, Institutionen för elektroteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-415474.
Testo completoAbstract (sommario):
The project idea was created from the demand of a renewal for a Power Distributor Unit also known as a PDU. The current product had successively turned in to a cable mess because of short term solutions. This made the product non user friendly, inconvenient and non-agile to handle troubleshooting. To develop this project, a PCB design was created by simplifying and improving circuit diagrams until satisfied. Once the final circuit diagram was obtained, a PCB layout design was created. The result of the project, due to limited time, was only theoretical. The finished product was not tested as there was no time allowing this.
13
Wood, Matthew. "Analysis of near fields and radiation of a printed circuit via hole". University of Western Australia. School of Electrical, Electronic and Computer Engineering, 2008. http://theses.library.uwa.edu.au/adt-WU2009.0053.
Testo completoAbstract (sommario):
Electromagnetic compatibility remains an important topic in the design and manufacturing of printed circuit boards (PCBs). Compatibility of these devices with their surroundings is becoming increasingly difficult as a modern PCB can have hundreds or thousands of parts, operating on many layers, and all at high speed. One such part is a via and its clearance, or via hole, commonly required in multilayer circuits where vertical connections between layers are used. The via hole may be exposed to large electromagnetic fields within the PCB. Although electrically small, the via hole provides a pathway for the fields to excite the exterior, either directly or through coupling to adjacent structures. To quantify this process, the near fields and radiation of an excited via hole are analysed, and are the focus of this thesis. The near fields of the via hole are first decoupled into electric and magnetic fields of the 'static' type. In both cases a series solution for two regions, one outside, and one inside the layers is constructed. The coefficients of the terms of the series are chosen to best satisfy the boundary behaviour of the fields on the conducting surfaces and across the hole. The criteria for assessing quality of the solution is based on the least squares method (LSM). Linear equation systems for both models are derived, and as no numerical integration or discretisation is required, an efficient and robust implementation to find the near fields is developed. Transformation into the far field is then achieved through surface integration of relevant field quantities close to the via hole. The far fields are best viewed as that due to two dipoles, of the magnetic and electric type, with strength and orientation depending on how the via hole is excited. It is shown that the two dipole model is sufficient to find the radiation from a 1mm diameter via hole at a frequency up to 8 GHz. Of further interest is how the choice of via hole dimensions affects the dipole moments and the near fields solved earlier are a key to this understanding.
14
Fouquet, Marc. "Earth imaging with microsatellites : an investigation, design, implementation and in-orbit demonstration of electronic imaging systems for Earth observation on-board low-cost microsatellites". Thesis, University of Surrey, 1995. http://epubs.surrey.ac.uk/844455/.
Testo completoAbstract (sommario):
This research programme has studied the possibilities and difficulties of using 50 kg microsatellites to perform remote imaging of the Earth. The design constraints of these missions are quite different to those encountered in larger, conventional spacecraft. While the main attractions of microsatellites are low cost and fast response times, they present the following key limitations: Payload mass under 5 kg, Continuous payload power under 5 Watts, peak power up to 15 Watts, Narrow communications bandwidths (9.6 / 38.4 kbps), Attitude control to within 5°, No moving mechanics. The most significant factor is the limited attitude stability. Without sub-degree attitude control, conventional scanning imaging systems cannot preserve scene geometry, and are therefore poorly suited to current microsatellite capabilities. The foremost conclusion of this thesis is that electronic cameras, which capture entire scenes in a single operation, must be used to overcome the effects of the satellite's motion. The potential applications of electronic cameras, including microsatellite remote sensing, have erupted with the recent availability of high sensitivity field-array CCD (charge-coupled device) image sensors. The research programme has established suitable techniques and architectures necessary for CCD sensors, cameras and entire imaging systems to fulfil scientific/commercial remote sensing despite the difficult conditions on microsatellites. The author has refined these theories by designing, building and exploiting in-orbit five generations of electronic cameras. The major objective of meteorological scale imaging was conclusively demonstrated by the Earth imaging camera flown on the UoSAT-5 spacecraft in 1991. Improved cameras have since been carried by the KITSAT-1 (1992) and PoSAT-1 (1993) microsatellites. PoSAT-1 also flies a medium resolution camera (200 metres) which (despite complete success) has highlighted certain limitations of microsatellites for high resolution remote sensing. A reworked, and extensively modularised, design has been developed for the four camera systems deployed on the FASat-Alfa mission (1995). Based on the success of these missions, this thesis presents many recommendations for the design of microsatellite imaging systems. The novelty of this research programme has been the principle of designing practical camera systems to fit on an existing, highly restrictive, satellite platform, rather than conceiving a fictitious small satellite to support a high performance scanning imager. This pragmatic approach has resulted in the first incontestable demonstrations of the feasibility of remote sensing of the Earth from inexpensive microsatellites.
15
Hajjar, Gabriel. "Design and construction of a photoplotter : Building a device for rapid prototyping of PCBs". Thesis, Uppsala universitet, Fasta tillståndets fysik, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-354717.
Testo completoAbstract (sommario):
The goal was to build a machine that could rapidly prototype PCBs using a moving light source and photoresist. The project failed, as the UV light did not make it through the lenses used to concentrate it. Better lenses and a laser would allow it to function better.
16
Camilo, Edson 1959. "Propostas de design de layout da PCI para redução de curto circuito de solda a onda, para processo de montagem de placa eletrônica = PCB layout design techniques for shortcircuit (bridging) reduction due to wave soldering in electronic board assembly". [s.n.], 2015. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260044.
Testo completoAbstract (sommario):
Orientador: Yuzo IanoDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação
Made available in DSpace on 2018-08-27T18:51:43Z (GMT). No. of bitstreams: 1 Camilo_Edson_M.pdf: 3518346 bytes, checksum: 0264cd60aaed512cef0dacda58a43540 (MD5) Previous issue date: 2015
Resumo: Este trabalho de Mestrado tem como objetivo contribuir para a área de placa de circuito impresso no que se refere ao projeto de layout focado não só em satisfazer as conexões das trilhas, mas nas regras de projeto com foco na redução de curto circuito de solda para o processo de solda por onda. Projetos de PCB (Printed Circuit Board) ou PCI (Placa de Circuito Impresso) envolvem uma série de conhecimentos no que se refere ao entendimento das funcionalidades dos circuitos e para tanto é importante que se faça o correto posicionamento dos componentes em grupos de circuitos pela funcionalidade; além disso, é importante que se conheça as regras de capacidade de corrente, de distâncias de isolação em função das tensões aplicadas, características de impedância, áreas de restrição mecânica entre outras. O que será visto neste trabalho está focado na aplicação de conceitos e considerações ligadas ao processo de montagem da placa eletrônica por solda a onda. Muitos dos defeitos que ocorrem num processo de montagem da PCB são atribuídos ao processo de montagem da PCB como, por exemplo, a temperatura da solda, o tempo de solda, quantidade de fluxo aplicado na placa, altura da onda de solda, etc. Recomendações sobre posicionamento de componentes PTH (Pin Through Hole) e SMD (Surface Mounting Devise) em relação ao sentido em que a PCB entra em direção à solda a onda, recursos de aplicação de serigrafia, tipos de laminados, de formato das ilhas de solda, adição de técnica de ladrão de solda e as recomendações da IPC (Association Connecting Electronics Industries) serão descritos neste trabalho. O correto entendimento dos defeitos que ocorrem durante o processo de montagem da PCB reflete na constante melhoria e aperfeiçoamento do projeto do layout da placa, que por sua vez resulta num processo de montagem de placa com menos ocorrência de defeitos de fabricação e consequentemente melhor qualidade do produto. Menos retrabalho nas PCBs significa menos custo de produção que reflete em maior lucro para as empresas. As propostas apresentadas neste trabalho são fruto de resultados práticos vivenciados na indústria e de pesquisa em literatura dos assuntos relacionados a defeitos em PCB e processos de solda por onda. O conjunto destas recomendações e seus resultados estão aqui descritos e ilustrados para servirem de referência aos futuros pesquisadores e leitores
Abstract: This work aims to contribute to the area of the printed circuit board in regard to layout design focused not only on satisfying the connections of the tracks but the design rules focused on reducing short- circuit solder for wave solder process . Projects PCB (Printed Circuit Board) involve a lot of knowledge when it comes to understanding the features of both circuit and is important to make the correct positioning of components into groups of circuits for feature addition is important to know the rules of current capacity, isolation distances depending on the applied voltage, impedance characteristics, areas of mechanical restrictions among others. What will be seen in this work is focused on application of concepts and considerations involved in the process of mounting the electronic board by solder wave. Many of the defects which occur in the process of assembling the PCB are assigned to the PCB assembly process such as the temperature of the solder, weld time , amount of flux applied to the board, solder wave height, etc. Recommendations on positioning components PTH( Pin Through Hole) and SMD( Surface Mounting Devise) relative to the direction in which the PCB goes toward the wave solder , screen printing application features , format type of solder lands , techniques of solder thief and the IPC ( Association Connecting Electronics Industries) recommendations will be described on this work . The correct understanding of the defects that occur during the assembly process of the PCB reflects on constant improvement and refinement of the board layout design, which in turn results in a process of mounting plate with fewer occurrences of defects in workmanship and consequently better quality product. Less rework means less PCBs in production cost which reflects in higher profits for companies. The proposals presented in this paper are the result of practical results experienced in industry and research literature on the subjects related to defects in PCB and wave solder processes. All these recommendations and their results are described and illustrated to better serve as reference for future researchers and readers
Mestrado
Telecomunicações e Telemática
Mestre em Engenharia Elétrica
17
Ström, Simon, e Ali Qhorbani. "Automation of the design process of printed circuit boards : Determining minimum distance required by auto-routing software". Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-251925.
Testo completoAbstract (sommario):
This thesis project aims to create an overview of new technologies in printed circuit board manufacturing which when automated could become part of an Industry 4.0 production flow. Potential design limits imposed by new technologies are then applied in the creation process of a minimum distance estimation function. The intended purpose of this function is to correctly estimate the minimum distance required for the auto-routing software FreeRouting to be able to successfully route between two components. This is achieved by using a brute-force attack to progressively decrease the distance between components using a bisectional approach to find the minimum distance at which the auto-routing software can still successfully route for a specific design. Using the results from this brute-force attack a couple of linear functions based on different base designs are created and then used to implement a minimum distance function. The minimum distance estimation function is then intended to be used to implement limits to how close components can be placed to each other in a printed circuit board design tool which purpose is to enable people with lesser knowledge of printed circuit boards to still be able to realize their design ideas.Detta examensarbete ämnar skapa en överblick av nya tekniker inom mönsterkorts-tillverkning som när de automatiseras skulle kunna bli en del av ett Industri 4.0 produktionsflöde. Eventuella designbegränsningar som uppstår till följd av dessa tekniker kommer sedan appliceras i skapningsprocessen av en minsta avståndsfunktion. Syftet med denna funktion är att korrekt uppskatta det minimala avståndet som krävs för att auto-routing mjukvaran FreeRouting ska kunna dra ledningar mellan två komponenter. Detta görs genom en brute-force attackvinkel där avståndet mellan komponenter fortsätter minskas med bisektionsmetoden tills ett minsta avstånd hittats där auto-routing mjukvaran fortfarande kan dra ledningar för en specifik design. Genom användande av resultaten från denna brute-force attack skapas sedan ett par linjära funktioner baserade på olika bas-designer och dessa används sedan för att implementera minsta avståndsfunktionen. Denna minsta avståndet-funktion är sedan ämnad att implementeras som begränsningar för hur nära komponenter kan placeras varandra i ett program för design av mönsterkort vars syfte är att möjliggöra folk utan kunskaper inom mönsterkortsdesign att ändå kunna realisera sina designidéer.
18
Plot, Alexandre. "Approches numériques de conception CEM de cartes électroniques basées sur les techniques d'apprentissage". Electronic Thesis or Diss., Rennes, INSA, 2024. http://www.theses.fr/2024ISAR0001.
Testo completoAbstract (sommario):
L’évolution constante des technologies des systèmes électroniques pose un défi du point de vue des performances de compatibilité électromagnétique (CEM). La nécessité de concevoir des équipements conformes aux normes CEM dès la première itération implique de prendre en compte la CEM dès les premières étapes de la conception. Ce mémoire s’intéresse à la conception CEM de cartes électroniques sous l’angle de la métamodélisation. L’utilisation d’une telle technique, permettant de se substituer à un modèle physique coûteux à calculer, présente un défi triple impliquant le choix d’une méthode appropriée, la détermination du nombre de données d’apprentissage, et les limites rencontrées dans le contexte de l’augmentation de la dimension (nombre de variables de conception). Cette thèse a permis de proposer une méthodologie complète répondant d’une part à la problématique de l’obtention d’un métamodèle fiable, et d’autre part au défi de l’analyse CEM de cartes électroniques. Un processus d’apprentissage systématique, reposant sur l’identification des variables prépondérantes et la mise en concurrence de plusieurs métamodèles dans un processus itératif d’apprentissage, est mis en place. Le métamodèle est ensuite utilisé comme modèle paramétrique du circuit imprimé, capable de calculer des grandeurs caractéristiques de performances CEM. La réalisation d’analyses de sensibilité et de criticité des paramètres de circuits imprimés, permet d’établir des règles de routage favorisant une conception CEM plus saine de la carte. Plusieurs situations physiques de conception sont étudiées afin de valider la méthode d’apprentissage et de confirmer la pertinence des règles de conception établiesThe constant evolution of electronic systems technologies presents a challenge in terms of electromagnetic compatibility (EMC) performance. The need to design equipment compliant with EMC standards from the first iteration requires considering EMC in the early stages of design. This thesis focuses on EMC design of electronic boards from the perspective of surrogate modeling. The use of such a technique, substituting for a costly-tocalculate physical model, poses a triple challenge involving the choice of an appropriate method, determining the number of learning data, and addressing limits in the context of dimension increase (number of design variables). The thesis proposes a comprehensive methodology addressing the training of a reliable metamodel and the challenge of EMC analysis of electronic boards. A systematic learning process, based on identifying significant variables and competing multiple metamodels in an iterative learning process, is established. The metamodel is then used as a parametric model of the printed circuit board, able to compute characteristic EMC observables. Conducting sensitivity and criticality analyses of printed circuit parameters helps establishing routing rules favoring a healthier EMC design of the board. Several scenarios are studied to validate the learning method and confirm the relevance of the established design rules
19
Walker, M. "Design and implementation of high-speed digital electronics hardware for telecommunications satellite on-board processors". Thesis, University College London (University of London), 2011. http://discovery.ucl.ac.uk/1220311/.
Testo completoAbstract (sommario):
Personal mobile voice and data communications have become ubiquitous in most developed areas of the modern world, with cellular mobile phone calls and text messages being perhaps the most common examples. Satellite operators provide comparable services that are not constrained by terrestrial cellular network coverage. With sustained demand for personal mobile communications via satellite and Moore’s law continuing to provide gains in integrated circuits, communications satellite vendors have the opportunity to supply new generations of equipment to fulfil this demand. Three linked projects are presented in chronological order, covering the design and implementation of high-speed digital electronics hardware for telecommunications satellite on-board digital signal processor equipments. Novel materials and hardware architectures are used to support the latest generations of integrated circuits thus enabling significant equipment performance increases, whilst meeting the strict resource budgets and constraints placed on satellite payload equipment. A novel processor equipment hardware architecture is described, which achieves high digital electronics power densities by using large aluminium nitride substrates to provide the physical component accommodation, electrical interconnections and thermal conduction path. The substrate material properties are studied and used to develop a baseline trace geometry and stack-up, optimised for routing capacity. The proposed architectures are then evaluated for feasibility. Alternative approaches are considered and a concept study of ‘thin PCB’ hardware undertaken. The development of the phase-2 next generation processor’s digital processor module is reported, from definition and design to testing, problem characterisation and resolution. After requirements capture and PCB stack-up design, the Clos network switch fabric routing is optimised for minimum PCB layer occupancy and signal integrity. The component pin-outs are optimised and ASIC and clock device packages designed, before the PCB is designed and fabricated. The module was tested at Engineering Model (EM) and Engineering Qualification Model (EQM) quality levels. Eight flight units will see deployment in the AlphaSat satellite, currently scheduled for launch in 2013. The research for this EngD took place under different phases of the Next Generation Processor (NGP) R&D programme, co-funded by Astrium and ESA. The work was carried out by the author, whilst in full time employment at the EADS Astrium Processor Products Group, in Stevenage, England. The group designs and delivers payload equipments, which use DSP algorithms, implemented in hardware, to realise flexible telecommunications satellite payloads, including the Inmarsat 4, Skynet 5 and AlphaSat processors.
20
Eben-Chaime, Moshe. "The physical design of printed circuit boards : a mathematical programming approach". Diss., Georgia Institute of Technology, 1989. http://hdl.handle.net/1853/25505.
Testo completo
21
Lin, Leo Y. 1972. "Design, implementation, and characterization of an optical multi-carrier demultiplexerdemodulator for satellite on-board processing". Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=21311.
Testo completoAbstract (sommario):
In order to keep up with the ever-increasing demand in communications, photonic technology, that has potential benefits in low power consumption, large bandwidth, reduction in payload mass and volume, and electromagnetic interference immunity, offers an alternative approach for the future communication satellites. An optical multi-carrier demultiplexer/demodulator (MCDD) system using acousto-optic technology has been built and characterized for satellite on-board processing (OBP). In this work, the design and implementation of this demonstrator are presented. The challenges for introducing the optical technologies are also discussed for the optics, optical packaging, and opto-electronics. The system was characterized and demonstrated a channel capacity of 438 channels with a power consumption of 63.9mW per channel.
22
Miller, Richard H. "User interface design and evaluation of a shipboard electronic warfare console". Diss., Virginia Tech, 1993. http://hdl.handle.net/10919/40148.
Testo completo
23
Chun, Sungjun. "Methodologies for modeling simultaneous switching noise in multi-layered packages and boards". Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15452.
Testo completo
24
Li, Weiping. "Large-area, low-cost via formation and metallization in multilayer thin film interconnection on Printed Wiring Boards (PWB)". Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/19641.
Testo completo
25
Dick, Jochen Helmut. "Cost modelling and concurrent engineering for testable design". Thesis, Brunel University, 1993. http://bura.brunel.ac.uk/handle/2438/5284.
Testo completoAbstract (sommario):
As integrated circuits and printed circuit boards increase in complexity, testing becomes a major cost factor of the design and production of the complex devices. Testability has to be considered during the design of complex electronic systems, and automatic test systems have to be used in order to facilitate the test. This fact is now widely accepted in industry. Both design for testability and the usage of automatic test systems aim at reducing the cost of production testing or, sometimes, making it possible at all. Many design for testability methods and test systems are available which can be configured into a production test strategy, in order to achieve high quality of the final product. The designer has to select from the various options for creating a test strategy, by maximising the quality and minimising the total cost for the electronic system. This thesis presents a methodology for test strategy generation which is based on consideration of the economics during the life cycle of the electronic system. This methodology is a concurrent engineering approach which takes into account all effects of a test strategy on the electronic system during its life cycle by evaluating its related cost. This objective methodology is used in an original test strategy planning advisory system, which allows for test strategy planning for VLSI circuits as well as for digital electronic systems. The cost models which are used for evaluating the economics of test strategies are described in detail and the test strategy planning system is presented. A methodology for making decisions which are based on estimated costing data is presented. Results of using the cost models and the test strategy planning system for evaluating the economics of test strategies for selected industrial designs are presented.
26
Sulaiman, Mubarak S. A. "The evaluation of academic electronic bulletin boards for communication and training : HCI factors in the UK and Saudi Arabia". Thesis, Loughborough University, 1994. https://dspace.lboro.ac.uk/2134/22202.
Testo completoAbstract (sommario):
Electronic networks services have become essential tools for the academic community. One of the services provided has been academic electronic bulletin boards (EBBs), and the use of EBBs has increased dramatically during the last decade. One question concerns the possible application of EBBs as a means both for communication and for remote training. A series of experiments were conducted during 1991, 1992, and 1993 with the aim of examining the use of EBBs for these purposes. The first experiment was carried out to investigate whether users experience problems in using EBBs. The next extended this to see how students evaluated EBBs for communication and training purposes. The main focus of the work was BUBL. After this second experiment, modifications were made to the BUBL data and a further experiment was carried out. A different group of students looked at the modified material, and also compared it with US data using different software. The fourth experiment compared the usability of a menu-based interface (dBase III +) and a hypertext interface (HyperCard) from a student's viewpoint. It was followed by an investigation of icons to find out how well different icons could be recognised and the possibility of using them for language-independent instructions. Finally, the characteristics and problems of GULFNET users were examined. The evaluation has demonstrated the general acceptability of EBBs and their likely value for training purposes. This leads to a discussion of how an EBB might best be developed for use in communication and training on GULFNET.
27
Caillaud, Rémy. "Integration of a 3.3 kW, AC/DC bidirectional converter using printed circuit board embedding technology". Thesis, Lyon, 2019. http://www.theses.fr/2019LYSEI001/document.
Testo completoAbstract (sommario):
Les énergies fossiles (Pétrole, Charbon, …) représentent 80 % des énergies consommés. Malheureusement pour l’environnement, elles sont les plus polluantes. Le remplacement actuel des énergies fossiles permet au marché de l’électronique de puissance de grandir d’année en année. L’électronique de puissance permet d’adapter l’énergie électrique à son utilisation finale. Dans la pratique, l’adaptation de l’énergie électrique utilise des convertisseurs. En plus de respecter le volume, l’efficacité et la fiabilité imposés par le cahier des charges pour chaque application, l’électronique de puissance doit aussi permettre de réduire sensiblement les coûts. Le convertisseur doit assurer le fonctionnement électrique du circuit, le support mécanique des composants et la gestion thermique. Le package utilisé par les nouveaux composants à grand gap limite leurs performances. L’intégration des convertisseurs doit développer des méthodes d’interconnexion permettant d’éliminer ce package. L’objectif de la recherche sur l’intégration des convertisseurs est de repousser les limites imposées par un cahier des charges standard tout en assurant ces 3 fonctions principales. Parmi les nombreuses techniques d’intégration, le circuit imprimé (PCB) est mature industriellement, permet la fabrication collective et un assemblage automatisé. L’intégration utilisant le PCB a développé la technique d’enfouissement de puce avec laquelle la puce est directement enfouie dans le PCB sans son package. Cette thèse va étudier la méthode d’enfouissement pour les autres composants nécessaires à la réalisation d’un convertisseur (Condensateurs, Composants Magnétiques). Une optimisation du convertisseur qui doit être réalisé permet de prendre en compte les avantages de cette nouvelle technologie. Un prototype de convertisseur intégré a été réalisé avec des composants utilisant cette technologieWith the endangering of the environment due to the use of fossil fuels, the power electronics market is growing through the years. The number of applications is increasing in numerous field as, for example, transport (electric car, "more electric" aircraft) or energy (photovoltaic, smart grid). Beyond meeting the volume, efficiency and reliability specifications for each application, power electronics should also reduce substantially costs. Today, the managing of the electric energy uses power electronic converters. The conception of a converter is a multiphysic problem. The converter has to ensure electrical functionality, mechanical support and proper thermal management.The new wide-band gap components are limited in performance by their package. The integration of a converter should use new interconnection methods to avoid the use of packaged components. The trend is to integrate the maximum of components into a single system. This integration can offer benefits such as size and weight reduction, cost saving and reliability improvement by managing the complexity and the high density of interconnection. Among many integration technologies available, Printed Circuit Board (PCB) is well known in the industry, allowing mass production with automated manufacturing and assembly. The PCB integration was developed with the “Die Embedding” technology in which a bare die in embedded directly in the PCB to not use package. This thesis studied the embedding technology on others components necessary to the realization of a converter (Capacitors, Magnetics, …). An optimization of the converter is done taking into account the advantages of this new technology. A prototype of an AC/DC bidirectional converter fully integrated using this technology was realized
28
Ditaranto, Abramo. "Design and prototyping of electronic PCBs for the study of the atmosphere in harsh environmental conditions". Master's thesis, Alma Mater Studiorum - Università di Bologna, 2014. http://amslaurea.unibo.it/7983/.
Testo completo
29
Perrin, Rémi. "Characterization and design of high-switching speed capability of GaN power devices in a 3-phase inverter". Thesis, Lyon, 2017. http://www.theses.fr/2017LYSEI001/document.
Testo completoAbstract (sommario):
Le projet industriel français MEGaN vise le développement de module de puissance à base de compostant HEMT en GaN. Une des application industrielle concerne l’aéronautique avec une forte contrainte en isolation galvanique (>100 kV/s) et en température ambiante (200°C). Le travail de thèse a été concentré sur une brique module de puissance (bras d’onduleur 650 V 30 A). L’objectif est d’atteindre un prototype de facteur de forme peu épais, 30 cm2 et embarquant l’ensemble des fonctions driver, alimentation de driver, la capacité de bus et capteur de courant phase. Cet objectif implique un fort rendement énergétique, et le respect de l’isolation galvanique alors que la contrainte en surface est forte. Le manuscrit, outre l’état de l’art relatif au module de puissance et notamment celui à base de transistor GaN HEMT, aborde une solution d’isolation de signaux de commande à base de micro-transformateur. Des prototypes de micro-transformateur ont été caractérisés et vieillis pendant 3000 H pour évaluer la robustesse de la solution. Les travaux ont contribué à la caractérisation de plusieurs composants GaN afin de mûrir des modèles pour la simulation circuit de topologie de convertisseur. Au sein du travail collaboratif MEGaN, notre contribution ne concernait pas la conception du circuit intégré (driver de grille), tout en ayant participé à la validation des spécifications, mais une stratégie d’alimentation du driver de grille. Une première proposition d’alimentation isolée pour le driver de grille a privilégié l’utilisation de composants GaN basse-tension. La topologie Flyback résonante avec clamp permet de tirer le meilleur parti de ces composants GaN mais pose la contrainte du transformateur de puissance. Plusieurs technologies pour la réalisation du transformateur ont été validées expérimentalement et notamment une proposition originale enfouissement du composant magnétique au sein d’un substrat polymère haute-température. En particulier, un procédé de fabrication peu onéreux permet d’obtenir un dispositif fiable (1000 H de cyclage entre - 55 ; + 200°C), avec un rendement intrinsèque de 88 % pour 2 W transférés. La capacité parasite d’isolation est réduite par rapport aux prototypes précédent. Deux prototypes d’alimentations à forte intégration utilisent soit les transistors GaN basse tension (2.4 MHz, 2 W, 74 %, 6 cm2), soit un circuit intégré dédié en technologie CMOS SOI, conçu pour l’application (1.2 MHz, 2 W, 77 %, 8.5 cm2). Le manuscrit propose par la suite une solution intégrable de mesure de courant de phase du bras de pont, basé sur une magnétorésistance. La comparaison expérimentale vis à vis d’une solution à résistance de shunt. Enfin, deux prototypes de convertisseur sont décrits, dont une a pu faire l’objet d’une validation expérimentale démontrant des pertes en commutation réduitesThe french industrial project MEGaN targets the development of power module based on GaN HEMT transistors. One of the industrial applications is the aeronautics field with a high-constraint on the galvanic isolation (>100 kV/s) and ambient temperature (200°C). The intent of this work is the power module block (3 phases inverter 650 V 30 A). The goal is to obtain a small footprint module, 30 cm2, with necessary functions such as gate driver, gate driver power supply, bulk capacitor and current phase sensor. This goal implies high efficiency as well as respect of the constraint of galvanic isolation with an optimized volume. This dissertation, besides the state of the art of power modules and especially the GaN HEMT ones, addressed a control signal isolation solution based on coreless transformers. Different prototypes based on coreless transformers were characterized and verified over 3000 hours in order to evaluate their robustness. The different studies realized the characterization of the different market available GaN HEMTs in order to mature a circuit simulation model for various converter topologies. In the collaborative work of the project, our contribution did not focus on the gate driver chip design even if experimental evaluation work was made, but a gate driver power supply strategy. The first gate driver isolated power supply design proposition focused on the low-voltage GaN HEMT conversion. The active-clamp Flyback topology allows to have the best trade-off between the GaN transistors and the isolation constraint of the transformer. Different transformer topolgies were experimentally performed and a novel PCB embedded transformer process was proposed with high-temperature capability. A lamination process was proposed for its cost-efficiency and for the reliability of the prototype (1000 H cycling test between - 55; + 200°C), with 88 % intrinsic efficiency. However, the transformer isolation capacitance was drastically reduced compared to the previous prototypes. 2 high-integrated gate driver power supply prototypes were designed with: GaN transistors (2.4 MHz, 2 W, 74 %, 6 cm2), and with a CMOS SOI dedicated chip (1.2 MHz, 2 W, 77 %, 8.5 cm2). In the last chapter, this dissertation presents an easily integrated solution for a phase current sensor based on the magnetoresistance component. The comparison between shunt resistor and magnetoresistance is experimentally performed. Finally, two inverter prototypes are presented, with one multi-level gate driver dedicated for GaN HEMT showing small switching loss performance
30
Caswell, Thomas Hubbard. "Designing an online support community for novice computer users". CSUSB ScholarWorks, 2004. https://scholarworks.lib.csusb.edu/etd-project/2504.
Testo completoAbstract (sommario):
This project seeks to identify characteristics of successful online communities and apply them to designing and prototyping an online discussion forum where novice computer users can share computer questions and answers. Usability and sociability are identified as essential goals in the development of online communities. Appropriate and effective Computer Mediated Communication (CMC) software is evaluated and selected to run the discussion forum.
31
Sicre, Mathieu. "Study of the noise aging mechanisms in single-photon avalanche photodiode for time-of-flight imaging". Electronic Thesis or Diss., Lyon, INSA, 2023. http://www.theses.fr/2023ISAL0104.
Testo completoAbstract (sommario):
Les diodes à avalanche à photon unique (SPAD) sont utilisées pour les capteurs à temps de vol afin de déterminer la distance d'une cible. Cependant, ils sont sujets à des déclenchements parasites par des porteurs de charge générés de manière parasitaire, quantifiés en tant que taux de comptage dans l’obscurité (DCR), ce qui peut compromettre la précision de la distance mesurée. Pour résoudre ce problème, une méthodologie de simulation a été mise en place pour évaluer le DCR. Cela est réalisé en simulant la probabilité de claquage d'avalanche, intégrée avec le taux de génération de porteurs de charge à partir de défauts. Cette méthodologie permet d'identifier les sources potentielles de DCR avant stress. Pour garantir l'intégrité des mesures de distance sur une longue période, il est nécessaire de prédire le niveau de DCR dans diverses conditions d'exploitation. La méthodologie de simulation susmentionnée est utilisée pour identifier les sources potentielles de DCR après stress. Pour un modèle cinétique précis de dégradation de type porteurs chauds (HCD), il est essentiel de considérer non seulement la distribution d'énergie des porteurs, mais également la distribution de l'énergie de dissociation de la liaison Si-H à l'interface Si/SiO2. La probabilité de dissociation d'ionisation d'impact est utilisée pour modéliser le processus de création de défauts, qui présente une dépendance temporelle sous-linéaire en raison de l'épuisement progressif des précurseurs de défauts. Une mesure précise de la distance nécessite de distinguer le signal du bruit ambiant et du plancher de DCR. L'impact de DCR peut être estimé en considérant la réflectance de la cible et les conditions d'éclairage ambiant. En résumé, ce travail utilise une méthodologie de caractérisation et de simulation approfondie pour prédire le DCR dans les dispositifs de type SPAD le long de sa durée de vie, permettant ainsi d'évaluer son impact sur les mesures de distanceSingle-Photon Avalanche Diode (SPAD) are used for Time-of-Flight (ToF) sensors to determine distance from a target by measuring the travel time of an emitted pulsed signal. These photodetectors work by triggering an avalanche of charge carriers upon photon absorption, resulting in a substantial amplification which can be detected. However, they are subject to spurious triggering by parasitic generated charge carriers, quantified as Dark Count Rate (DCR), which can compromise the accuracy of the measured distance. Therefore, it is crucial to identify and eliminate the potential source of DCR. To tackle this issue, a simulation methodology has been implemented to assess the DCR. This is achieved by simulating the avalanche breakdown probability, integrated with the carrier generation rate from defects. The breakdown probability can be simulated either in a deterministically, based on electric-field streamlines, or stochastically, by means of drift-diffusion simulation of the random carrier path. This methodology allows for the identification of the potential sources of pre-stress DCR by comparing simulation results to experimental data over a wide range of voltage and temperature. To ensure the accuracy of distance range measurements over time, it is necessary to predict the DCR level under various operating conditions. The aforementioned simulation methodology is used to identify the potential sources of post-stress DCR by comparing simulation results to stress experiments that evaluate the principal stress factors, namely temperature, voltage and irradiance. Furthermore, a Monte-Carlo study has been conducted to examine the device-to-device variation along stress duration. For an accurate Hot-Carrier Degradation (HCD) kinetics model, it is essential to consider not only the carrier energy distribution function but also the distribution of Si−H bond dissociation energy distribution at the Si/SiO2 interface. The number of available hot carriers is estimated from the carrier current density according to the carrier energy distribution simulated by means of a full-band Monte-Carlo method. The impact-ionization dissociation probability is employed to model the defect creation process, which exhibits sub-linear time dependence due to the gradual exhaustion of defect precursors. Accurate distance ranging requires distinguishing the signal from ambient noise and the DCR floor, and ensuring the target’s accumulated photon signal dominates over other random noise sources. An analytical formula allows to estimate the maximum distance ranging using the maximum signal strength, ambient noise level, and confidence levels. The impact of DCR can be estimated by considering the target’s reflectance and the ambient light conditions. In a nutshell, this work makes use of a in-depth characterization and simulation methodology to predict DCR in SPAD devices along stress duration, thereby allowing the assessment of its impact on distance range measurements
32
Song, Hamila. "Development of a web site for Korean returning students and their parents to help their process of re-adaptation". CSUSB ScholarWorks, 2005. https://scholarworks.lib.csusb.edu/etd-project/2874.
Testo completoAbstract (sommario):
The purpose of this project was to develop a website to relieve Korean returnees' reverse culture shock and help their re-adaptation process. A website can be an outstanding resource for returnees in terms of accessibility because the target audiences are scattered all over the world.
33
Chanda, Asit Baran. "Hardware design of electronic notice board". Thesis, 2014. http://ethesis.nitrkl.ac.in/6475/1/E-38.pdf.
Testo completoAbstract (sommario):
In this project a hardware is designed to measure the temperature and humidity and log the data in a SD card. At the core`e of the circuit is the ARDUINO UNO microcontroller which controls all its functions. A humidity and temperature sensor DHT11 is used for sensing the humidity and temperature of the environment and the system displays the humidity and temperature on an LCD in the range of 20%RH to 90%RH and 0°C to +50°C respectively. This humidity and temperature values are then programmed to log and saved in an external SD card as text file . The logged data can be seen by opening the text file in a computer.
34
Wei, Chen Hong, e 陳弘偉. "Vehicle Uses Electronic Display Board Design and Appraisal". Thesis, 2013. http://ndltd.ncl.edu.tw/handle/47805249369635549561.
Testo completoAbstract (sommario):
碩士大葉大學
設計暨藝術學院碩士班
101
An important medium of communication between drivers and vehicles is the vehicle dashboard presenting information about the current road situation and the car operation. Since electronic technology has obviously made relative progress in the auto industry, a variety of instruments ranging from digital, electronic, dashboards to the scope of information, integration systems, many shortcut keys helping drivers to quickly perform an action are developed. This research aimed mainly at improving driver, digital instruments, and integration of shortcut key operation to new design proposals and evaluation. This study selected six domestic cars, whose car dashboards are divided into three regional discussions, ---, digital dashboard, steering wheel, and center console area. It involed interviewing Two expert interviews. The interview intended to find at the factors impacting drivers’ behavior are operating dashboard, the details drivers care, and the unconscious behavior while they drive. By means of a questionnaire classified into several operating systems: instrument navigation and steering wheel, air conditioning, audio, shortcut keys, survey action items using frequency, we consequently will receive a level of operation of the system features data. Then we randomly choose six cars. Accordingly, we redesigned a new style instrument panel and consoles. New instrument panel and consoles in order to relieve/reduce the drivers dissatisfaction towards the inconvenience and the coplerity while driving, and operation using frequency, we redesigned tables/panel based on user-oriented design function, key configuration which met with drivers’ need to meet with operating requirement.
35
Lin, Tzu-Liang, e 林子良. "The Design and Implementation of an Electronic Dart Board". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/92563734067389742997.
Testo completoAbstract (sommario):
碩士逢甲大學
資訊電機工程碩士在職專班
100
The aim of this thesis is to design an electronic dart board which has features of plastic dart target and plastic dart head instead of traditional dart board. The design and implementation of an electronic dart board is fulfilled in this thesis. The hardware design is basically based on a microcontroller and some peripheral circuits such as LED drives, keypad decoders and transmit/receive drive. The software is programmed in assembly language. The detailed flowchart diagram and description related to the voice processing, image processing and keypad processing are presented and discussed in this thesis. Finally, the experimental results are demonstrated and show the verification and feasibility of the whole system design.
36
"An agent-assisted board-level functional fault diagnostic framework: design and optimization". 2014. http://repository.lib.cuhk.edu.hk/en/item/cuhk-1291511.
Testo completoAbstract (sommario):
Advances in semiconductor technology and design automation methods have introduced a new era for electronic products. With design sizes in millions of logic gates and operating frequencies in GHz, defects-per-million rates continue to increase, and defects are manifesting themselves in subtle ways.Diagnosing functional failures in complicated electronic boards is a challenging task, wherein debug technicians try to identify defective components by analyzing some syndromes obtained from the application of diagnostic tests. The diagnosis effectiveness and efficiency rely heavily on the quality of the in-house developed diagnostic tests and the debug technicians’ knowledge and experience, which, however, have no guarantees nowadays. To tackle this problem, this thesis proposes a novel agent-assisted diagnostic framework for board-level functional failures, namely AgentDiag, which facilitates to evaluate the quality of the diagnostic tests and bridge the knowledge gap between the diagnostic programmers who write diagnostic tests and the debug technicians who conduct in-field diagnosis with a lightweight model of the boards and tests.
Machine learning algorithms have been advocated for automated diagnosis of board-level functional failures due to the extreme complexity of the problem. Such reasoning-based solutions, however, remain ineffective at the early stage of the product cycle, simply because there are insufficient historical data for training the diagnostic system that has a large number of test syndromes. Guided by a proposed metric isolation capability, AgentDiag is able to leverage the knowledge from the lightweight model to selecting a reduced test syndrome set for diagnosis in an adaptive manner.
While AgentDiag is effective to improve the diagnostic accuracy, this technique, by excluding some test syndromes, may cause information loss for diagnosis. The thesis further presents a novel test syndrome merging methodology to address this problem. That is, by leveraging the domain knowledge of the diagnostic tests and the board structural information, we adaptively reduce the feature size of the diagnostic system by selectively merging test syndromes such that it can effectively utilize the available training cases.
Experimental results on real industrial boards and an OpenRISC design demonstrate the effectiveness of the proposed solutions.
半導體技術和設計自動化的高速發展開啟了電子產品的新紀元。百萬級別的設計尺寸和上G赫茲的操作頻率使得每百萬次採樣數的缺陷率繼續上升，缺陷顯現方式也日益微妙。
複雜電子板的診斷是一項極具挑戰的工作。調試人員通常通過分析診斷測試所產生的症狀，甄別有缺陷的元件。診斷的有效性和效率就極大地依賴於診斷測試的質量和調試人員的知識經驗，但是現在這些都是沒有確定性的。為了解決這一問題，本文提出一個新穎的針對板級功能性故障的代理輔助診斷系統AgentDiag。它幫助評估診斷測試的質量，並架起編寫診斷測試的測試程式員和從事實際診斷工作的調試人員之間的橋樑。
因為板級診斷的極度複雜，機器學習算法已經被提出來解決這一問題。但是這些基於推導的方法在早期很難達到好的效果，原因是過大的測試數量和相對較少的訓練數據。在度量Isolation Capability的引導下，能夠適應性地利用來自輕量級模型的知識去選取一個症狀集進行診斷。
AgentDiag可以有效地提高診斷準確率，但是由於是直接剔除一部分測試症狀，所以有可能造成信息的丟失。本文進一步提出了一個測試症狀合併的方法來解決這一問題。那就是利用診斷測試和電路板的結構描述，我們可以適應性地利用選擇性合併的測試症狀來減少測試症狀的數目，從而有效地利用已有的測試數據。
來自實際的工業電路板和OpenRisc設計的實驗數據驗證了提出的方法的有效性。
Sun, Zelong.
Thesis M.Phil. Chinese University of Hong Kong 2014.
Includes bibliographical references (leaves 47-51).
Abstracts also in Chinese.
Title from PDF title page (viewed on 12, October, 2016).
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
37
Park, In Seop. "Communications protocols for microcomputer-based workstations: a design and implementation of an Electronic Bulletin Board System (NPS-BBS)". Thesis, 1985. http://hdl.handle.net/10945/21197.
Testo completo
38
"Hardware emulation board based on field programmable gate arrays (FPGAs) and programmable interconnections". Chinese University of Hong Kong, 1994. http://library.cuhk.edu.hk/record=b5888211.
Testo completoAbstract (sommario):
by Lo Wing-yee.Thesis (M.Phil.)--Chinese University of Hong Kong, 1994.
Includes bibliographical references (leaves vii-ix).
ABSTRACT --- p.i
LIST OF TABLES --- p.iv
LIST OF FIGURES --- p.v
Chapter 1. --- INTRODUCTION --- p.1
Chapter 1.1 --- Traditional Design Prototyping --- p.1
Chapter 1.2 --- In-Circuit Rapid Prototyping System --- p.2
Chapter 1.3 --- A Summary of Prototyping Systems Available --- p.5
Chapter 1.4 --- Universal Prototyping Board (UPB) --- p.6
Chapter 2. --- HARDWARE DESIGNS --- p.9
Chapter 2.1 --- Bus Interconnection --- p.9
Chapter 2.1.1 --- Fixed buses --- p.9
Chapter 2.1.2 --- Programmable buses --- p.12
Chapter 2.2 --- Architectural Features --- p.15
Chapter 2.2.1 --- Field programmable gate array --- p.15
Chapter 2.2.2 --- Microprocessor --- p.15
Chapter 2.2.3 --- Memory --- p.16
Chapter 2.2.4 --- Buffers --- p.18
Chapter 3. --- SOFTWARE TOOLS --- p.20
Chapter 3.1 --- Critical Path Analysis --- p.20
Chapter 3.1.1 --- Algorithm of critical path analysis --- p.21
Chapter 3.1.2 --- Computation time --- p.21
Chapter 3.2 --- Circuit Partitioning --- p.23
Chapter 3.2.1 --- Partitioning algorithm --- p.24
Chapter 3.2.2 --- Effects of partitioning --- p.36
Chapter 3.2.3 --- Partitioning parameters --- p.38
Chapter 3.2.4 --- Pseudo-code of partitioner --- p.39
Chapter 3.3 --- IO Assignments --- p.40
Chapter 3.3.1 --- Connect 4 FPGAs --- p.40
Chapter 3.3.2 --- Connect 3 FPGAs --- p.42
Chapter 3.3.3 --- Connect 2 FPGAs --- p.44
Chapter 3.3.4 --- System IO (Connect 1 FPGA) --- p.47
Chapter 3.4 --- Other Tools --- p.48
Chapter 4. --- STRUCTURE ANALYSIS --- p.49
Chapter 5. --- RESULTS --- p.52
Chapter 6. --- FUTURE DIRECTION --- p.73
Chapter 6.1 --- Other Possible Configurations --- p.73
Chapter 6.2 --- Programmable Interconnection --- p.73
Chapter 6.3 --- Expandability of UPB --- p.74
Chapter 7. --- CONCLUSION --- p.75
BIBLIOGRAPHY --- p.vii
APPENDICES --- p.x
39
Wu, Chang-Ping, e 武昌平. "CPLD/FPGA Design for Testing Board of Digital Electronics Technician Authentication". Thesis, 2014. http://ndltd.ncl.edu.tw/handle/26t8fn.
Testo completoAbstract (sommario):
碩士國立高雄應用科技大學
電子工程系碩士班
102
Nowadays, in order to investigate the effectiveness of the circuit design, EDA enables fast verification and design for electronic circuits. The technician certification receives much attention in recent years. Thus, the certification of the Level B Technician for Digital Electronics is an important certification of electronic engineer. To acquire this certification, the skill of practical electronics design must be inspected by examination. including the design ability of practical functional circuits. After finishing the designs based on the assigned 3 examination questions, the designs are verified by 3 instruments. The verified instruments with large volume are expensive. If the examinee wants to exercise before test, they need to find the place with the 3 specific instruments to verify their designs. So it is not convenient to the examinee. This research aims at the tester designs for the verification of the 3 skill examination questions of the Level B Technician for Digital Electronics. Three testers are finished for the verification of examinee’s designed circuits, i.e, 4-digit display, keyboard scanner and digital electronic clock. The designed testers have the advantages of low cost, small volume and complete function verification. We use complex programmable logic device (CPLD) to develop our testers, so the realization period becomes shorter. The used CPLD from Altera Corporation belongs to the low-cost EPM series chips. It can be used to design complex circuits instead of using traditional TTL/CMOS gates. The Quartus II software is used to describe the intended function, and then it has been downloaded to burn into the CPLD IC via PC Print Port. Then the CPLD can operate independently. After the measurement, it is found that the designed testers have identical functions as the mentioned 3 specific instruments. Thus the designs are verified.
40
Mohanty, Nihar Ranjan. "Design and Analysis of an On-Board Electric Vehicle Charger for Wide Battery Voltage Range". Thesis, 2016. http://ethesis.nitrkl.ac.in/8501/1/2016_MT__214EE5261_NRMohanty.pdf.
Testo completoAbstract (sommario):
The scarcity of fossil fuel and the increased pollution leads the use of Electric Vehicles (EV) and Hybrid Electric Vehicles (HEV) instead of conventional Internal Combustion (IC) engine vehicles. An Electric Vehicle requires an on-board charger (OBC) to charge the propulsion battery. The objective of the project work is to design a multifunctional on-board charger that can charge the propulsion battery when the Electric Vehicle (EV) connected to the grid. In this case, the OBC plays an AC-DC converter. The surplus energy of the propulsion battery can be supplied to the grid, in this case, the OBC plays as an inverter. The auxiliary battery can be charged via the propulsion battery when PEV is in driving stage. In this case, the OBC plays like a low voltage DC-DC converter (LDC). An OBC is designed with Boost PFC converter at the first stage to obtain unity power factor with low Total Harmonic Distortion (THD) and a Bi-directional DC-DC converter to regulate the charging voltage and current of the propulsion battery. The battery is a Li-Ion battery with a nominal voltage of 360 V and can be charged from depleted voltage of 320 V to a fully charged condition of 420 V. The function of the second stage DC-DC converter is to charge the battery in a Constant Current and Constant Voltage manner. While in driving condition of the battery the OBC operates as an LDC to charge the Auxiliary battery of the vehicle whose voltage is around 12 V. In LDC operation the Bi-Directional DC-DC converter works in Vehicle to Grid (V2G) mode. A 1KW prototype of multifunctional OBC is designed and simulated in MATLAB/Simulink. The power factor obtained at full load is 0.999 with a THD of 3.65 %. The Battery is charged in A CC mode from 320 V to 420 V with a constant battery current of 2.38 A and the charging is switched into CV mode until the battery current falls below 0.24 A. An LDC is designed to charge a 12 V auxiliary battery with CV mode from the high voltage propulsion battery
41
"Accelerated Life testing of Electronic Circuit Boards with Applications in Lead-Free Design". Doctoral diss., 2012. http://hdl.handle.net/2286/R.I.14570.
Testo completoAbstract (sommario):
abstract: This dissertation presents methods for addressing research problems that currently can only adequately be solved using Quality Reliability Engineering (QRE) approaches especially accelerated life testing (ALT) of electronic printed wiring boards with applications to avionics circuit boards. The methods presented in this research are generally applicable to circuit boards, but the data generated and their analysis is for high performance avionics. Avionics equipment typically requires 20 years expected life by aircraft equipment manufacturers and therefore ALT is the only practical way of performing life test estimates. Both thermal and vibration ALT induced failure are performed and analyzed to resolve industry questions relating to the introduction of lead-free solder product and processes into high reliability avionics. In chapter 2, thermal ALT using an industry standard failure machine implementing Interconnect Stress Test (IST) that simulates circuit board life data is compared to real production failure data by likelihood ratio tests to arrive at a mechanical theory. This mechanical theory results in a statistically equivalent energy bound such that failure distributions below a specific energy level are considered to be from the same distribution thus allowing testers to quantify parameter setting in IST prior to life testing. In chapter 3, vibration ALT comparing tin-lead and lead-free circuit board solder designs involves the use of the likelihood ratio (LR) test to assess both complete failure data and S-N curves to present methods for analyzing data. Failure data is analyzed using Regression and two-way analysis of variance (ANOVA) and reconciled with the LR test results that indicating that a costly aging pre-process may be eliminated in certain cases. In chapter 4, vibration ALT for side-by-side tin-lead and lead-free solder black box designs are life tested. Commercial models from strain data do not exist at the low levels associated with life testing and need to be developed because testing performed and presented here indicate that both tin-lead and lead-free solders are similar. In addition, earlier failures due to vibration like connector failure modes will occur before solder interconnect failures.Dissertation/Thesis
Ph.D. Industrial Engineering 2012
42
Hongwei, Wu, e 吳泓緯. "Optimum Design Studies of Electronic Circuit Parameters for Blood Glucose Measurement with Test Strips Made of Gold Plated Printed Circuit Boards". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/pcmwf7.
Testo completoAbstract (sommario):
碩士國立臺北科技大學
機電整合研究所
105
The demand for blood glucose test strips is increasing with the number of diabetics, and aside from karbogel strips, gold strips also are prevalent on the market. This study discusses optimizing the design parameter for a gold blood glucose test strip, in which the accuracy of blood glucose reading is related to the applied voltage and applied current for the electrochemical reaction in the reaction zone of the gold blood glucose test strip. The research consists of two parts. The first part is the applied voltage. The cyclic voltammetry graph shows that the optimum applied voltage is 0.08V-0.1V. In the past, the parameters of the blood glucose meter were made in reference to the carbon test strip, whereas the measurement of blood glucose from the gold test strips are still based on the electrochemical analytical method based on carbon test strip. Therefore, the measurement of blood glucose from the gold test strips should be based on the electrochemical characteristics of the gold test strips, not carbon test strips. Part 2 is the applied current. The resistance of the all connecting conductor tracks are associated with the current generated, when the applied voltage is fixed. Different applied voltage and electrical resistance can influence the blood glucose reading. In this experiment, three applied voltages were used as the variable parameters for this study, including 0.3V, 0.15V, and 0.1V. In addition, the electrical resistance of three R4 resistors are 1.0kΩ, 1.2kΩ, and 1.5kΩ, respectively. According to the observation on different parameter settings, when the voltage is set to be 0.1V and the R4 resistor is set to be 1.2kΩ, the blood glucose reading is comparatively more stable and accurate, meaning that the parameters of determining gold test strip’s performance are different from that of the carbon test strip.
43
Pannell, Zachary William. "Design of a Highly Constrained Test System for a 12-bit, 16-channel Wilkinson ADC". 2009. http://trace.tennessee.edu/utk_gradthes/549.
Testo completoAbstract (sommario):
Outer space is a very harsh environment that can cause electronics to not operate as they were originally intended. Aside from the extreme amount of radiation found in space, temperatures can also change very dramatically in a relatively small time frame. In order to test electronics that will be used in this environment, they first need to be tested on Earth under replicated conditions. Vanderbilt University designed a dewar that allows devices to be tested at these extreme temperatures while being radiated. For this thesis, a test setup that met all of the dewar's constraints was designed that would allow a 12-bit, 16-channel analog-to-digital converter to be tested while inside.
44
Santos, Ângelo Emanuel Neves dos. "Design and simulation of a smart bottle with fill-level sensing based on oxide TFT technology". Master's thesis, 2016. http://hdl.handle.net/10362/19593.
Testo completoAbstract (sommario):
Packaging is an important element responsible for brand growth and one of the main rea-sons for producers to gain competitive advantages through technological innovation. In this re-gard, the aim of this work is to design a fully autonomous electronic system for a smart bottle packaging, being integrated in a European project named ROLL-OUT. The desired application for the smart bottle is to act as a fill-level sensor system in order to determine the liquid content level that exists inside an opaque bottle, so the consumer can exactly know the remaining quantity of the product inside.
An in-house amorphous indium–gallium–zinc oxide thin-film transistor (a-IGZO TFT) model, previously developed, was used for circuit designing purposes. This model was based in an artificial neural network (ANN) equivalent circuit approach.
Taking into account that only n-type oxide TFTs were used, plenty of electronic building-blocks have been designed: clock generator, non-overlapping phase generator, a capacitance-to-voltage converter and a comparator. As it was demonstrated by electrical simulations, it has been achieved good functionality for each block, having a final system with a power dissipation of 2.3 mW (VDD=10 V) not considering the clock generator. Four printed circuit boards (PCBs) have been also designed in order to help in the testing phase.
Mask layouts were already designed and are currently in fabrication, foreseeing a suc-cessful circuit fabrication, and a major step towards the design and integration of complex trans-ducer systems using oxide TFTs technology.