Letteratura scientifica selezionata sul tema "Dispositifs CMOS et integration"
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Articoli di riviste sul tema "Dispositifs CMOS et integration"
Yadav, Sachin, Pieter Cardinael, Ming Zhao, Komal Vondkar, Uthayasankaran Peralagu, Alireza Alian, Raul Rodriguez et al. "(Digital Presentation) Substrate Effects in GaN-on-Si Hemt Technology for RF FEM Applications". ECS Meeting Abstracts MA2022-02, n. 32 (9 ottobre 2022): 1208. http://dx.doi.org/10.1149/ma2022-02321208mtgabs.
Testo completoMori, Takahiro. "(Invited, Digital Presentation) Silicon Compatible Quantum Computers: Challenges in Devices, Integration, and Circuits". ECS Meeting Abstracts MA2022-01, n. 29 (7 luglio 2022): 1297. http://dx.doi.org/10.1149/ma2022-01291297mtgabs.
Testo completoChaudhary, Mayur, e Yu-Lun Chueh. "Dual Threshold and Memory Switching Induced By Conducting Filament Morphology in Ag/WSe2 Based ECM Cell". ECS Meeting Abstracts MA2022-02, n. 36 (9 ottobre 2022): 1334. http://dx.doi.org/10.1149/ma2022-02361334mtgabs.
Testo completoDaszko, Sebastian, Carsten Richter, Jens Martin, Katrin Berger, Uta Juda, Christiane Frank-Rotsch, Patrick Steglich e Karoline Stolze. "Transfer Printable Single-Crystalline Coupons for III-V on Si Integration". ECS Meeting Abstracts MA2022-02, n. 17 (9 ottobre 2022): 863. http://dx.doi.org/10.1149/ma2022-0217863mtgabs.
Testo completoNguyen, Ngoc-Anh, Olivier Schneegans, Jouhaiz Rouchou, Raphael Salot, Yann Lamy, Jean-Marc Boissel, Marjolaine Allain, Sylvain Poulet e Sami Oukassi. "(G02 Best Presentation Award Winner) Elaboration and Characterization of CMOS Compatible, Pico-Joule Energy Consumption, Electrochemical Synaptic Transistors for Neuromorphic Computing". ECS Meeting Abstracts MA2022-01, n. 29 (7 luglio 2022): 1293. http://dx.doi.org/10.1149/ma2022-01291293mtgabs.
Testo completoPekarik, Jack, Vibhor Jain, Crystal Kenney, Judson Holt, Shweta Khokale, Sudesh Saroop, Jeffrey Johnson et al. "Challenges for Sige Bicmos in Advanced-Node SOI". ECS Meeting Abstracts MA2022-02, n. 32 (9 ottobre 2022): 1196. http://dx.doi.org/10.1149/ma2022-02321196mtgabs.
Testo completoKanyandekwe, Joël, Matthias Bauer, Tanguy Marion, Lazhar Saidi, Jean-Baptiste Pin, Jeremie Bisserier, Jérôme Richy et al. "Very Low Temperature Tensile and Selective Si:P Epitaxy for Advanced CMOS Devices". ECS Meeting Abstracts MA2022-02, n. 32 (9 ottobre 2022): 1190. http://dx.doi.org/10.1149/ma2022-02321190mtgabs.
Testo completoLamy, Yann, Florian Dupont, Guillaume Rodriguez, Messaoud Bedjaoui, Pierre Perreau, Marie Bousquet, Alexandre Reinhardt e Sami Oukassi. "(Invited) Lithium-Based Components Integrated on Silicon: Disruptive, Promising and Credible Solutions for 5G & Beyond". ECS Meeting Abstracts MA2022-01, n. 29 (7 luglio 2022): 1286. http://dx.doi.org/10.1149/ma2022-01291286mtgabs.
Testo completoXu, Xiaopeng, Xi-Wei Lin, Youxin Gao e Soren Smidstrup. "(Invited) 3DIC Hierarchical Thermal and Mechanical Analysis with Continuum and Atomistic Modeling". ECS Meeting Abstracts MA2022-02, n. 17 (9 ottobre 2022): 845. http://dx.doi.org/10.1149/ma2022-0217845mtgabs.
Testo completoQuay, Ruediger, Arnulf Leuther, Sebastien Chartier, Laurenz John e Axel Tessmann. "(Invited) III-V Integration on Silicon for Resource-Efficient Sensor-Technology". ECS Meeting Abstracts MA2023-01, n. 33 (28 agosto 2023): 1853. http://dx.doi.org/10.1149/ma2023-01331853mtgabs.
Testo completoTesi sul tema "Dispositifs CMOS et integration"
Dubreuil, Théophile. "Architecture 3D 1T1R innovante à base de RRAMs pour le calcul hyperdimensionnel". Electronic Thesis or Diss., Université Grenoble Alpes, 2023. http://www.theses.fr/2023GRALT085.
Testo completoIn the years to come, due to the insatiable need for data-intensive machine learning applications, a drastic expansion of computing power is required to confront a veritable “data deluge”. To meet this challenge, high-performance In-Memory-Computing (IMC) architectures require the development of novel storage devices that are also suited for local computations. In this context, this thesis work presents a novel 3D 1T1R memory array derived from vertically stacked-nanosheet technology, which is used for Hyperdimensional Computing (HDC), an error-resilient and highly parallel brain-inspired computing paradigm. Firstly, the IMC paradigm can greatly benefit from novel 3D non-volatile memory (NVM) architectures which increase the density and the computing performances. However, the fabrication challenges and parasitics can greatly limit the potential benefits of these architectures. With the 3D 1T1R technology, made by coupling new disruptive gate-independent stacked-nanosheets with drain-based RRAM cells, we show that some of these issues can be overcome, thus leading to high-density 3D NVM arrays. We demonstrate various technological modules necessary for the fabrication of 3D 1T1R structures. Devices are fabricated and electrically characterized for both storage and computing applications. In particular, functional MEOL drain-based RRAM cells are demonstrated with a doped-Si bottom electrode for various types of selector technologies. Finally, we propose a full-IMC architecture of HDC to take advantage of the 3D 1T1R structure. Different hardware implementations are proposed and compared with SPICE simulations. We also show with software-based simulations that language and gesture recognition can be realistically performed with our 3D 1T1R implementation
Charbonneau, Micaël. "Etude et développement de points mémoires résistifs polymères pour les architectures Cross-Bar". Thesis, Grenoble, 2012. http://www.theses.fr/2012GRENT116/document.
Testo completoOver the past decade, non-volatile Flash storage technologies have played a major role in the development of mobile electronics and multimedia (MP3, Smartphone, USB, ultraportable computers ...). To further enhance performances, increase the capacity and reduce manufacturing costs, new technological solutions are now studied to provide complementary solutions or replace Flash technology. Cited by ITRS, the polymer resistive memories present very promising characteristics: low cost processing and ability for integration at high densities above CMOS interconnections or on flexible substrate. This PhD specifically focused on the development and study of composite material made of Poly-Methyl-Methacrylate (PMMA) polymer resist doped with C60 fullerene molecules. Studies were carried out on three different axes in parallel: Composite materials development & characterization, integration of the organic material in specific test structure and advanced devices and finally detailed electrical characterization of memory cells and performances analysis
Cassé, Mikaël. "Caractérisation Électrique et Modélisation du Transport dans les Dispositifs CMOS Avancés". Habilitation à diriger des recherches, Université de Grenoble, 2014. http://tel.archives-ouvertes.fr/tel-00974652.
Testo completoLee, Sang Bruno. "Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS". Thèse, Université de Sherbrooke, 2016. http://hdl.handle.net/11143/8955.
Testo completoAbstract : The single electron transistor (SET) is a nanoelectronic device very attractive due to its ultra-low power consumption and its high integration density, but he is not capable of completely replace CMOS technology. Nevertheless, the hybridization of these two technologies is an interesting approach since it combines the advantages of both technologies, in order to obtain circuits with new and unique functionalities. This thesis deals with the 3D monolithic integration of nanodevices in the back-end-ofline (BEOL) of a CMOS chip. This approach gives the opportunity to build hybrid circuits and to add value to CMOS chips without fundamentally changing the process fabrication of MOS transistors. This study is based on the nanodamascene process developed at UdeS, which is used to fabricate nanoelectronic devices on a SiO2 layer. This document presents the work done on the nanodamascene process optimization, in order to make it compatible with the BEOL of CMOS circuits. The development of plasma etching processes has been required to fabricate metallic and dielectric nanostructures useful to the fabrication of nanodevices. MIM junctions and metallic SET have been fabricated with the new reverse nanodamascene process on a SiO2 substrate. Electrical characterizations of MIM devices and SET formed with TiN/Al2O3 junctions have shown trap sites in the dielectric and a functional SET at low temperature (1.5 K). The transfer process on CMOS substrate and the vertical interconnection process have also been developed. Finally, a 3D circuit consisting of a titanium nanowire connected to a MOS transistor is fabricated and is functional. The results obtained during this thesis prove that the co-integration of nanoelectronic devices in the BEOL of a CMOS chip is possible, using a compatible process.
Lim, Tek Fouy. "Dispositifs de protection contre les décharges électrostatiques pour les applications radio fréquences et millimétriques". Thesis, Grenoble, 2013. http://www.theses.fr/2013GRENT033/document.
Testo completoAdvanced CMOS technologies provide an easier way to realize radio-frequency integrated circuits (RFICs). However, the lithography dimension shrink make electrostatic discharges (ESD) issues become more significant. Specific ESD protection devices are embedded in RFICs to avoid any damage. Unfortunately, ESD protections parasitic capacitance limits the operating bandwidth of RFICs. ESD protection size dimensions are also an issue for the protection of RFICs, in order to avoid a significant increase in production costs. This work focuses on a broadband ESD solution (DC-100 GHz) able to be implemented in an I/O pad to protect RFICs in advanced CMOS technologies. Thanks to the signal transmission properties of coplanar / microstrip lines, a broadband ESD solution is achieved by implementing ESD components under a transmission line. The silicon proved structure is broadband; it can be used in any RF circuits and fulfill ESD target. The physical dimensions also enable easy on-chip integration
Le, Goulven Katell. "Dispositifs institutionnels et integration des marches la commercialisation du porc au vietnam". Montpellier, ENSA, 2000. http://www.theses.fr/2000ENSA0012.
Testo completoMaggioni, Mezzomo Cécilia. "Caractérisation et modélisation des fluctuations aléatoires des paramètres électriques des dispositifs en technologies CMOS avancées". Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00987632.
Testo completoMaggioni, Mezzomo Cecilia. "Caractérisation et modélisation des fluctuations aléatoires des paramètres électriques des dispositifs en technologies CMOS avancées". Thesis, Grenoble, 2011. http://www.theses.fr/2011GRENT044/document.
Testo completoThis research characterizes and models the mismatch of electrical parameters in advanced MOS transistors. All characterizations are made through a test structure, which is experimentally validated using a structure based on Kelvin method. A model, valid in the linear region, is proposed. It is used for modeling the threshold voltage fluctuations of the transistors with pocket-implants, for any transistor length and gate voltage. It gives a deep understanding of the mismatch, especially for devices with non-uniform channel. Another study analyzes the mismatch of the drain current by characterizing and modeling in terms of the drain voltage. A second model is then proposed for transistors without pocket-implants. In order to apply this model, the correlation of threshold voltage fluctuations and mobility fluctuations must be considered. Characterizations are also performed on transistors with pocket-implants, showing a new drain current mismatch behavior for long transistors. Finally, characterizations are made to analyze the impact of gate roughness fluctuations on mismatch
Hossri, Nabil al. "Etude du phénomène métastable dans les dispositifs bistables de technologie CMOS modélisation, caractérisation et simulation". Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37598345s.
Testo completoHossri, Nabil al. "Etude du phénomène métastable dans les dispositifs bistables de technologie CMOS : modélisation, caractérisation et simulation". Bordeaux 1, 1986. http://www.theses.fr/1986BOR10868.
Testo completoLibri sul tema "Dispositifs CMOS et integration"
Faire société sans faire souffrir?: Les dispositifs vecteurs de cohésion sociale et leurs victimes. Paris: Harmattan, 2005.
Cerca il testo completoAnalog Vlsi Design: Nmos and Cmos (Silicon Systems Engineering Series). Prentice Hall, 1988.
Cerca il testo completoVLSI and Post-CMOS Electronics: Devices, Circuits and Interconnects. Institution of Engineering & Technology, 2019.
Cerca il testo completoVLSI and Post-CMOS Electronics: Design, Modelling and Simulation. Institution of Engineering & Technology, 2019.
Cerca il testo completoDhiman, Rohit, e Rajeevan Chandel. VLSI and Post-CMOS Electronics: Devices, Circuits and Interconnects, Volume 2. Institution of Engineering & Technology, 2019.
Cerca il testo completoDhiman, Rohit, e Rajeevan Chandel. VLSI and Post-CMOS Electronics: Design, Modelling and Simulation, Volume 1. Institution of Engineering & Technology, 2019.
Cerca il testo completoCapitoli di libri sul tema "Dispositifs CMOS et integration"
VUILLAUME, Dominique. "Électronique moléculaire : transport d’électrons, de spins et de chaleur". In Au-delà du CMOS, 259–300. ISTE Group, 2024. http://dx.doi.org/10.51926/iste.9127.ch7.
Testo completoVITALE, Steven A. "Valléetronique dans les matériaux 2D". In Au-delà du CMOS, 215–57. ISTE Group, 2024. http://dx.doi.org/10.51926/iste.9127.ch6.
Testo completoCAO, Wei, e Kaustav BANERJEE. "Transistors à effet de champ à capacité négative". In Au-delà du CMOS, 83–111. ISTE Group, 2024. http://dx.doi.org/10.51926/iste.9127.ch3.
Testo completoAtti di convegni sul tema "Dispositifs CMOS et integration"
Pu, R., R. Jurrat, E. M. Hayes, C. W. Wilmsen, K. D. Choquette e K. M. Geib. "Optical processing arrays based on VCSELs bonded directly to GaAs smart pixels". In Spatial Light Modulators. Washington, D.C.: Optica Publishing Group, 1997. http://dx.doi.org/10.1364/slmo.1997.smb.4.
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