Bibliografie tematiche / Computer software Verification

Letteratura scientifica selezionata sul tema "Computer software Verification"

Autore: Grafiati

Pubblicato: 4 giugno 2021

Ultima modifica: 31 gennaio 2023

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Articoli di riviste sul tema "Computer software Verification"

Goerigk, Wolfgang. "Mechanical Software Verification". Electronic Notes in Theoretical Computer Science 58, n. 2 (novembre 2001): 117–37. http://dx.doi.org/10.1016/s1571-0661(04)00282-8.

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Kwiatkowska, Marta. "From software verification to ‘everyware’ verification". Computer Science - Research and Development 28, n. 4 (7 settembre 2013): 295–310. http://dx.doi.org/10.1007/s00450-013-0249-1.

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Dobrescu, Mihai, e Katerina Argyraki. "Software dataplane verification". Communications of the ACM 58, n. 11 (23 ottobre 2015): 113–21. http://dx.doi.org/10.1145/2823400.

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Malkis, Alexander, e Anindya Banerjee. "Verification of software barriers". ACM SIGPLAN Notices 47, n. 8 (11 settembre 2012): 313–14. http://dx.doi.org/10.1145/2370036.2145871.

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Halpern, J. D., S. Owre, N. Proctor e W. F. Wilson. "Muse—A Computer Assisted Verification System". IEEE Transactions on Software Engineering SE-13, n. 2 (febbraio 1987): 151–56. http://dx.doi.org/10.1109/tse.1987.226477.

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Flanagan, Cormac, e Shaz Qadeer. "Predicate abstraction for software verification". ACM SIGPLAN Notices 37, n. 1 (gennaio 2002): 191–202. http://dx.doi.org/10.1145/565816.503291.

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Greengard, Samuel. "Formal software verification measures up". Communications of the ACM 64, n. 7 (luglio 2021): 13–15. http://dx.doi.org/10.1145/3464933.

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Andersen, B. Scott, e George Romanski. "Verification of safety-critical software". Communications of the ACM 54, n. 10 (ottobre 2011): 52–57. http://dx.doi.org/10.1145/2001269.2001286.

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Andersen, B. Scott, e George Romanski. "Verification of Safety-critical Software". Queue 9, n. 8 (agosto 2011): 50–59. http://dx.doi.org/10.1145/2016036.2024356.

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Hailpern, B., e P. Santhanam. "Software debugging, testing, and verification". IBM Systems Journal 41, n. 1 (2002): 4–12. http://dx.doi.org/10.1147/sj.411.0004.

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Tesi sul tema "Computer software Verification"

Dimovski, Aleksandar. "Compositional software verification based on game semantics". Thesis, University of Warwick, 2007. http://wrap.warwick.ac.uk/2398/.

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Abstract (sommario):

One of the major challenges in computer science is to put programming on a firmer mathematical basis, in order to improve the correctness of computer programs. Automatic program verification is acknowledged to be a very hard problem, but current work is reaching the point where at least the foundationalÃ?Â· aspects of the problem can be addressed and it is becoming a part of industrial software development. This thesis presents a semantic framework for verifying safety properties of open sequ;ptial programs. The presentation is focused on an Algol-like programming language that embodies many of the core ingredients of imperative and functional languages and incorporates data abstraction in its syntax. Game semantics is used to obtain a compositional, incremental way of generating accurate models of programs. Model-checking is made possible by giving certain kinds of concrete automata-theoretic representations of the model. A data-abstraction refinement procedure is developed for model-checking safety properties of programs with infinite integer types. The procedure starts by model-checking the most abstract version of the program. If no counterexample, or a genuine one, is found, the procedure terminates. Otherwise, it uses a spurious counterexample to refine the abstraction for the next iteration. Abstraction refinement, assume-guarantee reasoning and the L* algorithm for learning regular languages are combined to yield a procedure for compositional verification. Construction of a global model is avoided using assume-guarantee reasoning and the L* algorithm, by learning assumptions for arbitrary subprograms. An implementation based on the FDR model checker for the CSP process algebra demonstrates practicality of the methods.

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Addy, Edward A. "Verification and validation in software product line engineering". Morgantown, W. Va. : [West Virginia University Libraries], 1999. http://etd.wvu.edu/templates/showETD.cfm?recnum=1068.

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Thesis (Ph. D.)--West Virginia University, 1999.
Title from document title page. Document formatted into pages; contains vi, 75 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 35-39).

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Wahab, Matthew. "Object code verification". Thesis, University of Warwick, 1998. http://wrap.warwick.ac.uk/61068/.

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Object code is a program of a processor language and can be directly executed on a machine. Program verification constructs a formal proof that a program correctly implements its specification. Verifying object code therefore ensures that the program which is to be executed on a machine is correct. However, the nature of processor languages makes it difficult to specify and reason about object code programs in a formal system of logic. Furthermore, a proof of the correctness of an object code program will often be too large to construct manually because of the size of object code programs. The presence of pointers and computed jumps in object code programs constrains the use of automated tools to simplify object code verification. This thesis develops an abstract language which is expressive enough to describe any sequential object code program. The abstract language supports the definition of program logics in which to specify and verify object code programs. This allows the object code programs of any processor language to be verified in a single system of logic. The abstract language is expressive enough that a single command is enough to describe the behaviour of any processor instruction. An object code program can therefore be translated to the abstract language by replacing each instruction with the equivalent command of the abstract language. This ensures that the use of the abstract language does not increase the difficulty of verifying an object code program. The verification of an object code program can be simplified by constructing an abstraction of the program and showing that the abstraction correctly implements the program specification. Methods for abstracting programs of the abstract language are developed which consider only the text of a program. These methods are based on describing a finite sequence of commands as a single, equivalent, command of the abstract language. This is used to define transformations which abstract a program by replacing groups of program commands with a single command. The abstraction of a program formed in this way can be verified in the same system of logic as the original program. Because the transformations consider only the program text, they are suitable for efficient mechanisation in an automated proof tool. By reducing the number of commands which must be considered, these methods can reduce the manual work needed to verify a program. The use of an abstract language allows object code programs to be specified and verified in a system of logic while the use of abstraction to simplify programs makes verification practical. As examples, object code programs for two different processors are modelled, abstracted and verified in terms of the abstract language. Features of processor languages and of object code programs which affect verification and abstraction are also summarised.

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Swart, Riaan. "A language to support verification of embedded software". Thesis, Stellenbosch : Stellenbosch University, 2004. http://hdl.handle.net/10019.1/49823.

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Thesis (MSc)--University of Stellenbosch, 2004.
ENGLISH ABSTRACT: Embedded computer systems form part of larger systems such as aircraft or chemical processing facilities. Although testing and debugging of such systems are difficult, reliability is often essential. Development of embedded software can be simplified by an environment that limits opportunities for making errors and provides facilities for detection of errors. We implemented a language and compiler that can serve as basis for such an experimental environment. Both are designed to make verification of implementations feasible. Correctness and safety were given highest priority, but without sacrificing efficiency wherever possible. The language is concurrent and includes measures for protecting the address spaces of concurrently running processes. This eliminates the need for expensive run-time memory protection and will benefit resource-strapped embedded systems. The target hardware is assumed to provide no special support for concurrency. The language is designed to be small, simple and intuitive, and to promote compile-time detection of errors. Facilities for abstraction, such as modules and abstract data types support implementation and testing of bigger systems. We have opted for model checking as verification technique, so our implementation language is similar in design to a modelling language for a widely used model checker. Because of this, the implementation code can be used as input for a model checker. However, since the compiler can still contain errors, there might be discrepancies between the implementation code written in our language and the executable code produced by the compiler. Therefore we are attempting to make verification of executable code feasible. To achieve this, our compiler generates code in a special format, comprising a transition system of uninterruptible actions. The actions limit the scheduling points present in processes and reduce the different interleavings of process code possible in a concurrent system. Requirements that conventional hardware places on this form of code are discussed, as well as how the format influences efficiency and responsiveness.
AFRIKAANSE OPSOMMING: Ingebedde rekenaarstelsels maak deel uit van groter stelsels soos vliegtuie of chemiese prosesseerfasiliteite. Hoewel toetsing en ontfouting van sulke stelsels moeilik is, is betroubaarheid dikwels onontbeerlik. Ontwikkeling van ingebedde sagteware kan makliker gemaak word met 'n ontwikkelingsomgewing wat geleenthede vir foutmaak beperk en fasiliteite vir foutbespeuring verskaf. Ons het 'n programmeertaal en vertaler geïmplementeer wat as basis kan dien vir so 'n eksperimentele omgewing. Beide is ontwerp om verifikasie van implementasies haalbaar te maak. Korrektheid en veiligheid het die hoogste prioriteit geniet, maar sonder om effektiwiteit prys te gee, waar moontlik. Die taal is gelyklopend en bevat maatreëls om die adresruimtes van gelyklopende prosesse te beskerm. Dit maak duur looptyd-geheuebeskerming onnodig, tot voordeel van ingebedde stelsels met 'n tekort aan hulpbronne. Daar word aangeneem dat die teikenhardeware geen spesiale ondersteuning vir gelyklopendheid bevat nie. Die programmeertaal is ontwerp om klein, eenvoudig en intuïtief te wees, en om vertaaltyd-opsporing van foute te bevorder. Fasiliteite vir abstraksie, byvoorbeeld modules en abstrakte datatipes, ondersteun implementering en toetsing van groter stelsels. Ons het modeltoetsing as verifikasietegniek gekies, dus is die ontwerp van ons programmeertaal soortgelyk aan dié van 'n modelleertaal vir 'n modeltoetser wat algemeen gebruik word. As gevolg hiervan kan die implementasiekode as toevoer vir 'n modeltoetser gebruik word. Omdat die vertaler egter steeds foute kan bevat, mag daar teenstrydighede bestaan tussen die implementasie geskryf in ons implementasietaal, en die uitvoerbare masjienkode wat deur die vertaler gelewer word. Daarom poog ons om verifikasie van die uitvoerbare masjienkode haalbaar te maak. Om hierdie doelwit te bereik, is ons vertaler ontwerp om 'n spesiale formaat masjienkode te genereer bestaande uit 'n oorgangstelsel wat ononderbreekbare (atomiese) aksies bevat. Die aksies beperk die skeduleerpunte in prosesse en verminder sodoende die aantal interpaginasies van proseskode wat moontlik is in 'n gelyklopende stelsel. Die vereistes wat konvensionele hardeware aan dié spesifieke formaat kode stel, word bespreek, asook hoe die formaat effektiwiteit en reageerbaarheid van die stelsel beïnvloed.

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Wang, Xuan. "Verification of Digital Controller Verifications". BYU ScholarsArchive, 2005. https://scholarsarchive.byu.edu/etd/681.

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This thesis presents an analysis framework to verify the stablility property of a closed-loop control system with a software controller implementation. The usual approach to verifying stability for software uses experiments which are costly and can be dangerous. More recently, mathematical models of software have been proposed which can be used to reason about the correctness of controllers. However, these mathematical models ignore computational details that may be important in verification. We propose a method to determine the instability of a closed-loop system with a software controller implementation under l^2 inputs using simulation. This method avoids the cost of experimentation and the loss of precision inherent in mathematical modeling. The method uses the small gain theorem to compute a lower bound on the 2-induced norm of the uncertainty in the software implementation; if the lower bound is greater than 1/(2-induced norm of G), where G is the feedback system consisting of the mathematical model of the plant and the mathematical model of the controller, the closed-loop system is unsafe in a certain sense. The resulting method can not determine if the closed-loop system is stable, but can only suggest instability.

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Tagore, Aditi. "Techniques to Improve Automated Software Verification". The Ohio State University, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=osu1397661277.

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Kirschenbaum, Jason P. "Investigations in Automating Software Verification". The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1306862918.

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Hughes, Roger Brett. "Automated interactive software verification and synthesis". Thesis, Brunel University, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.306741.

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Jackson, David Mark. "Logical verification of reactive software systems". Thesis, University of Oxford, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.305989.

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Ibrahim, Alaa E. "Scenario-based verification and validation of dynamic UML specifications". Morgantown, W. Va. : [West Virginia University Libraries], 2001. http://etd.wvu.edu/templates/showETD.cfm?recnum=1799.

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Thesis (M.S.)--West Virginia University, 2001.
Title from document title page. Document formatted into pages; contains x, 143 p. : ill. (some col.). Vita. Includes abstract. Includes bibliographical references (p. 96-99).

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Libri sul tema "Computer software Verification"

1943-, Kurshan R. P., a cura di. Computer-aided verification. Boston: Kluwer Academic Publishers, 1992.

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Nissim, Francez. Program verification. Wokingham, Eng: Addison-Wesley Pub. Co., 1992.

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Nachum, Dershowitz, e Manna Zohar, a cura di. Verification: Theory and practice : essays dedicated to Zohar Manna on the occasion of his 64th birthday. Berlin: Springer-Verlag, 2004.

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Apt, Krzysztof R. Verification of sequential and concurrent programs. New York: Springer-Verlag, 1991.

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Apt, Krzysztof R. Verification of sequential and concurrent programs. 2^a ed. New York: Springer-Verlag, 1997.

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1952-, Colburn Timothy R., Fetzer James H. 1940- e Rankin Terry L, a cura di. Program verification: Fundamental issues in computer science. Dordrecht: Kluwer Academic Publishers, 1993.

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Almeida, José Bacelar. Rigorous software development: An introduction to program verification. London: Springer, 2011.

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Bergé, Jean-Michel. Hardware/Software Co-Design and Co-Verification. Boston, MA: Springer US, 1997.

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Jean-Michel, Bergé, Levia Oz e Rouillard Jacques, a cura di. Hardware/software co-design and co-verification. Boston: Kluwer Academic Publishers, 1997.

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Hoare, C. A. R., M. Broy e Christian Leuxner. Software and systems safety: Specification and verification. Amsterdam: IOS Press, 2011.

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Capitoli di libri sul tema "Computer software Verification"

Revesz, Peter. "Software Verification". In Texts in Computer Science, 685–99. London: Springer London, 2009. http://dx.doi.org/10.1007/978-1-84996-095-3_26.

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Weik, Martin H. "software verification". In Computer Science and Communications Dictionary, 1611. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_17667.

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Peled, Doron A. "Deductive Software Verification". In Texts in Computer Science, 179–213. New York, NY: Springer New York, 2001. http://dx.doi.org/10.1007/978-1-4757-3540-6_7.

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Weik, Martin H. "automated software verification". In Computer Science and Communications Dictionary, 81. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_1068.

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Cimatti, Alessandro, e Alberto Griggio. "Software Model Checking via IC3". In Computer Aided Verification, 277–93. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-31424-7_23.

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Hoare, Tony. "The Ideal of Verified Software". In Computer Aided Verification, 5–16. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11817963_4.

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Holzmann, Gerard_J. "Software Analysis and Model Checking". In Computer Aided Verification, 1–16. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45657-0_1.

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Cousot, Patrick, e Radhia Cousot. "On Abstraction in Software Verification". In Computer Aided Verification, 37–56. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45657-0_3.

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Ivančić, F., Z. Yang, M. K. Ganai, A. Gupta, I. Shlyakhter e P. Ashar. "F-Soft: Software Verification Platform". In Computer Aided Verification, 301–6. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11513988_31.

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van der Berg, Freark I. "LLMC: Verifying High-Performance Software". In Computer Aided Verification, 690–703. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81688-9_32.

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AbstractMulti-threaded unit tests for high-performance thread-safe data structures typically do not test all behaviour, because only a single scheduling of threads is witnessed per invocation of the unit tests. Model checking such unit tests allows to verify all interleavings of threads. These tests could be written in or compiled to LLVM IR. Existing LLVM IR model checkers like divine and Nidhugg, use an LLVM IR interpreter to determine the next state. This paper introduces llmc, a multi-core explicit-state model checker of multi-threaded LLVM IR that translates LLVM IR to LLVM IR that is executed instead of interpreted. A test suite of 24 tests, stressing data structures, shows that on average llmc clearly outperforms the state-of-the-art tools divine and Nidhugg.

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Atti di convegni sul tema "Computer software Verification"

Usener, Claus A., Susanne Gruttmann, Tim A. Majchrzak e Herbert Kuchen. "Computer-Supported Assessment of Software Verification Proofs". In 2010 International Conference on Educational and Information Technology (ICEIT). IEEE, 2010. http://dx.doi.org/10.1109/iceit.2010.5607766.

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Mukherjee, Rajdeep, Daniel Kroening e Tom Melham. "Hardware Verification Using Software Analyzers". In 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2015. http://dx.doi.org/10.1109/isvlsi.2015.107.

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Asadollahi, Somayeh, Vahid Rafe e Reza Rafeh. "Towards Automated Software Verification and Validation". In 2009 International Conference on Computer Technology and Development. IEEE, 2009. http://dx.doi.org/10.1109/icctd.2009.164.

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Grimm, Tomas, Djones Lettnin e Michael Hubner. "Semiformal Verification of Software-Controlled Connections". In 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2017. http://dx.doi.org/10.1109/isvlsi.2017.103.

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Biswas, M. A. Rafe, Samuel Garcia, Matthew Prado, Sadad Hossain, Matthew Souris e Lee Morin. "Software verification of Orion cockpit displays". In 2017 12th International Conference on Computer Science and Education (ICCSE). IEEE, 2017. http://dx.doi.org/10.1109/iccse.2017.8085474.

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Cruz, Daniela da, Pedro Rangel Henriques e Jorge Sousa Pinto. "Interactive Verification of Safety-Critical Software". In 2013 IEEE 37th Annual Computer Software and Applications Conference (COMPSAC). IEEE, 2013. http://dx.doi.org/10.1109/compsac.2013.86.

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Chao Wang, Malay Ganai, Shuvendu Lahiri e Daniel Kroening. "Embedded software verification: Challenges and solutions". In 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2008. http://dx.doi.org/10.1109/iccad.2008.4681536.

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Ding Zheng, Yichen Wang e Zou Xueyi. "The methods of FPGA software verification". In 2011 IEEE International Conference on Computer Science and Automation Engineering (CSAE). IEEE, 2011. http://dx.doi.org/10.1109/csae.2011.5952639.

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Craig, D. C., e W. M. Zuberek. "Compatibility of Software Components - Modeling and Verification". In 2006 International Conference on Dependability of Computer Systems. IEEE, 2006. http://dx.doi.org/10.1109/depcos-relcomex.2006.13.

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Lettnin, Djones, Markus Winterholer, Axel Braun, Joachim Gerlach, Jurgen Ruf, Thomas Kropf e Wolfgang Rosenstiel. "Coverage Driven Verification applied to Embedded Software". In IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07). IEEE, 2007. http://dx.doi.org/10.1109/isvlsi.2007.33.

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