Tesi sul tema "CMOS Device and Integration"
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Darwish, Mohamed. "Graphene Devices for Beyond-CMOS Heterogeneous Integration". Research Showcase @ CMU, 2017. http://repository.cmu.edu/dissertations/1072.
Testo completoHållstedt, Julius. "Integration of epitaxial SiGe(C) layers in advanced CMOS devices /". Stockholm : Kungliga Tekniska högskolan, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4498.
Testo completoHållstedt, Julius. "Integration of epitaxial SiGe(C) layers in advanced CMOS devices". Doctoral thesis, KTH, Mikroelektronik och tillämpad fysik, MAP, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4498.
Testo completoQC 20100715
Pacella, Nan Yang. "Platform for monolithic integration of III-V devices with Si CMOS technology". Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/76119.
Testo completoCataloged from PDF version of thesis.
Includes bibliographical references (p. 169-165).
Monolithic integration of III-V compound semiconductors and Si complementary metal-oxide- semiconductor (CMOS) enables the creation of advanced circuits with new functionalities. In order to merge the two technologies, compatible substrate platforms and processing approaches must be developed. The Silicon on Lattice Engineered Silicon (SOLES) substrate allows monolithic integration. It is a Si substrate with embedded III-V template layer, which supports epitaxial IIIV device growth, consistent with present II-V technology. The structure is capped with a silicon-on-insulator (SOI) layer, which enables processing of CMOS devices. The processes required for fabricating and utilizing SOLES wafers which have Ge or InP as the III-V template layers are explored. Allowable thermal budgets are important to consider because the substrate must withstand the thermal budget of all subsequent device processing steps. The maximum processing temperature of Ge SOLES is found to be limited by its melting point. However, Ge diffuses through the buried Si0 2 and must be contained. Solutions include 1) limiting device processing thermal budgets, 2) improving buried silicon dioxide quality and 3) incorporating a silicon nitride diffusion barrier. InP SOLES substrates are created using wafer bonding and layer transfer of silicon, SOI and InP-on-Si wafers, established using a two-step growth method. Two different InP SOLES structures are demonstrated and their allowable thermal budgets are investigated. The thermal budgets appear to be limited by low quality silicon dioxide used for wafer bonding. For ultimate integration, parallel metallization of the III-V and CMOS devices is sought. A method of making ohmic contact to III-V materials through Si encapsulation layers, using Si CMOS technology, is established. The metallurgies and electrical characteristics of nickel silicide structures on Si/III-V films are investigated and the NiSi/Si/III-V structure is found to be optimal. This structure is composed of a standard NiSi/Si interface and novel Si/III-V interface. Specific contact resistivity of the double hetero-interface stack can be tuned by controlling Si/IIIV band alignments at the epitaxial growth interface. P-type Si/GaAs interfaces and n-type Si/InGaAs interfaces create ohmic contacts with the lowest specific contact resistivity and present viable structures for integration. A Si-encapsulated GaAs/AlGaAs laser with NiSi front-side contact is demonstrated and confirms the feasibility of these contact structures.
by Nan Yang Pacella.
Ph.D.
London, Joanna M. 1974. "Wafer bonding for monolithic integration of Si CMOS VLSI electronics with III-V optoelectronic devices". Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/45498.
Testo completoIncludes bibliographical references (p. 90-91).
GaAs-on-silicon epitaxy techniques as well as wafer bonding GaAs to Si, have been developed to overcome lattice mismatch in order to integrate optoelectronic and Si devices. However, the thermal expansion differences between these materials continues to be a limitation in using either of these approaches. After recognizing that Si devices, such as MOSFETs, are intrinsically thin and relatively strain tolerant, while optoelectronic devices, such as LEDs and lasers, are thick and very strain sensitive, this research was based on developing a better approach which involved bonding thin Si layers to thick GaAs substrates with various dielectric layers as the interface, to produce silicon-on-gallium arsenide (SonG) wafers. Such wafers are suitable for the fabrication of Si SOICMOS electronics and the subsequent monolithic integration of high performance optoelectronic devices. Future goals for this work include bonding fully processed SOI-CMOS wafers to the GaAs, rather than silicon wafers containing no electronics. With the successful development of SonG techniques for monolithic integration, it will be possible to use full-wafer and batch processing techniques for the production of sophisticated economically viable optoelectronic integrated circuits.
by Joanna M. London.
S.M.
Riverola, Borreguero Martín. "Micro and Nano-electro-mechanical devices in the CMOS back end and their applications". Doctoral thesis, Universitat Autònoma de Barcelona, 2017. http://hdl.handle.net/10803/458694.
Testo completoRecently, several new emerging devices are starting to be explored because the traditional down-scaling approach of the complementary metal-oxide-semiconductor (CMOS) technology (often called “More Moore”) is reaching fundamental limits; mainly due to non-zero transistor off-state leakage. This brand-new domain that goes beyond the boundaries of Moore’s law is commonly named ``More than Moore'' and is driving interest in new devices for information processing and memory, new technologies for heterogeneous integration of multiple functions, and new paradigms for system architecture. One of these new promising technologies for logic and information processing is the micro- and nanoelectromechanical (M/NEM) relay technology, because of its immeasurably low off-state leakage current and super-steep switching behavior. This dissertation proposes to explore the possibilities of leveraging the available layers of the commercial CMOS technology AMS 0.35 µm to implement M/NEM relays. Specifically, two different approaches are explored: in-plane actuated relays defined using solely the via layer, and torsional actuated relays formed with metal and via layers (usually named composite) while supported by vias. Both approaches are supported by the tungsten VIA3 layer, which includes key features such as high hardness, high melting point, low stress and resistance to hydrofluoric (HF) acid, since the mechanical structures are released in a maskless post-CMOS process based on a wet HF enchant. Based on the key structural features that the developed relays showed, MEMS resonators based on the VIA3 platform were also fabricated. In this dissertation, we also present a particular contribution involving the design and characterization of a dual-frequency oscillator that consist of such reliable torsional tungsten resonators and a high gain, low power and ultra-compact transimpedance amplifier (TIA). Finally and parallel to the main thread of this dissertation, RF MEMS switched capacitors are developed as a result of the collaboration with the semiconductor manufacturing enterprise SilTerra Malaysia Sdn. Bhd. These devices have the particularity of being fully integrated into the process flow of a low cost, commercial 180 nm CMOS technology (using the SilTerra MEMS-on-CMOS process platform).
Pearson, Brian (Brian Sung-Il). "Large grain Ge growth on amorphous substrates for CMOS back-end-of-line integration of active optoelectronic devices". Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/78240.
Testo completoCataloged from PDF version of thesis.
Includes bibliographical references (p. 97-104).
The electronic-photonic integrated circuit (EPIC) has emerged as a leading technology to surpass the interconnect bottlenecks that threaten to limit the progress of Moore's Law in microprocessors. Compared to conventional metal interconnects, photonic interconnects have the potential to increase bandwidth density while simultaneously reducing power consumption. However, photonic devices are orders of magnitude larger than electronic devices and therefore consume valuable substrate real estate. The ideal solution, in order to take advantage of optical interconnects without decreasing transistor counts, is to monolithically implement dense threedimensional integration of electronics and photonics. This involves moving the photonic devices off the substrate, and into the metal interconnect stack. Moving photonic devices into the interconnect stack imposes two fabrication limitations. First, the available thermal budget allowed for photonic device processing is limited to 450 °C. Second, the metal interconnects are embedded within amorphous dielectrics and therefore there is no crystalline seed to initiate epitaxial growth. This thesis addresses two major barriers for integration of photonics in the back end: (1) how to fabricate high quality Ge for active regions of optoelectronic devices while adhering to back-end processing constraints, and (2) how to couple optical power to these devices. First, an approach was developed to fabricate the active region of Ge-based optoelectronic devices. A new technique, known as two-dimensional geometrically confined lateral growth (2D GCLG), has demonstrated single crystalline Ge on an amorphous substrate. This thesis presents the first application of the 2D GCLG technique to fill a lithographically defined Si0 2 trench with large grain Ge, while adhering to back-end processing constraints. A modified design is then proposed to increases the yield of 2D GCLG structures. This trench filling technique is an integral step towards fabricating Ge-based optoelectronic devices that are capable of being integrated into the back-end of a microprocessor. Once it was established that high quality Ge trenches could be fabricated in the back-end, optical coupling to devices was addressed. For dense three-dimensional integration of photonic devices, vertical coupling between photonic planes is necessary. Therefore, this thesis begins with the design and simulation of vertical couplers. These couplers utilize evanescent coupling between two overlapping inversely tapered waveguides, which ensure efficient coupling due to optical impedance matching. These couplers are designed to exhibit coupling efficiencies in excess of 98.4%, equivalent to a 0.07 dB coupling loss. The technique of evanescent coupling between overlapping inverse tapers is then applied to electro-absorption modulators (EAMs). A design for low-loss evanescent coupling from a waveguide to a Ge EAM is modeled and optimized. The design implements lateral evanescent coupling from overlapping inverse taper structures. Simulation results show that the coupling efficiency into and out of the modulator can be as high as 99%, equivalent to a 0.04 dB coupling loss.
by Brian Pearson.
S.M.
Smith, Anderson. "Graphene-based Devices for More than Moore Applications". Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-188134.
Testo completoQC 20160610
Bari, Mohammad Rezaul. "Fabrication, Characterization, and Modelling of Self-Assembled Silicon Nanostructure Vacuum Field Emission Devices". Thesis, University of Canterbury. Electrical and Computer Engineering, 2011. http://hdl.handle.net/10092/6601.
Testo completoDubreuil, Théophile. "Architecture 3D 1T1R innovante à base de RRAMs pour le calcul hyperdimensionnel". Electronic Thesis or Diss., Université Grenoble Alpes, 2023. http://www.theses.fr/2023GRALT085.
Testo completoIn the years to come, due to the insatiable need for data-intensive machine learning applications, a drastic expansion of computing power is required to confront a veritable “data deluge”. To meet this challenge, high-performance In-Memory-Computing (IMC) architectures require the development of novel storage devices that are also suited for local computations. In this context, this thesis work presents a novel 3D 1T1R memory array derived from vertically stacked-nanosheet technology, which is used for Hyperdimensional Computing (HDC), an error-resilient and highly parallel brain-inspired computing paradigm. Firstly, the IMC paradigm can greatly benefit from novel 3D non-volatile memory (NVM) architectures which increase the density and the computing performances. However, the fabrication challenges and parasitics can greatly limit the potential benefits of these architectures. With the 3D 1T1R technology, made by coupling new disruptive gate-independent stacked-nanosheets with drain-based RRAM cells, we show that some of these issues can be overcome, thus leading to high-density 3D NVM arrays. We demonstrate various technological modules necessary for the fabrication of 3D 1T1R structures. Devices are fabricated and electrically characterized for both storage and computing applications. In particular, functional MEOL drain-based RRAM cells are demonstrated with a doped-Si bottom electrode for various types of selector technologies. Finally, we propose a full-IMC architecture of HDC to take advantage of the 3D 1T1R structure. Different hardware implementations are proposed and compared with SPICE simulations. We also show with software-based simulations that language and gesture recognition can be realistically performed with our 3D 1T1R implementation
Xu, Cuiqin. "Optimisation du procédé de réalisation pour l'intégration séquentielle 3D des transistors CMOS FDSOI". Phd thesis, Université de Grenoble, 2012. http://tel.archives-ouvertes.fr/tel-00771763.
Testo completoLabalette, Marina. "Intégration 3D de dispositifs mémoires résistives complémentaires dans le back end of line du CMOS". Thesis, Lyon, 2018. http://www.theses.fr/2018LYSEI037/document.
Testo completoIn our digital era, management, manipulation and data storage are real challenges. To support this reality the need for more efficient, less energy and money consuming memory technologies is drastically increasing. Among those emerging memory technologies we find the oxide resistive memory technology (OxRRAM), where the information is stored as the electrical resistance of a switching oxide in sandwich between two metallic electrodes. Resistive memories are really interested if used inside passive memory matrix. However the main drawback of this architecture remains related to sneak path currents occurring when addressing any point in the passive matrix. To face this problem complementary resistive switching devices (CRS), consisting in two OxRRAM back to back, have been proposed as efficient and costless BEOL CMOS compatible solution. This thesis brought the proof of concept of fabrication and 3D monolithic integration of CRS devices in CMOS BEOL
Price, David T. "N-Well CMOS process integration /". Online version of thesis, 1992. http://hdl.handle.net/1850/11261.
Testo completoChen, Tingsu. "Spin Torque Oscillator Modeling, CMOS Design and STO-CMOS Integration". Doctoral thesis, KTH, Integrerade komponenter och kretsar, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-176890.
Testo completoQC 20151112
Raja, Hamran, e Roshan Lee. "Integration of a Drainage Device". Thesis, KTH, Tillämpad maskinteknik (KTH Södertälje), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-190025.
Testo completoYu, Chuanzhao. "STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY". Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3551.
Testo completoPh.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
Lim, Desmond Rodney. "Device integration for silicon microphotonic platforms". Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/16784.
Testo completoAlso available online at the MIT Theses Online homepage
Includes bibliographical references (p. 199-211).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Silicon ULSI compatible, high index contrast waveguides and devices provide high density integration for optical networking and on-chip optical interconnects. Four such waveguide systems were fabricated and analyzed: crystalline silicon-on-insulator (SOI) strip, polycrystalline silicon (polySi) strip, silicon nitride strip and SPARROW waveguides. The loss of 15 dB/cm measured through an SOI waveguide was the smallest ever measured for a silicon strip waveguide and is due to improved side-wall roughness. The TM mode of a single mode polySi strip waveguide with a 1:2.5 aspect ratio exhibited, surprisingly, smaller loss than the TE mode. Further, analysis shows that high index contrast waveguides are more sensitive to polarization dependent loss in the presence of surface roughness. Single mode bends and splits in both silicon and silicon nitride were studied. 0.01 dB/turn loss has been measured for 2 micron radius silicon bends. Polarization dependent loss was also observed; the bending loss of a TM mode was, as expected, much larger than that of a TE mode. The splitting losses for two-degree Y-split was 0.15 dB/split. A 1x16 multi-mode interferometer splitter occupied an area of 480 sq-microns and exhibited loss of 3 dB. ULSI compatible waveguide structures integrated with micro-resonators have been studied. Qs of 10000 and efficiencies close to 100% were achieved in high index contrast ring resonators and Qs of 100 million were achieved in microsphere resonators. A thermal and mechanical tuning mechanism was demonstrated for micro-ring resonators.
(cont.) In addition, >95% coupling efficiency between SPARROW waveguides and microspheres was achieved, the first microspheres to be coupled to integrated optics waveguides. 1x4 wavelength division multiplexing devices have been, for the first time, demonstrated in high index contrast silicon and silicon nitride strip waveguide systems. These systems have a component density of 1-million devices/sq-cm. Higher order filters made from multiple rings exhibited flat top responses and the expected steeper roll-off resonance response. Integrated modulators and switches based on waveguides and rings were also studied. Finally, the integration of the components in systems applications was analyzed. A study of the effect of polarization and loss in silicon microphotonics waveguide systems is presented.
by Desmond Rodney Lim Chin Siong.
Ph.D.
Muñoz, Gamarra Jose Luis. "NEMS/MEMS integration in submicron CMOS Technologies". Doctoral thesis, Universitat Autònoma de Barcelona, 2014. http://hdl.handle.net/10803/285060.
Testo completoThe reduction of MEMS devices dimensions to the nano scale (NEMS) has allowed them to access a host of new physics and promise to revolutionize sensing applications. However this miniaturization has been obtained at an expense of dedicated, difficult and non reproducible fabrication processes. This thesis deals with the miniaturization of MEMS structures following a CMOS-MEMS approach. In order to it a small pitch CMOS technology (ST 65nm) is studied in depth, NEMS structures are defined using its available layers (width= 60 nm, thickness= 100nm in polysilicon and width= 90nm, thickness= 180nm in metal 1 based on copper) and a post-CMOS releasing process is developed in order to release them. Successful integration of NEMS devices is demostrated with the added value of a robust, reproducible fabrication and an easy integration with additional circuitry. However this aggressive scaling has a main drawback, small output signals. As an alternative to capacitive read-out, the implementation of a resonant gate transduction, based on the idea of modulate the charge of a transistor by the movement of a mechanical structure, is studied and implemented. The frequency response of a polysilicon resonator implemented in AMS 0.35um CMOS technology (24 MHz) has been successfully characterized and its operation as a low voltage switch (2.25 V pull-in) is demonstrated. In addition, we propose the use of mechanical switches not only as memory or logic devices (due to its energy efficiency), but also as the building blocks of a ring oscillator configuration composed exclusively by mechanical switches. This new approach extends their use to other application as mass sensing but with the added value of a digital output signal. In order to implement this new configuration a model to simulate its behavior is developed and mechanical switches are built using different CMOS technologies, trying always to reduce their dimensions. Low operating voltages (5 V, MIM approach), abrupt response (4.3 mV/decade, ST Metal 1) and good ION/IOFF ratio (1.104, MIM approach) are obtained.
Bruno, B. "Secure Mobile Device Integration for Automotive Telematics". Thesis, Honours thesis, University of Tasmania, 2005. https://eprints.utas.edu.au/241/1/bpbruno_Thesis.pdf.
Testo completoLippitt, Alex. "Development of a bioimpedance-based swallowing biofeedback device with smart device integration". Thesis, University of Canterbury. Electrical and Computer Engineering, 2015. http://hdl.handle.net/10092/10975.
Testo completoWu, Dongping. "Novel concepts for advanced CMOS : Materials, process and device architecture". Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3805.
Testo completoThe continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration.
High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO2and Al2O3as well as their mixtures are investigated assubstitutes for the traditionally used SiO2in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed.
A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode.
Key words:CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.
Xu, Chen. "Low voltage CMOS digital imaging architecture with device scaling considerations /". View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20XU.
Testo completoIncludes bibliographical references (leaves 131-136). Also available in electronic version. Access restricted to campus users.
Arcamone, Julien. "Integration of Nanomechanical Sensors on CMOS by Nanopatterning Methods". Doctoral thesis, Universitat Autònoma de Barcelona, 2007. http://hdl.handle.net/10803/5351.
Testo completoComo primer paso, dos tipos de resonadores nano/micromecánicos ('cantilevers' y 'quad-beams') se han modelado analíticamente para poder estudiar su respuesta frecuencial mecánica. Con el objetivo de excitarlos y detectarlos eléctricamente, se ha optado por una técnica capacitiva. Para poder prever el comportamiento eléctrico de la estructura mecánica se ha implementado un modelo mixto electromecánico. Luego se han estudiado las ventajas y la viabilidad de una integración monolítica con circuitería CMOS. En efecto, los NEMS/CMOS son sistemas que combinan extraordinarias propiedades de sensado, proporcionadas por la parte móvil mecánica, con la posibilidad de detectar la señal de salida en condiciones mucho más favorables: las capacidades parásitas son reducidas drásticamente al tratar dicha señal a través de una circuitería CMOS 'on-chip'. Por este motivo, se ha diseñado especialmente un circuito CMOS de lectura y de bajo consumo. Funciona como amplificador de transimpedancia para convertir la corriente creada por la resonancia mecánica en un voltaje de salida suficientemente alto. A partir de simulaciones, se ha analizado exhaustivamente (i) el comportamiento intrínseco de este circuito y (ii) cuando está acoplado al resonador mecánico.
Sin embargo, la fabricación de tales nanodispositivos integrados en CMOS constituía un reto ya que la integración a nivel de oblea entera de NEMS sobre CMOS mediante procesos no excesivamente costosos no había sido demostrada aún al inicio de esta tesis. Debido a esto, se puso en marcha una colaboración con el EPFL (École Polytechnique Fédérale de Lausanne, Suiza) para desarrollar la litografía 'nanostencil' con el objetivo de integrar a escala de oblea entera estructuras mesoscópicas (micro y nano) sobre circuitos CMOS pre-fabricados. Después de identificar los principales problemas iniciales, se ha podido desarrollar con éxito una tecnología de post-proceso que permite integrar NEMS en CMOS mediante una única etapa de litografía nanostencil. En paralelo, otro post-proceso basado en una etapa de litografía por haz de electrones ('e-beam lithography') se ha puesto a punto de manera que se pueden fabricar nuevos prototipos de nanodispositivos sobre CMOS en cortos plazos de tiempo.
La caracterización eléctrica de estos NEMS/CMOS se ha llevado a cabo tanto en aire como en vacío y se ha demostrado el correcto funcionamiento del dispositivo NEMS/CMOS fabricado. Han sido analizados los niveles de señal obtenidos experimentalmente y las características principales de los espectros de resonancia.
Finalmente, estos NEMS/CMOS han sido implementados como sensores de masa. Actualmente, esta aplicación de los NEMS es una de las más exploradas ya que los resonadores nano/micromecánicos ofrecen grandes ventajas en términos de sensibilidad e integración de sistemas comparados con las tradicionales microbalanzas de cuarzo. En este contexto, se han llevado a cabo cuatro experimentos diferentes: (i) en colaboración con un grupo de investigación en química física se ha estudiado mediante un resonador nano/micromecánico, utilizado como nano/microbalanza, la evaporación de gotas de volúmenes extremadamente reducidos, del orden del femtolitro (10-15), para profundizar en los conocimientos necesarios para el desarrollo de dispositivos de nano/microfluídica; (ii) una arquitectura nueva de resonador, basada en una palanca doble ('doble cantilever'), se ha diseñado y testeado. Este dispositivo novedoso permite hacer medidas de masa en condiciones ambientales con una auto-referencia proporcionando la incertidumbre de la medida; (iii) se han hecho pruebas de deposición en alto vacío de capas ultra-finas de oro (de espesor equivalente inferior a una mono-capa) sobre resonadores. De esa manera, se ha demostrado la gran sensibilidad en masa distribuida de estos dispositivos, en particular al comparar su respuesta con la de una microbalanza de cuarzo a la que superan por entre dos y tres ordenes de magnitud a nivel de sensibilidad; (iv) basándose en los resultados del experimento previo de deposición de oro, se está diseñando, y sigue en curso, un sistema 'quasi-dinámico' de litografía nanostencil junto con el EPFL. Este sistema consiste en efectuar deposiciones sucesivas de distintos materiales a través de un nanostencil desplazado entre cada deposición: de esa manera se obtienen multi-depósitos estructurados y ultra-puros. De manera muy novedosa, el sensor de masa NEMS/CMOS se utiliza aquí como sensor de alineamiento entre la membrana nanostencil y el substrato a litografiar.
This thesis has been a co-direction between Dr. F. Pérez-Murano from CNM-CSIC, Barcelona (Spain) and Pr. G. Brémond from INSA Lyon/INL-CNRS (France). This work involves two main aspects: one has to see with the modeling, the design and the operation of a nanomechanical device integrated on CMOS, and the other on nanofabrication techniques.
First, the mechanical and electrical behavior of electrostatically actuated nano/microresonators (cantilevers, bridges and quad-beams) embedded in a capacitive detection scheme have been analyzed. In such a scheme, the main issue comes from parasitic stray capacitances that can drastically degrade the performance of the transduction. Additionally, output parasitic capacitances arising from the measurement instrumentation can further reduce the available signal levels. In this sense, the advantages and the feasibility of a monolithic integration with CMOS circuitry have been studied. Indeed NEMS/CMOS are very promising systems which combine outstanding sensing attributes, thanks to the mobile mechanical part, with the possibility to electrically detect the output signal in enhanced conditions. Regarding the electrical response, such integration provides two major advantages: (i) reducing all the parasitic loads at the resonator output, and (ii) amplifying and conditioning 'on-chip' the resonance signal. Hence, a specific low-power CMOS readout circuit, whose function is to read out the capacitive current generated by a resonating nano/micromechanical device, has been designed. It is basically a transimpedance amplifier whose architecture is based on a second generation current conveyor. Its topology and the corresponding layout have been described and the circuit behavior (intrinsic and coupled to the NEMS) has been fully simulated. According to simulation results, the detection of the resonance of nano/microresonators is greatly enhanced through the CMOS integration.
Then, NEMS/CMOS devices have been fabricated combining a standard CMOS technology (CNM one) with emerging nanopatterning techniques, in particular with nanostencil lithography (nSL), of which the resolution and the conditions of applications have been optimized. Our works demonstrate the potential of nSL as a parallel, straightforward and CMOS compatible patterning technique to define at full wafer scale nanodevices on CMOS. These results represent the first time that an emerging nanolithography technique has been used to pattern multiple N-MEMS devices on a whole CMOS wafer in a parallel, potentially low-cost approach. The same strategy could be extended to other examples of nanodevices, such as single electron transistors on CMOS, for which there is at present no affordable technological process that fulfill the requirements of high resolution processing at wafer scale and CMOS compatibility.
After their fabrication, fully integrated nanomechanical resonators (cantilevers and quad-beams) have been extensively characterized electrically. Their mechanical resonance has been successfully sensed by the CMOS circuitry. Cantilevers and quad-beams have exhibited quality factors in vacuum up to 9500 and 7000 respectively. The resonance frequency could be tuned by varying the driving voltage and interesting hysteretic non-linear behaviors have been observed either in air or in vacuum
Finally, these resonators have been implemented as ultra-sensitive mass sensors in four different applications: in this way the extreme versatility and the high performance of such sensors has been demonstrated. Indeed, such ultra-sensitive nanosensors open up new possibilities of exploring new physical or chemical phenomena previously unattainable with any other tools. In the first experiment, wetting mechanisms of sessile droplets have been explored at very small scales (volumes in the femtoliter range) implementing the resonators as nano/microbalances. Such phenomena could not have been analyzed with traditional quartz microbalances whose mass resolution is more limited. In the second experiment, a new architecture of resonator based on a double nano/microcantilever has been designed and tested: this new device allows making reliable measurements under ambient conditions by providing a direct estimation of the measurement uncertainty.
The fact that NEMS-based mass sensors provide an unprecedented mass sensitivity and a very high spatial resolution inherent to their small size makes of them interesting devices for industrial applications as well. With regard to this matter, another experiment has consisted in monitoring in-situ the deposition of ultra-thin gold layers both with NEMS/CMOS and quartz-crystal microbalances. When measuring in real time the mass of these uniform deposits of thicknesses inferior to sub-monolayer, silicon nano/microresonators have exhibited a mass sensitivity better than QCM by between two and three orders of magnitude. This is very promising with regard to the possibility of replacing QCM in the semiconductor industry as a tool to monitor the deposition of thin layers. These outstanding mass sensing attributes have led us to apply such sensors as positioning sensors according to an innovative concept. In fact, CNM and EPFL are presently developing a 'quasi-dynamic' stencil lithography system. This system consists in performing successive depositions of several materials through a nanostencil shadow mask which is displaced in-between each deposition: in this way high-purity and structured multi-deposits can be obtained. In this context, NEMS/CMOS mass sensors are used as positioning sensors for the in-situ alignment between the movable nanostencil and the substrate to be patterned.
Martiny, Ingo. "Integration und Optimierung optoelektronischer Sensoren in Standard-CMOS-Prozessen". Düsseldorf VDI-Verl, 1999. http://deposit.d-nb.de/cgi-bin/dokserv?idn=975788728.
Testo completoCappellani, Annalisa. "Metal gate integration in CMOS logic for RF applications". Thesis, University of Newcastle Upon Tyne, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.366569.
Testo completoMoral, Cejudo Alberto Jose del. "Integration of vertical Single Electron Transistor into CMOS technology". Doctoral thesis, Universitat Autònoma de Barcelona, 2021. http://hdl.handle.net/10803/673762.
Testo completoEsta tesis presenta las investigaciones realizadas hacia la integración de transistores verticales de un solo electrón (SET) en tecnología metal-óxido-semiconductor complementario (CMOS). Dos de las principales motivaciones de la industria de semiconductores son la miniaturización de dispositivos y la reducción de consumo de energía. En los nodos más avanzados, las arquitecturas tridimensionales han ganado una importancia significativa para aumentar la densidad de integración, siendo los dispositivos dispuestos verticalmente los candidatos más adecuados para las generaciones más recientes. Por otro lado, los dispositivos de un solo electrón son ejemplos de circuitos de bajo consumo energético. En este trabajo, se aborda la fabricación de un SET basado en un nanohilo vertical y su co-integración con tecnología CMOS. El punto de partida es un nanopilar de Si/SiO/Si con nanopuntos de Si en la capa intermedia de SiO2, que actúan como puntos cuánticos del sistema. Los electrodos de puerta y drenador se sitúan alrededor del óxido intermedio y en contacto con la parte superior del pilar, respectivamente. La integridad del pilar y el contacto de sus electrodos se validan mediante caracterización estructural. Aunque la integración SET en producción a gran escala es todavía un reto, su combinación con tecnología CMOS se beneficia de la madurez tecnológica del procesamiento de circuitos integrados, superando al mismo tiempo los inconvenientes intrínsecos del SET como ruido de fondo o la inestabilidad del dispositivo. Este trabajo también presenta la fabricación monolítica y compatible con CMOS de un transistor planar convencional co-integrado con un SET vertical. La fabricación del proceso se adapta para cumplir las restricciones impuestas por el SET prefabricado, como presupuesto térmico reducido, capas de protección o dopaje modificado. Se demuestra la fabricación monolítica de SET vertical y transistores planares convencionales; se preserva la integridad del pilar y los transistores fabricados funcionan en condiciones óptimas para la compatibilidad SET.
This thesis presents the investigations performed towards the integration of Single Electron Transistor (SET) into Complementary Metal-Oxide-Semiconductor (CMOS) technologies. Two of the main drives in semiconductor industry are device miniaturization and power consumption reduction. In the most advanced nodes, three-dimensional architectures have gained significant importance to increase the integration density, being vertically arranged devices the most suitable candidates for the ultimate generations. On the other hand, single electron devices are examples of ultra-low power consumption circuits. In this work, the fabrication of a SET based on a vertical nanowire and its co-integration with CMOS technology is addressed. The starting point is a Si/SiO2/Si nanopillar with Si nanodots in the intermediate SiO2 layer, acting as quantum dot of the system. The subsequent gate and drain electrodes are placed all-around the embedded oxide and on contact with the pillar cap, respectively. Pillar integrity and its electrodes contacting are validated by structural characterization. While SET integration in large-scale production is still challenging, its combination with CMOS technology benefits from the technological maturity of integrated circuits processing, overtaking SET intrinsic drawbacks as background noise or device instability. This work also reports the CMOS compatible and monolithic fabrication of a conventional planar transistor co-integrated with a vertical SET. The process fabrication is adapted to fulfil the restrictions imposed by the pre-fabricated SET, such as reduced thermal budget, protective layers and modified doping. The monolithic fabrication of vertical SET and planar transistors is demonstrated; the pillar integrity is preserved, and the fabricated transistors operate at optimum conditions for SET compatibility.
Universitat Autònoma de Barcelona. Programa de Doctorat en Enginyeria Electrònica i de Telecomunicació
Charbonneau, Micaël. "Etude et développement de points mémoires résistifs polymères pour les architectures Cross-Bar". Thesis, Grenoble, 2012. http://www.theses.fr/2012GRENT116/document.
Testo completoOver the past decade, non-volatile Flash storage technologies have played a major role in the development of mobile electronics and multimedia (MP3, Smartphone, USB, ultraportable computers ...). To further enhance performances, increase the capacity and reduce manufacturing costs, new technological solutions are now studied to provide complementary solutions or replace Flash technology. Cited by ITRS, the polymer resistive memories present very promising characteristics: low cost processing and ability for integration at high densities above CMOS interconnections or on flexible substrate. This PhD specifically focused on the development and study of composite material made of Poly-Methyl-Methacrylate (PMMA) polymer resist doped with C60 fullerene molecules. Studies were carried out on three different axes in parallel: Composite materials development & characterization, integration of the organic material in specific test structure and advanced devices and finally detailed electrical characterization of memory cells and performances analysis
Liddiard, C. L. "Charge integration and multigrid techniques in semiconductor device simulation". Thesis, Swansea University, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.637908.
Testo completoJain, Ishita. "Modeling and simulation of self-heating effects in sub-14NM CMOS devices". Thesis, IIT Delhi, 2019. http://eprint.iitd.ac.in:80//handle/2074/8137.
Testo completoSäckinger, Eduard. "Theory and monolithic CMOS integration of a differential difference amplifier /". Zürich, 1989. http://e-collection.ethbib.ethz.ch/show?type=diss&nr=8854.
Testo completoLeuschner, Stephan [Verfasser]. "CMOS Power Amplifiers for Single-Chip Radio Integration / Stephan Leuschner". München : Verlag Dr. Hut, 2018. http://d-nb.info/1162767766/34.
Testo completoKopalle, Deepika Niu Guofu. "RF linearity analysis in nano scale CMOS using harmonic balance device simulations". Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Fall/Thesis/KOPALLE_DEEPIKA_43.pdf.
Testo completoRakheja, Shaloo. "Interconnects for post-CMOS devices: physical limits and device and circuit implications". Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45866.
Testo completoOdanaka, Shinji. "A STUDY OF NUMERICAL PROCESS AND DEVICE MODELING CAD FOR SUBMICROMETER CMOS". Kyoto University, 1990. http://hdl.handle.net/2433/86214.
Testo completoWang, Haihong. "Advanced transport models development for deep submicron low power CMOS device design /". Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
Testo completoHUSSAIN, IZHAR. "TAMTAMS: A web based performance estimation tool from Device to System level for advanced CMOS processes to beyond CMOS technologies". Doctoral thesis, Politecnico di Torino, 2018. http://hdl.handle.net/11583/2710840.
Testo completoTibavinsky, Ivan Andres. "A microfabricated rapid desalting device for integration with electrospraying tip". Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/52226.
Testo completoFARAONE, GABRIELE. "Two-Dimensional Phosphorus: From the Synthesis Towards the Device Integration". Doctoral thesis, Università degli Studi di Milano-Bicocca, 2021. http://hdl.handle.net/10281/304380.
Testo completoPhosphorus and silicon two-dimensional (2D) allotropes have been the forerunners among the post-graphene monoelemental 2D materials. The scientific and technological advantages of these materials require the development of processing methods to guarantee their effective integration in new devices for nanoelectronics. In the present thesis work, some of the unresolved bottlenecks along the device integration path of 2D elemental phosphorus allotropes have been examined considering specifically the case of the α-P (single-layer black phosphorus or phosphorene) and β-P (blue phosphorene) 2D polymorphs. The integration of the 2D α-P phase in devices has been the subject of extensive investigations and nowadays relies on an almost consolidated path that has led to applications spanning a wide range of fields. One of the few remaining obstacles on this path is the lack of a scalable method to produce 2D α-P layers on large areas and with accurate control of the thickness. In particular, such control is difficult to achieve in the exfoliation of layered black phosphorus (BP) crystals. In this respect, micro-Raman spectroscopy has been used both as a metrological tool to determine the thickness of the exfoliated flakes and as method to achieve their controllable thickness reduction employing the laser thinning technique. However, thickness determination methods based on the calibration of the intensity of the Raman bands have been poorly investigated in the case of multilayer BP flakes due to difficulties caused by optical interferences and anisotropy effects. In this thesis work, we have proposed a novel Raman spectroscopy approach that, carefully accounting for these effects, allowed the quick discrimination of the thickness of exfoliated BP flakes between 5 nm and 100 nm. Moreover, in order to achieve a better control of the laser thinning process down to the ultimate 2D limit, we have also investigated the effects of the substrate on the laser heating and ablation of multilayer BP flakes. Raman thermometry experiments and numerical calculations of the heat diffusion problem have elucidated that optical, thermal, and mechanical effects caused by the substrate may act differently on the laser heating and ablation of the flakes depending on their thickness. An effective device integration route for the 2D β-P phase, instead, is still missing due to more stringent requirements in its synthesis, based on epitaxial techniques, and to the instability issue outside the UHV growth environment. These obstacles are commonly shared with other members of the family of 2D epitaxial Xenes and, in this work, have been investigated considering the case of β-P epitaxially grown on Au(111)/mica substrates. The details of its atomic structure and the chemical reactivity to ex-situ and in-situ oxygen exposure have been analyzed with the aid of Scanning Tunneling Microscopy (STM) and X-Ray Photoelectron Spectroscopy (XPS). The air-instability issues have been tackled by developing a suitable encapsulation strategy based on the in-situ growth of an Al2O3 capping layer that, in turn, allowed the handling of epitaxial phosphorus along the preliminary steps of a device integration process. In this respect, two novel approaches for the transfer of the epitaxial membrane from the growth substrate towards target substrates have been surveyed. Both the transfer methods can be suitably generalized to the whole class of 2D epitaxial Xenes grown on metal/mica paving the way for the establishment of methodological standards for their manipulation. In particular, the universality of such approaches has been exploited for the successful fabrication of back-gated FET and MIM devices on Al2O3/multilayer silicene/Ag(111) and Al2O3/epitaxial phosphorus/Au(111) mica-delaminated membranes, respectively. The epitaxial phosphorus MIM devices may open intriguing perspectives in the study of the non-volatile resistive switching in monoelemental epitaxial 2D materials.
Demirci, Kemal Safak. "Chemical microsystem based on integration of resonant microsensor and CMOS ASIC". Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/41182.
Testo completoCalayir, Enes. "Heterogeneous Integration of AlN MEMS Contour-Mode Resonators and CMOS Circuits". Research Showcase @ CMU, 2017. http://repository.cmu.edu/dissertations/1084.
Testo completoDavey, William Mark. "High-k dielectric stacks for integration into an advanced CMOS process". Thesis, University of Liverpool, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.526811.
Testo completoMartiny, Ingo [Verfasser]. "Integration und Optimierung optoelektronischer Sensoren in Standard-CMOS-Prozessen / Ingo Martiny". Düsseldorf : VDI-Verl, 1999. http://d-nb.info/975788728/34.
Testo completoLei, Yi-Shu Vivian 1979. "Post assembly process development for Monolithic OptoPill integration on silicon CMOS". Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/28548.
Testo completoIncludes bibliographical references (leaves 108-110).
Monolithic OptoPill integration by means of recess mounting is a heterogeneous technique employed to integrate III-V photonic devices on silicon CMOS circuits. The goal is to create an effective fabrication process that enables the volume production of high performance optoelectronic integrated circuits (OEICs). This thesis focuses on the development of post-assembly processes and technologies, in which InGaAs/InP P-i-N photodiodes were integrated as long wavelength photodetectors with an optical clock receiver circuit. Fabrication procedures, challenges experienced, and results accomplished are presented for each process step including the formation of alloyed and non-alloyed ohmic contacts on n-type and p-type InGaAs contact layers, active area definition by dry-etching InGaAs/InP with ECR-enhanced RIE, BCB passivation and planarization, via opening by dry-etching BCB with RIE, and top contact metallization. In conjunction, an InP-based test heterostructure was fabricated into discrete photodiodes. Decoupling the fabrication and benchmarking of III-V photonic device from the Si-CMOS electronic circuit allowed for the independent electrical and optical characterization of the photodetectors. Measurements and analysis of the P-i-N photodiodes will assist the forthcoming analysis of the final OEIC. Preliminary results and discussions of the calibration sample are presented in this thesis.
by Yi-Shu Vivian Lei.
S.M.
Orcutt, Jason S. (Jason Scott). "Monolithic electronic-photonic integration in state-of-the-art CMOS processes". Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/71279.
Testo completoThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student submitted PDF version of thesis.
Includes bibliographical references (p. 388-407).
As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. Photonic devices promise to break this bottleneck with superior bandwidth-density and energy-efficiency. Initial work by many research groups to adapt photonic device designs to a silicon-based material platform demonstrated suitable independent performance for such links. However, electronic-photonic integration attempts to date have been limited by the high cost and complexity associated with modifying CMOS platforms suitable for modern high-performance computing applications. In this work, we instead utilize existing state-of-the-art electronic CMOS processes to fabricate integrated photonics by: modifying designs to match the existing process; preparing a design-rule compliant layout within industry-standard CAD tools; and locally-removing the handle silicon substrate in the photonic region through post-processing. This effort has resulted in the fabrication of seven test chips from two major foundries in 28, 45, 65 and 90 nm CMOS processes. Of these efforts, a single die fabricated through a widely available 45nm SOI-CMOS mask-share foundry with integrated waveguides with 3.7 dB/cm propagation loss alongside unmodified electronics with less than 5 ps inverter stage delay serves as a proof-of-concept for this approach. Demonstrated photonic devices include high-extinction carrier-injection modulators, 8-channel wavelength division multiplexing filter banks and low-efficiency silicon germanium photodetectors. Simultaneous electronic-photonic functionality is verified by recording a 600 Mb/s eye diagram from a resonant modulator driven by integrated digital circuits. Initial work towards photonic device integration within the peripheral CMOS flow of a memory process that has resulted in polysilicon waveguide propagation losses of 6.4 dB/cm will also be presented.
by Jason S. Orcutt.
Ph.D.
Webster, Eric Alexander Garner. "Single-Photon Avalanche Diode theory, simulation, and high performance CMOS integration". Thesis, University of Edinburgh, 2013. http://hdl.handle.net/1842/17987.
Testo completoSudirgo, Stephen. "The integration of Si-based resonant interband tunnel diodes with CMOS /". Online version of thesis, 2003. http://hdl.handle.net/1850/5192.
Testo completoLeene, Lieuwe. "Brain machine interfaces : low power techniques for CMOS based system integration". Thesis, Imperial College London, 2016. http://hdl.handle.net/10044/1/47980.
Testo completoBerthelon, Rémy. "Strain integration and performance optimization in sub-20nm FDSOI CMOS technology". Thesis, Toulouse 3, 2018. http://www.theses.fr/2018TOU30066/document.
Testo completoThe Ultra-Thin Body and Buried oxide Fully Depleted Silicon On Insulator (UTBB FDSOI) CMOS technology has been demonstrated to be highly efficient for low power and low leakage applications such as mobile, internet of things or wearable. This is mainly due to the excellent electrostatics in the transistor and the successful integration of strained channel as a carrier mobility booster. This work explores scaling solutions of FDSOI for sub-20nm nodes, including innovative strain engineering, relying on material, device, process integration and circuit design layout studies. Thanks to mechanical simulations, physical characterizations and experimental integration of strained channels (sSOI, SiGe) and local stressors (nitride, oxide creeping, SiGe source/drain) into FDSOI CMOS transistors, we provide guidelines for technology and physical circuit design. In this PhD, we have in-depth studied the carrier transport in short devices, leading us to propose an original method to extract simultaneously the carrier mobility and the access resistance and to clearly evidence and extract the strain sensitivity of the access resistance, not only in FDSOI but also in strained nanowire transistors. Most of all, we evidence and model the patterning-induced SiGe strain relaxation, which is responsible for electrical Local Layout Effects (LLE) in advanced FDSOI transistors. Taking into account these geometrical effects observed at the nano-scale, we propose design and technology solutions to enhance Static Random Access Memory (SRAM) and digital standard cells performance and especially an original dual active isolation integration. Such a solution is not only stress-friendly but can also extend the powerful back-bias capability, which is a key differentiating feature of FDSOI. Eventually the 3D monolithic integration can also leverage planar Fully-Depleted devices by enabling dynamic back-bias owing to a Design/Technology Co-Optimization
Jamil, Mustafa. "Germanium and epitaxial Ge:C devices for CMOS extension and beyond". Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-08-3783.
Testo completotext
Hung, Shih-Han, e 洪士涵. "A Study of MEMS Devices Integration for RF CMOS Power Amplifier". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/ht8j8d.
Testo completo國立臺北科技大學
機電整合研究所
96
Nowadays, communication system development toward MMIC and SOC become more and more massive. Due to the reason, using the standard CMOS process for RF communication system design has been regarded as a valuable research. Since CMOS process develops rapidly and its feature sizes reduces gradually, it make the operation speed faster、the power consumption reduced and the operation frequency increased. The increased operation frequency is the most important for RF communication system designs. Therefore, CMOS elements can be applied to RF communication systems widely. The study demonstrates that the Class AB power amplifier based on RF CMOS integrates with MEMS Devices. Because the system is to extend the battery life of sensing points, the power amplifier is necessary to have the characteristic of high efficiency. The power amplifier fabrication is based on TSMC 0.18μm 1P6M CMOS process. Its operation voltage is 1.8 V. The experimental results show: when the frequency is 2.4GHz and the input power is -10dBm, the output power is 14dBm and its PAE is 30%;When the frequency is 1.8GHz and the input power is -10dBm, the output power is 14dBm and its PAE is 24%. We desire to design the high integrated and low power consumption power amplifier. By the circuit simulations, we design the On-chip power amplifier. Avoiding using Lump elements is for the reduction of the area consumption. Moreover, we use 1.8 V low voltage. PAE is up to more 30%.