Letteratura scientifica selezionata sul tema "Application specific instruction-set processor (ASIP)"
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Articoli di riviste sul tema "Application specific instruction-set processor (ASIP)"
Imai, Masaharu, Yoshinori Takeuchi, Keishi Sakanushi e Nagisa Ishiura. "Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP)". IPSJ Transactions on System LSI Design Methodology 3 (2010): 161–78. http://dx.doi.org/10.2197/ipsjtsldm.3.161.
Testo completoSharma, Poonam, Ashwani Kumar Dubey e Ayush Goyal. "Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier". Recent Patents on Engineering 13, n. 2 (27 maggio 2019): 174–80. http://dx.doi.org/10.2174/1872212112666180810150357.
Testo completoXin, Yao, Will X. Y. Li, Zhaorui Zhang, Ray C. C. Cheung, Dong Song e Theodore W. Berger. "An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics". IEEE/ACM Transactions on Computational Biology and Bioinformatics 12, n. 5 (1 settembre 2015): 1034–47. http://dx.doi.org/10.1109/tcbb.2015.2440248.
Testo completoSafaei Mehrabani, Yavar. "Synthesis of an Application Specific Instruction Set Processor (ASIP) for RIPEMD-160 Hash Algorithm". International Journal of Electronics Letters 7, n. 2 (25 maggio 2018): 154–65. http://dx.doi.org/10.1080/21681724.2018.1477182.
Testo completoZhang, Diandian, Li Lu, Jeronimo Castrillon, Torsten Kempf, Gerd Ascheid, Rainer Leupers e Bart Vanthournout. "Efficient Implementation of Application-Aware Spinlock Control in MPSoCs". International Journal of Embedded and Real-Time Communication Systems 4, n. 1 (gennaio 2013): 64–84. http://dx.doi.org/10.4018/jertcs.2013010104.
Testo completoIwaizumi, Hiroki, Shingo Yoshizawa e Yoshikazu Miyanaga. "A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems". VLSI Design 2013 (18 marzo 2013): 1–10. http://dx.doi.org/10.1155/2013/625019.
Testo completoQiao, Wan, e Dake Liu. "A scalable ASIP for BP Polar decoding with multiple code lengths". MATEC Web of Conferences 232 (2018): 01046. http://dx.doi.org/10.1051/matecconf/201823201046.
Testo completoWong, Tingh Wee, Bryan Ng e Chee Onn Wong. "Encoding Custom Instruction Generation as Satisfiability Problem". Advanced Materials Research 403-408 (novembre 2011): 502–10. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.502.
Testo completoFischer, Dirk, Jürgen Teich, Ralph Weper e Michael Thies. "BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs". Journal of Circuits, Systems and Computers 12, n. 03 (giugno 2003): 353–75. http://dx.doi.org/10.1142/s0218126603000799.
Testo completoAhmed, O., S. Areibi e G. Grewal. "Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm". International Journal of Reconfigurable Computing 2013 (2013): 1–33. http://dx.doi.org/10.1155/2013/681894.
Testo completoTesi sul tema "Application specific instruction-set processor (ASIP)"
Radhakrishnan, Swarnalatha Computer Science & Engineering Faculty of Engineering UNSW. "Heterogeneous multi-pipeline application specific instruction-set processor design and implementation". Awarded by:University of New South Wales. Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/29161.
Testo completoPackiaraj, Vivek. "Study, Design and Implementation of an Application Specific Instruction Set Processor for a Specific DSP Task". Thesis, Linköping University, Electronics System, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-52314.
Testo completoThere is a lot of literature already available describing well-structured approach for embeddeddesign and implementation of Application Specific Integrated Processor (ASIP) micro processorcore.
This concept features hardware structured approach for implementation of processor core fromminimal instruction set, encoding standards, hardware mapping, and micro architecture design,coding conventions, RTL,verification and burning into a FPGA. The goal is to design an ASIPprocessor core (Micro architecture design and RTL) which can perform DSP task, e.g., FIR. Thereport is a well structured approach of design and implementation of an ASIP DSP processor forDSP applications like FIR. This report contains design flow starting from Instruction set design,micro architecture design and RTL implementation of the core. Details of the power simulationsof FPGA are also listed and analyzed.
Cheung, Newton Computer Science & Engineering Faculty of Engineering UNSW. "Design automation methodologies for extensible processor platform". Awarded by:University of New South Wales. School of Computer Science and Engineering, 2005. http://handle.unsw.edu.au/1959.4/26118.
Testo completoMikó, Albert. "Akcelerace aplikací pomocí specializovaných instrukcí". Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2016. http://www.nusl.cz/ntk/nusl-255444.
Testo completoŠulek, Jakub. "Verifikace ASIP založena na formálních tvrzeních". Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2015. http://www.nusl.cz/ntk/nusl-264941.
Testo completoVogt, Timo. "A reconfigurable application-specific instruction-set processor for trellis-based channel decoding /". Kaiserslautern : Techn. Univ. Kaiserslautern, 2008. http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&doc_number=016537958&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA.
Testo completoShee, Seng Lin Computer Science & Engineering Faculty of Engineering UNSW. "ADAPT : architectural and design exploration for application specific instruction-set processor technologies". Awarded by:University of New South Wales, 2007. http://handle.unsw.edu.au/1959.4/35404.
Testo completoYassin, Yahya H. "ULTRA LOW POWER APPLICATION SPECIFIC INSTRUCTION-SET PROCESSOR DESIGN : for a cardiac beat detector algorithm". Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2009. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-9914.
Testo completoHigh efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption. By optimizing the processor for the application, or a set of applications, one could improve the computing power by introducing special purpose hardware units. The execution cycle count of the application would in this case be reduced significantly, and the resulting processor would consume less power. In this thesis, some research is done in how to optimize a software and hardware development for ultra low power consumption. A cardiac beat detector algorithm is implemented in ANSI C, and optimized for low power consumption, by using several software power optimization techniques. The resulting application is mapped on a basic processor architecture provided by Target Compiler Technologies. This processor is optimized further for ultra low power consumption by applying application specific hardware, and by using several hardware power optimization techniques. A general processor and the optimized processor has been mapped on a chip, using a 90 nm low power TSMC process. Information about power dissipation is extracted through netlist simulation, and the results of both processors have been compared. The optimized processor consume 55% less average power, and the duty cycle of the processor, i.e., the time in which the processor executes its task with respect to the time budget available, has been reduced from 14% to 2.8%. The reduction in the total execution cycle count is 81%. The possibilities of applying power gating, or voltage and frequency scaling are discussed, and it is concluded that further reduction in power consumption is possible by applying these power optimization techniques. For a given case, the average leakage power dissipation is estimated to be reduced by 97.2%.
Husár, Adam. "Implementace obecného assembleru". Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2007. http://www.nusl.cz/ntk/nusl-412779.
Testo completoBytyn, Andreas [Verfasser], Gerd [Akademischer Betreuer] Ascheid e Rainer [Akademischer Betreuer] Leupers. "Efficiency and scalability exploration of an application-specific instruction-set processor for deep convolutional neural networks / Andreas Bytyn ; Gerd Ascheid, Rainer Leupers". Aachen : Universitätsbibliothek der RWTH Aachen, 2020. http://d-nb.info/1230325506/34.
Testo completoLibri sul tema "Application specific instruction-set processor (ASIP)"
Embedded DSP processor design: Application specific instruction set processors. Amsterdam: Morgan Kaufmann, 2008.
Cerca il testo completoRainer, Leupers, e SpringerLink (Online service), a cura di. Application Analysis Tools for ASIP Design: Application Profiling and Instruction-set Customization. New York, NY: Springer Science+Business Media, LLC, 2011.
Cerca il testo completoNelson, Victor P. 74AS-EVM-16: A microprogramming approach to application-specific instruction set processor design : register-transfer level design : laboratory manual no. 1. Dallas, TX: Texas Instruments, 1987.
Cerca il testo completoNelson, Victor P. 74AS-EVM-16: A microprogramming approach to application-specific instruction set processor design : register-transfer level design : laboratory manual no. 1. Dallas, TX: Texas Instruments, 1987.
Cerca il testo completoLeupers, Rainer, e Kingshuk Karuri. Application Analysis Tools for ASIP Design: Application Profiling and Instruction-set Customization. Springer, 2014.
Cerca il testo completoCapitoli di libri sul tema "Application specific instruction-set processor (ASIP)"
Choi, Seung-Hyun, Neungsoo Park, Yong Ho Song e Seong-Won Lee. "ASiPEC: An Application Specific Instruction-Set Processor for High Performance Entropy Coding". In Ubiquitous Computing Application and Wireless Sensor, 67–75. Dordrecht: Springer Netherlands, 2015. http://dx.doi.org/10.1007/978-94-017-9618-7_7.
Testo completoWenger, Erich. "A Lightweight ATmega-Based Application-Specific Instruction-Set Processor for Elliptic Curve Cryptography". In Lecture Notes in Computer Science, 1–15. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-40392-7_1.
Testo completoKaruri, Kingshuk, Rainer Leupers, Gerd Ascheid e Heinrich Meyr. "A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs)". In Lecture Notes in Computer Science, 204–14. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03138-0_22.
Testo completoZhang, Diandian, Jeronimo Castrillon, Stefan Schürmans, Gerd Ascheid, Rainer Leupers e Bart Vanthournout. "System-Level Analysis of MPSoCs with a Hardware Scheduler". In Advances in Systems Analysis, Software Engineering, and High Performance Computing, 335–67. IGI Global, 2014. http://dx.doi.org/10.4018/978-1-4666-6034-2.ch014.
Testo completoPuusaari, Kimmo, Timo Yli-Pietilä e Kim Rounioja. "Application Specific Instruction Set Processor for UMTS-FDD Cell Search". In Customizable Embedded Processors, 339–60. Elsevier, 2007. http://dx.doi.org/10.1016/b978-012369526-0/50015-2.
Testo completoAtti di convegni sul tema "Application specific instruction-set processor (ASIP)"
Liu, Dake. "ASIP (Application Specific Instruction-set Processors) design". In 2009 IEEE 8th International Conference on ASIC (ASICON). IEEE, 2009. http://dx.doi.org/10.1109/asicon.2009.5351271.
Testo completoMazurek, Przemyslaw. "BOSON - Application-Specific Instruction Set Processor (ASIP) for Educational Purposes". In 2020 16th International Conference on Control, Automation, Robotics and Vision (ICARCV). IEEE, 2020. http://dx.doi.org/10.1109/icarcv50220.2020.9305396.
Testo completoMazurek, Przemyslaw. "BOSON - Application-Specific Instruction Set Processor (ASIP) for Educational Purposes". In 2020 16th International Conference on Control, Automation, Robotics and Vision (ICARCV). IEEE, 2020. http://dx.doi.org/10.1109/icarcv50220.2020.9305396.
Testo completoHuang, Wei-pei, Ray C. C. Cheung e Hong Yan. "An Efficient Application Specific Instruction Set Processor (ASIP) for Tensor Computation". In 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2019. http://dx.doi.org/10.1109/asap.2019.00-36.
Testo completoHu, Jingwei, Wangchen Dai, Liu Yao e Ray C. C. Cheung. "An application specific instruction set processor (ASIP) for the niederreiter cryptosystem". In 2018 6th International Symposium on Digital Forensic and Security (ISDFS). IEEE, 2018. http://dx.doi.org/10.1109/isdfs.2018.8355364.
Testo completoHussain, Waqar, Xiaolin Chen, Gerd Ascheid e Jari Nurmi. "A Reconfigurable Application-specific Instruction-set Processor for Fast Fourier Transform processing". In 2013 IEEE 24th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2013. http://dx.doi.org/10.1109/asap.2013.6567599.
Testo completoFathy, Amr, Tsuyoshi Isshiki, Dongju Li e Hiroaki Kunieda. "Custom instruction search for application specific instruction-set processor using guided simulated annealing". In 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2014. http://dx.doi.org/10.1109/apccas.2014.7032796.
Testo completoBertoni, Guido, Luca Breveglieri, Farina Roberto e Francesco Regazzoni. "Speeding Up AES By Extending a 32 bit Processor Instruction Set". In IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06). IEEE, 2006. http://dx.doi.org/10.1109/asap.2006.62.
Testo completoEissa, Ahmed S., Mahmoud A. Elmohr, Mostafa A. Saleh, Khaled E. Ahmed e Mohammed M. Farag. "SHA-3 Instruction Set Extension for A 32-bit RISC processor architecture". In 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2016. http://dx.doi.org/10.1109/asap.2016.7760804.
Testo completoJun-Young Lee, Jae-Jin Lee, MooKyoung Jeong, NakWoong Eum e SeongMo Park. "A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder". In 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008. IEEE, 2008. http://dx.doi.org/10.1109/iscas.2008.4542204.
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