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Letteratura scientifica selezionata sul tema "Active Deep Trench Isolation"

Autore: Grafiati

Pubblicato: 25 gennaio 2025

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Articoli di riviste sul tema "Active Deep Trench Isolation"

David Theodore, N., Barbara Vasquez e Peter Fejes. "Microstructural characterization of implanted LOCOS + trench-isolated structures". Proceedings, annual meeting, Electron Microscopy Society of America 49 (agosto 1991): 888–89. http://dx.doi.org/10.1017/s0424820100088750.

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As device dimensions decrease and circuit densities increase, conventional LOCOS (Local-Oxidation of Silicon) isolation presents a limitation due to lateral encroachment of the isolation-oxide. Variations in LOCOS, including poly-buffered LOCOS have been of interest as means to limit lateral encroachment of the field-oxide into the active device-region. Deep-trench isolation provides a means to support device scaling and in this work is integrated with poly-buffered LOCOS to create self-aligned shallow fieldoxide elements with minimal encroachment into active regions. Use of these technologies however requires an understanding of the behavior of the materials and structures being used and their interactions under different processing conditions. The effect of fabrication-related stresses in the structures is of interest because extended-defects, if formed, could electrically degrade devices.

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Park, Byung Jun, Jongwan Jung, Chang-Rok Moon, Sung Ho Hwang, Yong Woo Lee, Dae Woong Kim, Kee Hyun Paik, Jong Ryeol Yoo, Duck Hyung Lee e Kinam Kim. "Deep Trench Isolation for Crosstalk Suppression in Active Pixel Sensors with 1.7 µm Pixel Pitch". Japanese Journal of Applied Physics 46, n. 4B (24 aprile 2007): 2454–57. http://dx.doi.org/10.1143/jjap.46.2454.

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Schonenberg, K., Siu-Wai Chan, D. Harame, M. Gilbert, C. Stanis e L. Gignac. "The stability of Si1−xGex strained layers on small-area trench-isolated silicon". Journal of Materials Research 12, n. 2 (febbraio 1997): 364–70. http://dx.doi.org/10.1557/jmr.1997.0052.

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The combined effects of isolation stress, active area size, and SiGe misfit strain on dislocation generation in an advanced SiGe heterojunction bipolar transistor (HBT) process were studied. Eight-inch wafers were patterned with polysilicon-filled deep, and oxide-filled shallow trench isolation similar to that used in IBM's analog SiGe HBT technology. Half of the wafers were subjected to an additional stress-producing oxidation prior to SiGe growth. Si1−xGex films containing 0, 5.5, 9, and 13 at.% Ge were grown epitaxially by ultrahigh vacuum chemical vapor deposition (UHV CVD). The films were of constant thickness with an intrinsic Si cap. Some samples received an additional relaxation anneal following deposition. After the growth and anneal cycles, the dislocation density was determined by transmission electron microscopy (TEM). On nonstressed samples, no dislocations were observed in the device areas, even at Ge concentrations which are not stable to misfit dislocation generation in blanket form. This small area effect has been observed on patterned substrates that do not have functional device isolation. On the stressed-isolation wafers, the compressive stress from the oxidation of the trench sidewalls was found to intensify stress in the SiGe films, and to lower the critical strain at which misfit dislocations appeared. In large active areas on these wafers, two distinct dislocation regions were observed. Defects at the edge resembled those caused by isolation stress, while the defects in the center were more typical of the misfit dislocations associated with lattice-mismatch epitaxial films. It is clear that isolation stress must be minimized when fabricating integrated circuits using SiGe epitaxial films. It is also evident that SiGe films grown on nonstressed isolation exhibit the same increase in critical thickness with decreasing lateral dimension that has been observed on much simpler patterned substrates.

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Ajel, Hasan A., Haider S. Al-Jubair e Jaafar K. Ali. "An experimental study on vibration isolation by open and in-filled trenches". Open Engineering 12, n. 1 (1 gennaio 2022): 555–69. http://dx.doi.org/10.1515/eng-2022-0011.

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Abstract The mitigation of vibrations due to a harmonic load induced by a mechanical oscillator is studied experimentally. The vertical components of soil particle velocities are measured (via geophones) at different locations apart from the source, where various frequencies (30–70 Hz) are generated. For normal conditions where no mitigation means are used, it is found that the measured peak particle velocities are proportional to the excitation frequencies. The mitigation effect of constructing an active (near source) open (0.4 m wide × 3 m long × 2 m deep) trench barrier is also studied. The measurements revealed velocity increase at the points in front of the trench due to the reflected waves. This increase is proportional to the vibration frequency. Although the presence of the barrier greatly reduced the peak particle velocities beyond it, it is found that the efficiency of screening is more pronounced at high vibration frequencies. Increased and fluctuated trends of the amplitude reduction ratio are reported away from the barrier. It is realized that passive (near target) screening is less effective for all frequencies except at 30 Hz. Active and passive trenches, filled with native soil–rubber mixture at various ratios (20–40% rubber), are also considered. The rubber material is in a form of tire chips purchased from the Unit of Recycling Scrap Tires in Al-Diwaniyah Tires Factory. Although the in-filled trenches are less effective in screening the vibrations, similar trends and behavior to the open trenches are noted. It is found that the mitigation efficacy is increased with the rubber content.

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Kang, Harin, e Yunkyung Kim. "High Sensitive Pixels using the Deep Trench Isolation". Journal of Korean Institute of Information Technology 19, n. 9 (30 settembre 2021): 49–56. http://dx.doi.org/10.14801/jkiit.2021.19.9.49.

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Tsang, Y. L., e J. M. Aitken. "Junction breakdown instabilities in deep trench isolation structures". IEEE Transactions on Electron Devices 38, n. 9 (1991): 2134–38. http://dx.doi.org/10.1109/16.83741.

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Lee, S., e R. Bashir. "Modeling and characterization of deep trench isolation structures". Microelectronics Journal 32, n. 4 (aprile 2001): 295–300. http://dx.doi.org/10.1016/s0026-2692(00)00148-8.

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Fejes, Peter, N. David Theodore e Han-Bin Liang. "Geometry-dependence of defects in PBLT serpentines". Proceedings, annual meeting, Electron Microscopy Society of America 50, n. 2 (agosto 1992): 1410–11. http://dx.doi.org/10.1017/s0424820100131681.

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Poly-buffered LOCOS + trench-isolation is a technique being explored for device-isolation on semiconductor substrates. The method creates self-aligned shallow field-oxide elements with minimal encroachment into active regions. In an earlier study/dislocations were observed in PBLT structures, associated with a combination of high-dose [∼1E15 cm−2] phosphorus implants and PBLT isolation. The present study investigates the effect of implant- and isolation-geometries on the formation of extended-defects in PBLT structures. The effect of fabrication-related stresses in the structures is of interest because extended-defects, once formed, can electrically degrade devices.PBLT structures were fabricated using varied implant- and isolation- geometries. Selected regions of the structures were exposed to 1E15 cm−2 phosphorus implants. Transmission electron microscopy was then used to characterize these regions. Some of the structures investigated were (i) trench with no adjacent implant, (ii) trench with an adjacent trench, but no implant, (iii) trench with a 1E15 cm−2 phosphorus implant placed ∼4 μm from the trench, (iv) trench with a 1E15 cm−2 phosphorus implant placed ∼2 μm from the trench, (v) doubly-kinked trench with a 1E15cm−2 phosphorus implant placed between the kinks.

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Liu, Jinglei, Chuanqing Yu, Kai Li, Jie Liu e Mengyao Wen. "Test on the Influence of Geometric Parameters of an Annular Trench on the Vibration Isolation Area". Shock and Vibration 2020 (19 marzo 2020): 1–19. http://dx.doi.org/10.1155/2020/7801085.

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To study the influence of annular trenches on a vibration isolation area, the depth, width, vibration source distance, and central angle of the trench are analysed as research variables, and a contour diagram of the amplitude reduction ratio is drawn based on an outdoor test of the trench. Taking an area with an amplitude reduction ratio less than 0.40 as the evaluation index of the effective vibration isolation area, the effects of the above geometric parameters on the vibration isolation area are analysed. Limited to the test conditions of this paper, the results show that the depth, vibration source distance, and deep width ratio are the important factors affecting the effective vibration isolation area; with the increase of the above parameters, the effective vibration isolation area increases significantly, but the area increase rate decreases gradually. The width has a relatively little effect on the effective vibration isolation area. When the ratio of depth to width is from 7.05 to 9.15, and the width reaches 0.23 times the Rayleigh wavelength, the annular trench can have a good effective vibration isolation area. When the central angle of the trench is less than 90°, a discontinuous effective vibration isolation area will form in the vibration isolation region. The selection of the central angle of the trench is related to the frequency. With the same trench size, the effective vibration isolation area decreases as frequency decreases. In addition, the effect of distance depth ratio on the effective vibration isolation area presents a fluctuation. When the ratio of distance to depth is from 1.21 to 2.05, a good effective vibration isolation area can be obtained and it is reasonable.

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Elattari, B., P. Coppens, G. Van den bosch, P. Moens e G. Groeseneken. "Breakdown and hot carrier injection in deep trench isolation structures". Solid-State Electronics 49, n. 8 (agosto 2005): 1370–75. http://dx.doi.org/10.1016/j.sse.2005.06.003.

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Più fonti

Tesi sul tema "Active Deep Trench Isolation"

Ahmed, Nayera. "MOS Capacitor Deep Trench Isolation (CDTI) for CMOS Image Sensors". Thesis, Lyon 1, 2015. http://www.theses.fr/2015LYO10048.

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The development of high-resolution image sensors with smaller pixel sizes is facing critical issues, such as optical and electrical crosstalk, dark current and dynamic range. As part of this thesis, we addressed this issue by proposing the integration of MOS capacitor deep trench isolation (CDTI). Our studies focus on the validation of the proposal with the aim of improving performances compared to the state of the art. First, we modeled interface states Si/SiO2 and the charge in the oxide. By TCAD simulations, using our model, we were able to evaluate the main characteristics of a pixel. We have validated this approach by comparison between simulations and measurements on a 1.4μm DTI pixel. Then, we developed manufacturing processes for integrating CDTI and defined the associated key parameters. With TCAD simulations of process type, we could achieve the desired performances while keeping a short development cycle and cost. Finally, we have designed, manufactured and tested a 1.4μm CDTI pixel ; we got a very low dark current: ~ 1 aA/pixel at 60°C, which is 6 times less than the DTI pixel, and doubled saturation charge up to 12000e-. Other performances are comparable between the two types of pixels. We have demonstrated the validity of the proposed CDTI solution CDTI

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Salih, Alj Antoine. "Effets des radiations et propriétés électriques d’un capteur CCD-sur-CMOS à tranchées profondes actives pour l’imagerie haute-performance". Electronic Thesis or Diss., Toulouse, ISAE, 2024. http://www.theses.fr/2024ESAE0048.

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Les dispositifs d'imagerie CMOS (Complementary Metal Oxide Semiconductor), trouvent de nombreuses applications en imagerie terrestre haute résolution et en imagerie scientifique (par exemple : Sentinel-2, MSL2020 et MMX). Les avancées impressionnantes réalisées ces cinq dernières années en technologie d'imagerie CMOS, tant au niveau des performances de photodétection que de la réduction du bruit, ouvrent aujourd'hui la voie à des applications de très haute performance, alors que les CCD (Charge Coupled Device) étaient jusqu'à présent les meilleurs candidats.Pour de telles applications, le développement de cette technologie doit se concentrer sur l'amélioration du rapport signal-à-bruit (SNR) afin d'atteindre une résolution spatiale optimale pour les images satellites d'observation terrestre (résolution sub-métrique). Le premier levier d'amélioration repose sur l'augmentation de la sensibilité du détecteur, avec comme objectif l'optimisation du transfert de charge inter-pixels et la réduction des courants d'obscurité parasites. Le second levier consiste à maximiser la capacité de collection de charge et à contrôler les effets de saturation. L'ensemble de ces paramètres doit être évalué en tenant compte des conditions de l'environnement spatial, en particulier les effets des radiations (ionisation et déplacement), qui peuvent fortement altérer les propriétés électriques des capteurs d'images.La technologie CMOS actuellement privilégiée pour les futurs projets d'imagerie terrestre haute résolution intègre un nœud technologique spécifique de tranchée profonde active. Cette technologie permet, lorsqu'elle est associée au potentiel de tranchée adapté, de contrôler les mouvements de charge dans le silicium. Ainsi, des registres à transfert de charge de type CCD-sur-CMOS utilisant cette technologie, ont été implémentés avec succès. L'analyse théorique et la caractérisation de certaines architectures de registres CCD à deux phases ont donné des résultats très prometteurs et ouvert de nouvelles perspectives.Les objectifs de cette thèse sont multiples : améliorer la compréhension de ce nouveau type de pixel à transfert de charge, et en particulier des tranchées profondes actives, à travers une analyse approfondie des phénomènes physiques en jeu et des effets des radiations (tant en termes de dose d'ionisation que de déplacement). Il s'agit également d'évaluer et de proposer des optimisations de conception adaptées à plusieurs modes de fonctionnement (Time Delay Integration, Electron Multiplication), permettant d'atteindre les performances visées en matière de SNR, tout en répondant aux exigences de tolérance aux radiations pour l'imagerie très haute résolution
CMOS imaging devices (Complementary Metal Oxide Semiconductor) have numerous applications in high-resolution terrestrial imaging and scientific imaging (e.g., Sentinel-2, MSL2020, and MMX). The remarkable advancements made in CMOS imaging technology over the past five years, both in terms of photodetection performance and noise reduction, have paved the way for very high-performance applications, where CCDs (Charge Coupled Devices) were previously considered the best candidates.For such applications, the development of this technology must focus on improving the signal-to-noise ratio (SNR) to achieve optimal spatial resolution in satellite images for terrestrial observation (sub-meter resolution). The first lever for improvement is increasing detector sensitivity, to optimize inter-pixel charge transfer and reduce parasitic dark currents. The second lever is maximizing charge collection capacity and controlling saturation effects. All these parameters must be evaluated considering the space environment, particularly the effects of radiation (ionization and displacement), which can significantly degrade the electrical properties of image sensors.The CMOS technology currently favored for future high-resolution terrestrial imaging projects integrates a specific feature of active deep trench isolation. When combined with the appropriate trench potential, this technology allows the control of charge movements within the silicon. As a result, CCD-on-CMOS charge transfer registers using this technology have been successfully implemented. Theoretical analysis and characterization of certain two-phase CCD register architectures have yielded very promising results and opened up new perspectives.The objectives of this thesis are multiple: to improve the understanding of this new type of charge transfer pixel, particularly the active deep trench isolation feature, through an in-depth analysis of the physical phenomena involved and the effects of radiation (both in terms of ionizing dose and displacement). Additionally, it aims to evaluate and propose design optimizations for various operating modes (Time Delay Integration, Electron Multiplication), to achieve the targeted SNR performance while meeting radiation tolerance requirements for high-resolution imaging

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Finkelstein, Hod. "Shallow-trench-isolation bounded single-photon avalanche diodes in commercial deep submicron CMOS technologies". Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2007. http://wwwlib.umi.com/cr/ucsd/fullcit?p3274523.

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Thesis (Ph. D.)--University of California, San Diego, 2007.
Title from first page of PDF file (viewed October 3, 2007). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 256-271).

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Forsberg, Markus. "Chemical Mechanical Polishing of Silicon and Silicon Dioxide in Front End Processing". Doctoral thesis, Uppsala : Acta Universitatis Upsaliensis : Univ.-bibl. [distributör], 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-4304.

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Gacim, Fadoua. "Modelling, characterisation and optimization of substrate losses in RF switch IC design for WLAN applications". Thesis, Normandie, 2017. http://www.theses.fr/2017NORMC268/document.

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Cette thèse est une étude sur la caractérisation, la modélisation et l’optimisation des effets substrat dans les circuits intégrés, dédies à des applications WLAN.L’objectif de ces travaux de recherche est de développer une nouvelle méthodologie d’extraction qui prenne en compte tous les parasites ; à savoir les modèles RLCK distribués, les effets électromagnétiques, ainsi que le couplage substrat.Les effets substrat ont été optimisés grâce au développement de nouvelles structures d’isolation utilisant des tranches profondes d’isolation (DTI).La prédictibilité des simulations circuits a été améliorée grace à l’introduction d’une nouvelle méthodologie d’extraction, basée sur une approche quasi-statique prenant en compte avec précision la description exacte et complète du procédé BiCMOS ainsi que les pertes dans le substrat, aussi bien diélectriques que résistives.La validité de cette méthodologie a été évaluée en comparant les résultats de simulation avec les mesures sur silicium. La bonne corrélation des résultats démontre la pertinence de cette nouvelle méthodologie. Cette méthode permet de plus, de réduire le « time to maket » grâce à l’optimisation des temps de simulations
This thesis is about characterization, modelling and optimization of substrate effects in integrated circuits, dedicated to WLAN applications.The objective of this thesis is to develop a new extraction methodology that takes into account all parasites; distributed RLCK models, electromagnetic effects, as well as substrate coupling.Substrate effects have been optimized through the development of a new insulation strategies using deep isolation isolation (DTIs).The circuit predictability has been improved thanks to the development of a new extraction methodology, based on a quasi-static approach taking into account the complete description of the BiCMOS process as well as the substrate loss, both capacitive and resistive effects.The validation of this methodology was evaluated by comparing simulation results with silicon measurements. The good correlation of the obtained results demonstrates the accuracy of this new methodology. This method also makes it possible to reduce the time to market thanks to the optimization of the simulation times

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Ait, Fqir Ali Fatima Zahra. "Développement et caractérisation de nouveaux procédés de passivation pour les capteurs d'images CMOS". Thesis, Lyon 1, 2013. http://www.theses.fr/2013LYO10186.

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La conception des futures générations de capteurs d'images CMOS, nécessite l'intégration de structures 3D telles que les tranchées profondes d'isolation, ou encore l'adoption de nouvelles architectures telles que les capteurs d'images à illumination face arrière. Cependant, l'intégration de telles architectures engendre l'apparition de nouvelles interfaces Si/SiO2, pouvant être la source d'un fort courant d'obscurité Idark, dégradant considérablement les performances électro-optiques du capteur. Ainsi, dans le but d'éliminer le Idark et d'augmenter l'efficacité de collecte et de confinement des photoporteurs au sein de la photodiode, la passivation de ces interfaces par l'introduction d'une jonction fortement dopée a été étudiée. D'une part, la passivation de la face arrière a été réalisée par implantation ionique activée par recuit laser pulsé. Grâce à un traitement très court et localisé, le recuit laser a démontré sa capacité à réaliser des jonctions minces et très abruptes. Une très bonne qualité cristalline ainsi que des taux d'activation avoisinant les 100% ont pu être atteint dans le mode fusion. Le mode sous-fusion quant à lui permet d'obtenir des résultats prometteurs en multipliant le nombre de tir laser. Les résultats électriques ont permis de distinguer les conditions optimales d'implantation et de recuit pour l'achèvement d'un faible niveau de Idark comparable à la référence en vigueur ainsi qu'une bonne sensibilité. Le deuxième axe d'étude s'est intéressé à la passivation des flancs des DTI par épitaxie sélective dopée in-situ. Des dépôts très uniformes de la cavité accompagnés d'une très bonne conformité de dopage le long des tranchées ont pu être réalisés. Les résultats sur lot électrique ont montré un très faible niveau de Idark supplantant la référence en vigueur
In order to maintain or enhance the electro-optical performances while decreasing the pixel size, advanced CMOS Image Sensors (CIS) requires the implementation of new architectures. For this purpose, deep trenches for pixel isolation (DTI) and backside illumination (BSI) have been introduced as ones of the most promising candidates. The major challenge of these architectures is the high dark current level (Idark) due to the generation/recombination centers present at both, DTI sidewalls and backside surfaces. Therefore, the creation of very shallow doped junctions at these surfaces reducing Idark and further crosstalk by drifting the photo-generated carriers to the photodiode region appears as key process step for introducing these architectures. For the backside surface passivation, a very shallow doped layer can be achieved by low-energy implantation followed by very short and localized heating provided by pulsed laser annealing (PLA). In the melt regime, box-shaped profiles with activation rates close to 100% and excellent crystalline quality have been achieved. The non-melt regime shows some potential, especially for multiple pulse conditions. In the optimal process conditions, very low level of Idark comparable to the standard reference has been achieved. In the other side, the passivation of DTI sidewalls has been performed by in-situ doped Epitaxy. Deposited layers with good uniformity and doping conformity all along the DTI cavity have been achieved. The electrical results show Idark values lower than the standard reference

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Mamdy, Bastien. "Nouvelle architecture de pixel CMOS éclairé par la face arrière, intégrant une photodiode à collection de trous et une chaine de lecture PMOS pour capteurs d’image en environnement ionisant". Thesis, Lyon, 2016. http://www.theses.fr/2016LYSE1197/document.

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Grâce à l'explosion du marché grand public des smartphones et tablettes, les capteurs d'image CMOS ont bénéficiés de développements technologiques majeurs leur permettant de rivaliser voir même de devancer les performances des capteurs CCD. En parallèle, dans les domaines de l'aérospatial ou de l'imagerie médicale, des capteurs CMOS ont également été développés pour des applications à fortes valeurs ajoutées avec des technologies reconnues pour leur robustesse en environnement ionisant. Le travail de cette thèse a pour but de réunir dans une même architecture de pixel les dernières avancées technologiques développées pour les capteurs grands publics avec une solution novatrice de durcissement aux rayonnements ionisants récemment développée chez STMicroelectronics. Pour la première fois, cette nouvelle architecture de pixel de 1,4µm de côté et éclairée par la face arrière intègre une photodiode pincée verticale à collection de trous, une chaine de lecture composée de transistors PMOS et des tranchées d'isolation profondes à passivation passive ou active. Ce type de pixel a été conçu à l'aide de simulations TCAD en trois dimensions qui ont permis d'optimiser l'intégration de procédés pour sa fabrication. Il a été caractérisé et comparé à un pixel équivalent de type N avant et après irradiation par rayonnement gamma. Le pixel développé au cours de cette thèse présente intrinsèquement un plus faible courant d'obscurité que son homologue de type N et une meilleure résistance aux radiations. La passivation active des tranchées d'isolation profondes permet d'atténuer fortement l'impact des dégradations habituellement observées au niveau des interfaces Si/SiO2 et s'avère donc prometteuse en environnement ionisant. Des mécanismes intrinsèquement différents de formation de pixels blancs sous irradiation ont été mis en évidence pour les pixels de type P et de type N. Enfin, les technologies de l'éclairement par la face arrière et de la photodiode verticale contribuent chacune à la bonne efficacité quantique du pixel ainsi qu'à sa capacité de stockage importante
Thanks to the growing smartphones and tablets consumer markets, CMOS image sensors have benefited from major technology developments and are able to rival with and even outperform CCD sensors. In parallel, for spatial and medical imaging applications, CMOS sensors have been developed using technologies recognized for their robustness in harsh ionizing environment. This Ph.D. thesis work aims at combining in one single pixel architecture the latest technology developments driven by consumer applications with a novel solution for radiation hardening recently developed at STMicroelectronics. For the first time, this innovative back-side illuminated pixel architecture integrates within a 1.4µm pitch a vertical pinned photodiode based on hole-collection, a PMOS readout chain and deep trench isolation with either passive or active interface passivation. This pixel has been developed using 3D-TCAD simulations allowing fast and efficient optimization of its fabrication process. Through a series of electro-optical characterizations, we have compared its performances to its N-type equivalent before and after irradiation with gamma rays. The pixel developed during this thesis exhibits intrinsically lower level of dark current than its N-type counterpart and improved radiation hardness. Active passivation of deep trench isolation greatly decreases the impact of degradations usually observed at Si/SiO2 interfaces and therefore shows very promising results in ionizing environment. Evidence of intrinsically different mechanisms of white pixel formation under irradiation for N-type and P-type pixels have been presented. Finally, back-side illumination technology and the vertical photodiode both contribute to the pixel’s high full well capacity and good quantum efficiency

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Hong-JiaKong e 龔泓家. "Studies of the Novel Shallow Trench Isolation Technology for Deep Nano CMOS Device Application". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/82697809014373009610.

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Yang, Wen-Jei, e 楊文杰. "The Width-Dependent Hot Carrier Reliability of Deep-Submicron CMOS with Shallow Trench Isolation". Thesis, 1999. http://ndltd.ncl.edu.tw/handle/64955702322560017981.

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碩士
國立交通大學
電子工程系
87
To improve the packing density of integrated circuits, scaling of CMOS isolation become indispensable. Recently, the shallow-trench-isolation (STI) technology has been widely used to achieve this goal. Moreover, STI can improve the subthreshold hump, bird掇 beak, and field oxide thinning effect in LOCOS (Local Oxidation of Silicon). However, hot-carrier effect has been be a major reliability issue in a STI device. In this thesis, width dependent hot-carrier degradation of shallow-trench-isolated MOSFET's is investigated. Smaller hot carrier injection is observed in a narrower device. However, it is shown that a narrower device causes larger drain current degradation under the same stress condition. A new model is then proposed to explain the width dependent degradation. This model is based on the channel shortening concept which can be used to explain the width dependent hot carrier degradation in PMOSFET's. It was found that the channel shortening length after device stress becomes larger at the edge of a PMOFET. Thus, a narrower PMOSFET has larger effective channel shortening length and hence a larger current degradation after stress. In the case of NMOSFET's, enhanced interface state generation was found at the STI edge. This may be due to the mechanical stress at the device edge. So, the average amount of interface states and current degradation in a narrower NMOSFET is larger after hot-carrier stress.

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Liao, Tsai-Ying, e 廖采瑩. "Low-Loss High-Isolation Sub-6 GHz MOS Switches with Deep Trench Isolation Using SiGe BiCMOS Process and Microwave GaN/Si Switches". Thesis, 2019. http://ndltd.ncl.edu.tw/handle/9muz2q.

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Capitoli di libri sul tema "Active Deep Trench Isolation"

Kato, Chiaki. "Molecular Analyses of the Sediment and Isolation of Extreme Barophiles from the Deepest Mariana Trench". In Extremophiles in Deep-Sea Environments, 27–37. Tokyo: Springer Japan, 1999. http://dx.doi.org/10.1007/978-4-431-67925-7_2.

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Kobayashi, Kazuo. "The Fate of Seamounts and Oceanic Plateaus Encountering a Deep-Sea Trench and their Effects on the Continental Margins". In Formation of Active Ocean Margins, 625–37. Dordrecht: Springer Netherlands, 1985. http://dx.doi.org/10.1007/978-94-009-4720-7_28.

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Yanda, Richard F., Michael Heynes e Anne K. Miller. "Isolate Active Areas (Shallow Trench Isolation)". In Demystifying Chipmaking, 93–128. Elsevier, 2005. http://dx.doi.org/10.1016/b978-075067760-8/50007-5.

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Jafarzadeh, F., M. Ghayoomi e A. Bahmanpour. "The effect of open trench on active foundation isolation using physical modeling". In Physical Modelling in Geotechnics. Taylor & Francis, 2006. http://dx.doi.org/10.1201/noe0415415866.ch179.

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Coulbourn, W. T. "Introduction and Summary of Active-Margin Drilling in the Nankai Trough and Japan Trench, Deep Sea Drilling Project Leg 87". In Initial Reports of the Deep Sea Drilling Project. U.S. Government Printing Office, 1986. http://dx.doi.org/10.2973/dsdp.proc.87.101.1986.

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Summerhayes, Colin. "The Antarctica Peninsula, the Falklands, and South Georgia". In The Icy Planet, 152—C5P262. Oxford University PressNew York, 2023. http://dx.doi.org/10.1093/oso/9780197627983.003.0005.

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Abstract The Antarctic Peninsula is an island arc flanked by a deep ocean trench. Volcanism is active in the Bransfield Strait, a back-arc basin. The arc is a continuation of the Andes, broken by the Drake Passage. Lying north of the Antarctic Circle, the peninsula is the warmest part of the continent, largely because it is bathed by warm winds from the north that circulate around the Amundsen Sea low pressure center. In 1950–2000 the peninsula warmed by c.2.5°C (4.5°F). It cooled slightly in 2000–2014, when local winds turned easterly, but is now warming again. Glaciers are shrinking and sea ice is disappearing down the west coast; ice shelves are disappearing down the east coast. Where sea ice disappeared, Adélie penguins declined; other species thrived, including Elephant and Weddell seals. Easterly winds blow icebergs into the Southern Ocean through Iceberg Alley along the peninsula’s east coast, but icebergs are rare on its west coast north of 65°N.

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Hutchison, Charles S. "The Geological Framework". In The Physical Geography of Southeast Asia. Oxford University Press, 2005. http://dx.doi.org/10.1093/oso/9780199248025.003.0011.

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This chapter outlines the principal geological features of the region, extending from Myanmar and Taiwan in the north, southwards to include all the ASEAN countries, and extending as far as northern Australia. The present-day lithospheric plates and plate margins are described, and the Cenozoic evolution of the region discussed. Within a general framework of convergent plate tectonics, Southeast Asia is also characterized by important extensional tectonics, resulting in the world’s greatest concentration of deep-water marginal basins and Cenozoic sedimentary basins, which have become the focus of the petroleum industry. The pre-Cenozoic geology is too complex for an adequate analysis in this chapter and the reader is referred to Hutchison (1989) for further details. A chronological account summarizing the major geological changes in Southeast Asia is given in Figure 1.2. The main geographical features of the region were established in the Triassic, when the large lithospheric plate of Sinoburmalaya (also known as Sibumasu), which had earlier rifted from the Australian part of Gondwanaland, and collided with and became sutured onto South China and Indochina, together named Cathaysia. The result was a great mountain-building event known as the Indosinian orogeny. Major granites were emplaced during this orogeny, with which the tin and tungsten mineral deposits were genetically related. The orogeny resulted in general uplift and the formation of major new landmasses, which have predominantly persisted as the present-day regional physical geography of Southeast Asia. The Indo-Australian Plate is converging at an average rate of 70 mm a−1 in a 003° direction, pushed from the active South Indian Ocean spreading axis. For the most part it is composed of the Indian Ocean, formed of oceanic sea-floor basalt overlain by deep water. It forms a convergent plate margin with the continental Eurasian Plate, beneath which it subducts at the Sunda or Java Trench. The Eurasian continental plate protrudes as a peninsular extension (Sundaland) southwards as far as Singapore, continuing beneath the shallow Straits of Malacca and the Sunda Shelf as the island of Sumatra and the northwestern part of Borneo.

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Atti di convegni sul tema "Active Deep Trench Isolation"

Lee, Seunghwan, Jeongjin Cho, Shinyoung Choi, Sung Yoon Min, Eunjung Lee, Minji Jung, Kyoungmok Son et al. "A Temporal Noise Reduction via 40% Enhanced Conversion Gain in Dual-Pixel CMOS Image Sensor with Full-Depth Deep-Trench Isolation and Locally Lowered-Stack Technology". In 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 1–2. IEEE, 2024. http://dx.doi.org/10.1109/vlsitechnologyandcir46783.2024.10631436.

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Herfurth, Norbert, Awwal A. Adesunkanmi, Abdelkhalek Bouchtouq, Gerfried Zwicker e Christian Boit. "Novel Backside IC Preparation Stopping on STI with Full Circuit Functionality Using Chemical Mechanical Polishing (CMP) with Highly Selective Slurry". In ISTFA 2024, 416–21. ASM International, 2024. http://dx.doi.org/10.31399/asm.cp.istfa2024p0416.

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Abstract Mechanical sample preparation is a crucial and indispensable step in modern failure analysis (FA). Traditional methods excel in reducing bulk silicon to thicknesses of several tens of micrometers. However, contemporary demands necessitate sample preparation below 10 µm or even below 5 µm, which is challenging, time-consuming, and requires an expensive toolset and advanced operator expertise. Existing methods, which rely on mechanical components for bulk removal, induce mechanical stress and microcracks that can alter the electrical characteristics of the sample. Maintaining the sample's electrical behavior is essential for accurate FA. This paper introduces a novel approach to sample preparation that employs concepts from wafer-level chemical mechanical polishing (CMP). This method ensures reliable sample preparation without introducing microcracks, accurately halts material removal at the shallow trench isolation (STI) – or deep STI - level, and maintains the sample's electrical functionality. The proposed approach is discussed in detail, including successful thinning of various sample types to the STI level, which were subsequently tested for electrical functionality.

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Park, Byung Jun, Chang-Rok Moon, Young Woo Lee, Dae Woong Kim, Kee Hyun Paik, Jong Rycol Yoo, Young Sub Yoo et al. "Deep Trench Isolation for Pixel Crosstalk Suppression in Active Pixel Sensor with 1.7μm pixel pitch". In 2006 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2006. http://dx.doi.org/10.7567/ssdm.2006.b-9-2.

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Aurelio, Mario, Kristine Joy Taguibao, Edmundo Vargas, Maria Visitacion Palattao, Rolando Reyes, Carl Nohay, Roy Anthony Luna e Alfonso Singayan. "Geological Criteria for Site Selection of an LILW Radioactive Waste Repository in the Philippines". In ASME 2013 15th International Conference on Environmental Remediation and Radioactive Waste Management. American Society of Mechanical Engineers, 2013. http://dx.doi.org/10.1115/icem2013-96127.

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In the selection of sites for disposal facilities involving low- and intermediate-level radioactive waste (LILW), International Atomic Energy Agency (IAEA) recommendations require that “the region in which the site is located shall be such that significant tectonic and surface processes are not expected to occur with an intensity that would compromise the required isolation capability of the repository”. Evaluating the appropriateness of a site therefore requires a deep understanding of the geological and tectonic setting of the area. The Philippines sits in a tectonically active region frequented by earthquakes and volcanic activity. Its highly variable morphology coupled with its location along the typhoon corridor in the west Pacific region subjects the country to surface processes often manifested in the form of landslides. The Philippine LILW near surface repository project site is located on the north eastern sector of the Island of Luzon in northern Philippines. This island is surrounded by active subduction trenches; to the east by the East Luzon Trough and to the west by the Manila Trench. The island is also traversed by several branches of the Philippine Fault System. The Philippine LILW repository project is located more than 100 km away from any of these major active fault systems. In the near field, the project site is located less than 10 km from a minor fault (Dummon River Fault) and more than 40 km away from a volcanic edifice (Mt. Caguas). This paper presents an analysis of the potential hazards that these active tectonic features may pose to the project site. The assessment of such geologic hazards is imperative in the characterization of the site and a crucial input in the design and safety assessment of the repository.

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Lerner, Ralf, Uwe Eckoldt, Klaus Schottmann, Steffen Heinz, Klaus Erler, Andre Lange e Gunter Ebest. "Time Dependent Isolation Capability of High Voltage Deep Trench Isolation". In IC's (ISPSD). IEEE, 2008. http://dx.doi.org/10.1109/ispsd.2008.4538934.

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Thuy Dao, Todd Roggenbauer e Gordon Boyd. "Improved deep trench isolation breakdown voltage for SmartMOS". In 2013 International Conference on IC Design & Technology (ICICDT). IEEE, 2013. http://dx.doi.org/10.1109/icicdt.2013.6563313.

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Ahmed, N., F. Roy, G.-N. Lu, B. Mamdy, J.-P. Carrere, A. Tournier, N. Virollet et al. "MOS Capacitor Deep Trench Isolation for CMOS image sensors". In 2014 IEEE International Electron Devices Meeting (IEDM). IEEE, 2014. http://dx.doi.org/10.1109/iedm.2014.7046979.

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Chatterjee, Amitava, M. Nandakumar, Stan Ashburn, Vikas Gupta, Siang P. Kwok e Ih-Chin Chen. "On Shallow Trench Isolation for Deep Submission CMOS Technologies". In 1998 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1998. http://dx.doi.org/10.7567/ssdm.1998.a-8-1.

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Park, Ahn, Kim, Lee, Lee e Lee. "Double Trench Isolation (DTI): A Novel Isolation Technology For Deep-submicron Silicon Devices". In Symposium on VLSI Technology. IEEE, 1993. http://dx.doi.org/10.1109/vlsit.1993.760286.

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Han, Kyung Joon, Martin Stiftinger, Ronald Kakoschke, Nigel Chan, Sungrae Kim, Ben Leung, Volker Hecht et al. "A Novel Flash-based FPGA Technology with Deep Trench Isolation". In 2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop. IEEE, 2007. http://dx.doi.org/10.1109/nvsmw.2007.4290569.

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Rapporti di organizzazioni sul tema "Active Deep Trench Isolation"

The space between: Analysis of gender and ethnicity pay gaps in UK-based organisations active in global health. Global Health 50/50, novembre 2023. http://dx.doi.org/10.56649/zhpp4836.

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Inequalities in opportunities, power and privilege are evident in our working lives. Historical structures shape opportunities in the career pipelines of different groups of people, including access to education, recruitment and promotion, occupational segregation and the so-called ‘motherhood penalty’. Often these dynamics result in certain groups, particularly men and traditionally privileged ethnic groups, occupying higher status and better paid positions, than other groups – resulting in what are called ‘pay gaps’. Increasing transparency on pay gaps helps to ensure that employers are being fair in providing equitable (fair) opportunities and reducing inequalities across the workforce it also holds them accountable for closing the gap. In the UK, reporting the gender pay gap has been mandatory since 2017 for organisations with more than 250 employees. The law has driven an unprecedented level of transparency on the gender pay gap in the UK and provided valuable information to employers and employees on inequality inside their organisations. To date, however, reporting the ethnicity pay gap remains voluntary. Global Health 50/50 (GH5050) tracks and publicises the policies and practices of nearly 200 organisations active in global health for their commitments to gender equality. This Report takes a deep dive into the reporting of gender and ethnicity pay gap data of 43 organisations in the GH5050 sample which have a presence in the UK. This Report focuses specifically on UK-based organisations given the general lack of pay gap reporting worldwide. The Report finds that, between 2017 and 2022, some progress was made in closing the gap – from 12.7% to 10.9% for median pay gap, and from 14.3% to 10.8% for mean pay gap. A quarter of organisations, however, saw an increase in their gender pay gap by a median 3.6 percentage points. In the absence of mandatory reporting, we found that only 13 organisations voluntarily reported their ethnicity pay gaps in 2022, mostly reporting binary gaps between white and ethnic minority employees. While binary reporting in isolation is generally not recommended, it may be needed to protect salary information of ethnic minority employees when numbers of employees are small. Among this (limited) data, we found a median gap of 3.7% and a mean gap of 6.9% favouring white employees. This Report finds that there has been some positive change since mandatory gender pay gap reporting was introduced in 2017. Yet slow and uneven progress indicates a clear need for continued advocacy to ensure pay gap transparency and to close the gender pay gap. This advocacy should include the expansion of mandatory pay gap reporting to include ethnicity; and for very large organisations, an intersectional approach to the data (combining gender and ethnicity, for example) will provide even more nuance and understanding of where action is needed. Even in the absence of legislative requirements, employers in global health, which are often working to advance social justice and gender equality, should act as models for career equality including by publicly reporting pay gap data. This data can inform target-setting and the development of policies to reduce the gap, such as including multiple women in shortlists for recruitment and promotion, and transparency in pay negotiations. Closing the unjust space between women’s and men’s pay is an urgent priority and would ensure that women are equally and fairly paid for their contributions to organisations and to society. Increasing transparency of the pay gaps will rely on more countries passing legislation, as a critical component of comprehensive frameworks for diversity, inclusion and equality in the workplace.

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