Bibliographies thématiques / VERILOG IMPLEMENTATION

Littérature scientifique sur le sujet « VERILOG IMPLEMENTATION »

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Publié le 11 septembre 2023

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Articles de revues sur le sujet "VERILOG IMPLEMENTATION"

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Koti, Mr Manjunath, et Dr Basavaraj I. Neelgar. « CAN Tx Frame Implementation using Verilog ». Journal of University of Shanghai for Science and Technology 23, no 07 (29 juillet 2021) : 1303–13. http://dx.doi.org/10.51201/jusst/21/07311.

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This article discusses the concept of CAN protocol and its implementation in verilog language. Initially the CAN protocol description is given in brief with the block diagram, later its design, implementation in verilog code is presented. The CAN transmission (Tx) data Frame is realized using verilog code, this is achieved by defining individual sub-blocks verilog codes and combining these to get the CAN transmission of data frame. In the year 1986, CAN data link layer protocol was introduced in SAE conference. In 1993, CAN protocol and high speed physical layer were internationally accredited as ISO 11898. As on today it has 11898-1 to 4 standard documents. The CAN 1.0, 2.0 versions were initially had fixed data rate for the entire frame. In 2012, CAN-FD (Flexible data rate) protocol was introduced. This will allow data phase a second higher bit rate, along with this restriction of 8 bytes is extended up to 64 bytes.In this paper CAN Tx data frame is realized using Xilinx 14.7 version using verilog language.
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Paramahamsa, Prof Mr YRK. « Implementation of Zigbee Transmitter using Verilog ». International Journal for Research in Applied Science and Engineering Technology V, no III (28 mars 2017) : 1010–17. http://dx.doi.org/10.22214/ijraset.2017.3185.

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Shet, Ganesh Gopal, Jamuna V, Shravani S, Nayana H G et Pramod Kumar S. « Implementation of AES Algorithm using Verilog ». JNNCE Journal of Engineering and Management 4, no 1 (30 novembre 2020) : 17. http://dx.doi.org/10.37314/jjem.2020.040103.

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Krishna, T. Rama, T. Krishna Murthy, N. Vilasrao Sarode, P. Srilakshmi et V. Geetha Sri. « Verilog HDL using LTE Implementation MAP Algorithm ». International Journal of Innovative Research in Computer Science and Technology 10, no 2 (30 mars 2022) : 611–14. http://dx.doi.org/10.55524/ijircst.2022.10.2.115.

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In many communication systems, turbo coding Techniques for Encoding and Decoding are employed to repair errors. As compared to other error correction codes, turbo codes provide great error correcting capabilities. For the implementation of the Turbo decoder, a Very Large Scale Integration (VLSI) architecture is suggested in this study. The Maximum-a-Posteriori (MAP) algorithm is employed at the decoder side, where soft-in-soft-out decoders, interleaves, and deinterleavers are all used. The usage of the MAP algorithm reduces the quantity of iterations necessary to decode the information bits being transferred. This research employs a system for the encoder component that consists of two recursive convolutional encoders and a pseudorandom interleaver on the encoder side. Tools from Octave and Xilinx Vivado are used for the Turbo encoding and decoding. The system is synthesised and implemented using a specialised integrated circuit.
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Zheng, Li Kun, Ya Li Chen et Zhe Ying Li. « Design and Implementation of USB Transceiver with Verilog ». Applied Mechanics and Materials 462-463 (novembre 2013) : 604–8. http://dx.doi.org/10.4028/www.scientific.net/amm.462-463.604.

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The Universal Serial Bus Transceiver is one of the important functional blocks of USB controller, which can transmit and receive data to or from USB devices. In this paper, USB Transceiver is designed and implemented with Verilog HDL, This includes functions such as, data serialization, bit stuffing, NRZI encoding and NRZI decoding, bit destuffing, deserialization. The transceiver is simulated by the modelsim software and the simulation wave is gave.
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Perali, Sri Phanindra, Nithin Krishna Madadi et Rohith Reddy. « RTL Implementation of AMBA AHB Protocol using Verilog ». International Journal for Research in Applied Science and Engineering Technology 11, no 4 (30 avril 2023) : 4056–63. http://dx.doi.org/10.22214/ijraset.2023.51179.

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Abstract: The enactment of a computer system heavily depends on the design of its bus interconnect. A poorly designed system bus can hinder the transmission of instructions and data between the processor and memory or between peripheral devices and memory. To address these challenges, the Advanced Microcontroller Bus Architecture (AMBA) provides an open standard for connecting and managing functional blocks in a System-on-Chip (SoC). This architecture allows for developing multi-processor designs with many controllers and peripherals while ensuring the system is designed correctly the first time. Furthermore, the AMBA specifications are royalty-free and platform-independent. They can be used with any processor architecture. The project will provide an RTL view and an extracted design summary of the AMBA AHB module at the system-on-chip level. The AMBA High-performance Bus (AHB) is another part of the AMBA family of conventions. The AHB is designed to support highperformance, high-clock system modules and serves as the system's high-performance backbone bus. The AHB enables the efficient connection of low-power peripheral functions to processors, on-chip memories, and external off-chip memory interfaces. All signal transitions in the AHB relate only to the rising clock edge, allowing AHB peripherals to be easily integrated into any design flow. The project also describes the AMBA AHB design and implementation using Verilog, with read/write operations implemented using the Xilinx simulator.
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J, Padmini, et V. Nanammal. « FPGA Implementation of Digital Modulation Schemes Using Verilog HDL ». International Journal for Research in Applied Science and Engineering Technology 10, no 9 (30 septembre 2022) : 560–67. http://dx.doi.org/10.22214/ijraset.2022.46596.

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Abstract: This paper describes the design and development of an FPGA-based digital Modulation Scheme for high-resolution Communication Application. We are focusing on implementation of Verilog based code simulation for fundamental and widely used digital modulation techniques such as Binary Amplitude-shift keying (BASK), Binary Frequency-shift keying (BFSK), Binary Phase-shift keying (BPSK) and Quadrature Phase Shift Keying(QPSK). In this work the idea of sinusoidal signals that have been generated is plain sailing in nature and based on fundamentals of signal sampling and quantization. Such concept of sinusoidal signals generation is not unfamiliar but somehow simplified using sampling and quantization in time and amplitude domain, respectively. The whole simulation is done on Modelsim and Xilinx-ISE using VERILOG Hardware descriptive language. The work has been accomplished on Thirty two bit serial data transmission with self-adjustable carrier frequency and bit duration length.
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Sreekanth, P. « Verilog Implementation of Image Compression Using Discrete Wavelet Transform ». CVR Journal of Science & ; Technology 9, no 1 (1 décembre 2015) : 21–25. http://dx.doi.org/10.32377/cvrjst0905.

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Balakrishna, J. « Design and Implementation of RFID Controller using Verilog HDL ». International Journal for Research in Applied Science and Engineering Technology 9, no VI (30 juin 2021) : 4335–42. http://dx.doi.org/10.22214/ijraset.2021.35942.

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Manual monitoring consumes more time, man power and shows inaccurate results. So, automation is the solution to cover the problems stated. Barcode and RFID are two different forms of automated technology that are used for reading and collecting data. The RFID (Radio Frequency Identification) technology is a well-known wireless application for traceability, logistics and access control. The RFID controller is constructed in to demonstrate access control through the use of low-frequency RFID tags. These tags contain identification number which is read by the reader, sent to a database where it is compared with stored values. It works on the principle that If the tag’s identification number is in the system database, it gives access. If the data is not in the system database, it doesn’t give access. To implement these various blocks, include RFID transmitter, RFID receiver, Baud clock generator, Database are designed. The RFID Controller is designed using Verilog HDL in Xilinx ISE tool.
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Pari, Kumar. « Implementation of reduced memory Viterbi Decoder using Verilog HDL ». IOSR Journal of Electronics and Communication Engineering 8, no 4 (2013) : 73–79. http://dx.doi.org/10.9790/2834-0847379.

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Thèses sur le sujet "VERILOG IMPLEMENTATION"

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Skärpe, Anders. « Implementation of an SDR in Verilog ». Thesis, Linköpings universitet, Kommunikationssystem, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-132325.

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This report presents an implementation of the software part in a software definedradio. The radio is not entirely implemented in software and therefore there arecertain limitations on the received signal. The parts implemented are oscillator,decimation filter, carrier synchronization, time synchronization, package detection,and demodulation. Different algorithms were tested for the different partsto measure the power consumption. To understand how the number of bits usedto represent the signal affects the power consumption, the number of bits wasreduced from 20 bits to 10 bits. This reduction reduced the power consumptionfrom 2.57mW to 1.89mW. A small change in the choice of algorithms was thenmade which reduced the power consumption to 1.86mW. Then the clock rate wasreduced for some parts of the system which reduced the power consumption to1.05mW.
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Chen, Adam Y. (Adam Yu-Chih). « Implementation of the Intel 486 SX microprocessor in Verilog hardware description language ». Thesis, Massachusetts Institute of Technology, 1993. http://hdl.handle.net/1721.1/79470.

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RAGHURAMAN, SRINIVASAN. « IMPLEMENTATION AND PERFORMANCE MEASUREMENTS OF A VERILOG-AMS MODEL OF BSIM3v3.3 TRANSISTOR ». University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1163711277.

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NARAYANAN, SHRUTHI. « HARDWARE IMPLEMENTATION OF GENETIC ALGORITHM MODULES FOR INTELLIGENT SYSTEMS ». University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1122909070.

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Kasarabada, Yasaswy. « A Verilog Description and Efficient Hardware Implementation of the Baillie-PSW Primality Test ». University of Cincinnati / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1471347471.

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Park, Sungho. « A verilog-hdl implementation of virtual channels in a network-on-chip router ». [College Station, Tex. : Texas A&M University, 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2890.

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Sampath, Kumar Santhiya. « Implementation of Low-Bit Rate Audio Codec, Codec2, in Verilog on Modern FPGAS ». Miami University / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=miami158819886466373.

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Pampana, Srilaxmi. « FPGA BASED IMPLEMENTATION OF A POSITION ESTIMATOR FOR CONTROLLING A SWITCHED RELUCTANCE MOTOR ». UKnowledge, 2004. http://uknowledge.uky.edu/gradschool_theses/254.

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Rotor Position information is essential in the operation of the Switched Reluctance Motor (SRM) for properly controlling its phase currents. This thesis uses Field Programmable Gate Array (FPGA) technology to implement a method to estimate the SRMs rotor position using the inverse inductance value of the SRMs phases. The estimated rotor position is given as input to the Commutator circuit, also implemented in the FPGA, to determine when torque-producing currents should be input in the SRM phase windings. The Estimator and Commutator design is coded using Verilog HDL and is simulated using Xilinx tools. This circuit is implemented on a Xilinx Virtex XCV800 FPGA system. The experimentally generated output is validated by comparing it with simulation results from a Simulink model of the Estimator. The performance of the FPGA based SRM rotor position estimator in terms of calculation time is compared to a digital signal processor (DSP) implementation of the same position estimator algorithm. It is found that the FPGA rotor position Estimator with a 5MHz clock can update its rotor position estimate every 7s compared to an update time of 50s for a TMS320C6701-150 DSP implementation using a commercial DSP board. This is a greater than 7 to one reduction in the update time.
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Thakur, Ravi Bhushan. « Low power design implementation of a signal acquisition module ». Thesis, Kansas State University, 2010. http://hdl.handle.net/2097/4617.

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Master of Science
Department of Electrical and Computer Engineering
Don M. Gruenbacher
As semiconductor technologies advance, the smallest feature sizes that can be fabricated get smaller. This has led to the development of high density FPGAs capable of supporting high clock speeds, which allows for the implementation of larger more complex designs on a single chip. Over the past decade the technology market has shifted toward mobile devices with low power consumption at or near the top of design considerations. By reducing power consumption in FPGAs we can achieve greater reliability, lower cooling cost, simpler power supply and delivery, and longer battery life. In this thesis, FPGA technology is discussed for the design and commercial implementation of low power systems as compared to ASICs or microprocessors, and a few techniques are suggested for lowering power consumption in FPGA designs. The objective of this research is to implement some of these approaches and attempt to design a low power signal acquisition module. Designing for low power consumption without compromising performance requires a power-efficient FPGA architecture and good design practices to leverage the architectural features. With various power conservation techniques suggested for every stage of the FPGA design flow, the following approach was used in the design process implementation: the switching activity is addressed in the design entry, and synthesis level and software tools are utilized to get an initial estimate of and optimize the design’s power consumption. Finally, the device choice is made based on its features that will enhance the optimization achieved in the previous stages; it is configured and real time board level power measurements are made to verify the implementation’s efficacy
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Gumus, Rasit. « Implementation Of A Risc Microcontroller Using Fpga ». Master's thesis, METU, 2005. http://etd.lib.metu.edu.tr/upload/2/12606694/index.pdf.

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In this thesis a microcontroller core is developed in an FPGA. Its instruction set is compatible with the microcontroller PIC16XX series by Microchip Technology. The microcontroller employs a RISC architecture with separate busses for instructions and data. Our goal in this research is to implement and evaluate the design in the FPGA. Increasing performance and gate capacity of recent FPGA devices permits complex logic systems to be implemented on a single programmable device. Such a growing complexity demands design approaches, which can lead to designs containing millions of logic gates, memories, high-speed interfaces, and other high-performance components. In recent years, the continuous development in the area of highly integrated circuits has lead to a change in the design methods used, making it possible to economically utilize FPGAs in many designs. A test demo board from the Digilent Inc is used to fit our testing requirements of the RISC microcontroller. The test demo board also had the capability of communicating with a personal computer (PC) so that we can load the program from PC. Based on the modern design methods the microcontroller core is developed using the Verilog hardware description language. Xilinx ISE Foundation 6.3i software is used for its synthesis and implementation. An embedded test program code using MPLAB is also developed, and then loaded into the designed microcontroller residing in the FPGA. In order to perform a functional test of the microcontroller core a special test program downloader application is designed by using Borland C++ Builder. First, the specification from the PIC16XX datasheet is transferred into an abstract behavioral description. Based on that, the next step is to develop a description of the microcontroller core with some minor modifications which can be synthesizable into a FPGA. Finally, the resulting gate level netlist is evaluated and tested using a demo board.
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Livres sur le sujet "VERILOG IMPLEMENTATION"

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New, York (State) Legislature Assembly Committee on Corporations Authorities and Commissions. Public hearing on service quality issues relating to the implementation of the Verizon incentive. [Mineola] : EN-DE Reporting, 2002.

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Scarpino. Vhdl Verilog Digital Systems Implementation. Pearson Education, Limited, 2020.

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Digital System Design with FPGA : Implementation Using Verilog and VHDL. McGraw-Hill Education, 2017.

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Digital VLSI Systems Design : A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog. Springer London, Limited, 2007.

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Ramachandran, Seetharaman. Digital VLSI Systems Design : A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog. Springer Netherlands, 2014.

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Digital VLSI Systems Design : A Design Manual for Implementation of Projects on FPGAs and ASICs Using Verilog. Springer, 2007.

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Chapitres de livres sur le sujet "VERILOG IMPLEMENTATION"

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Mohamed, Khaled Salah. « Verilog for Implementation and Verification ». Dans Analog Circuits and Signal Processing, 97–119. Cham : Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-22035-2_5.

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Navabi, Zainalabedin. « Verilog for Simulation and Synthesis ». Dans Digital Design and Implementation with Field Programmable Devices, 59–103. Boston, MA : Springer US, 2005. http://dx.doi.org/10.1007/1-4020-8012-3_3.

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Tijare, Ankita, Prajwal Yelne, Ankit Mindewar et Khushboo Borgaonkar. « Verilog implementation of AES 256 algorithm ». Dans Recent Advances in Material, Manufacturing, and Machine Learning, 464–68. London : CRC Press, 2023. http://dx.doi.org/10.1201/9781003358596-51.

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Kumar, Sandeep, et Trailokya Nath Sasamal. « Verilog Implementation of High-Speed Wallace Tree Multiplier ». Dans Lecture Notes in Networks and Systems, 457–69. Singapore : Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-8218-9_38.

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Ye, Yunqing, et Shuying Cheng. « Implementation of 2D-DCT Based on FPGA with Verilog HDL ». Dans Lecture Notes in Electrical Engineering, 633–39. Berlin, Heidelberg : Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-21697-8_80.

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Glasmacher, Alexander, et Kai Woska. « Design and Implementation of an XC6216 FPGA Model in Verilog ». Dans Lecture Notes in Computer Science, 449–55. Berlin, Heidelberg : Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-44614-1_48.

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Shashikumar, M., Bhaskar Jyoti Das, Jagritee Talukdar et Kavicharan Mummaneni. « Radix-10 Multiplier Implementation with Carry Skip Adder Using Verilog ». Dans Lecture Notes in Electrical Engineering, 397–405. Singapore : Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-3767-4_38.

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Suhaili, Shamsiah Binti, Rene Brooke Fredrick, Zainah Md Zain et Norhuzaimin Julai. « Design and Implementation of Advanced Encryption Standard Using Verilog HDL ». Dans Lecture Notes in Electrical Engineering, 483–98. Singapore : Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-2406-3_37.

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Venkatasatyakranthikumar, Taddi, Samparka Dey, Malvika, Vivek kumar et Kavicharan Mummaneni. « Design and Implementation of Bus Ticketing System Using Verilog HDL ». Dans Lecture Notes in Electrical Engineering, 259–65. Singapore : Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-4495-8_21.

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Sandhya, Goundla, et Dheeraj Kumar Sharma. « Software Implementation of Plantlet Stream Cipher Using Verilog Hardware Description Language ». Dans Lecture Notes in Electrical Engineering, 107–18. Singapore : Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0312-0_12.

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Actes de conférences sur le sujet "VERILOG IMPLEMENTATION"

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Mushtaq, U., O. Hasan et F. Awwad. « PNOC : Implementation on Verilog for FPGA ». Dans 2013 9th International Conference on Innovations in Information Technology (IIT). IEEE, 2013. http://dx.doi.org/10.1109/innovations.2013.6544409.

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Du, Zihang, Yang Liu, Chaoqun Qiu et Xinmeng Zhang. « Verilog implementation of configurable UART module ». Dans Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022), sous la direction de Shi Jin et Wanyang Dai. SPIE, 2023. http://dx.doi.org/10.1117/12.2672692.

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Guru, R. Pavithra, et C. Kalyana Sundram. « Verilog module for on the Go implementation ». Dans 2016 International Conference on Energy Efficient Technologies for Sustainability (ICEETS). IEEE, 2016. http://dx.doi.org/10.1109/iceets.2016.7583851.

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Nagpurwala, Armaan Hasan, C. Sundaresan et CVS Chaitanya. « Implementation of HDLC controller design using Verilog HDL ». Dans 2013 International Conference on Electrical, Electronics and System Engineering (ICEESE). IEEE, 2013. http://dx.doi.org/10.1109/iceese.2013.6895033.

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Tamuli, Manashwi, Shreyasee Debnath, Ashok Ray et Swanirbhar Majumdar. « Implementation of Jacobi iterative solver in verilog HDL ». Dans 2016 2nd International Conference on Control, Instrumentation, Energy & Communication (CIEC). IEEE, 2016. http://dx.doi.org/10.1109/ciec.2016.7513747.

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., Nisha, et Prashanth Barla. « Implementation of Least Mean Square Algorithm Verilog HDL ». Dans Second International Conference on Signal Processing, Image Processing and VLSI. Singapore : Research Publishing Services, 2015. http://dx.doi.org/10.3850/978-981-09-6200-5_o-75.

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Singh, Amita, S. Pratap Singh, M. Lakshmanan et V. K. Pandey. « Verilog Implementation of Diffusion Concentration in Molecular Communication ». Dans 2020 2nd International Conference on Advances in Computing, Communication Control and Networking (ICACCCN). IEEE, 2020. http://dx.doi.org/10.1109/icacccn51052.2020.9362889.

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Rinoj, B. Michael Vinoline, et J. Jeya Caleb. « Implementation of neural network based controller using Verilog ». Dans 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN). IEEE, 2011. http://dx.doi.org/10.1109/icsccn.2011.6024574.

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Pathirage, T. D., H. P. D. K. Wijewardana, L. A. S. Lakshan, Hassaan Hydher et Lasith Yasakethu. « Multi-Prime RSA Verilog Implementation Using 4-Primes ». Dans 2021 10th International Conference on Information and Automation for Sustainability (ICIAfS). IEEE, 2021. http://dx.doi.org/10.1109/iciafs52090.2021.9605975.

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Engin, Deniz, et Berna Ors. « Implementation of Enigma machine using verilog on an FPGA ». Dans 2015 9th International Conference on Electrical and Electronics Engineering (ELECO). IEEE, 2015. http://dx.doi.org/10.1109/eleco.2015.7394608.

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