Bibliographies thématiques / VEDIC MULTIPLIER

Littérature scientifique sur le sujet « VEDIC MULTIPLIER »

Auteur : Grafiati
Publié le 11 septembre 2023

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Articles de revues sur le sujet "VEDIC MULTIPLIER"

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Eshack, Ansiya, et S. Krishnakumar. « Pipelined vedic multiplier with manifold adder complexity levels ». International Journal of Electrical and Computer Engineering (IJECE) 10, no 3 (1 juin 2020) : 2951. http://dx.doi.org/10.11591/ijece.v10i3.pp2951-2958.

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Recently, the increased use of portable devices, has driven the research world to design systems with low power-consumption and high throughput. Vedic multiplier provides least delay even in complex multiplications when compared to other conventional multipliers. In this paper, a 64-bit multiplier is created using the Urdhava Tiryakbhyam sutra in Vedic mathematics. The design of this 64-bit multiplier is implemented in five different ways with the pipelining concept applied at different stages of adder complexities. The different architectures show different delay and power consumption. It is noticed that as complexity of adders in the multipliers reduce, the systems show improved speed and least hardware utilization. The architecture designed using 2 x 2 – bit pipelined Vedic multiplier is, then, compared with existing Vedic multipliers and conventional multipliers and shows least delay.
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Khubnani, Rashi, Tarunika Sharma et Chitirala Subramanyam. « Applications of Vedic multiplier - A Review ». Journal of Physics : Conference Series 2225, no 1 (1 mars 2022) : 012003. http://dx.doi.org/10.1088/1742-6596/2225/1/012003.

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Abstract Vedic Multiplier is a key tool in rapidly growing technology especially in the immense domain of Image processing, Digital Signal Processing, real-time signal. Multipliers are important block in digital systems and play a critical role in digital designs. Along with accuracy demand for minimizing time area, power, and delay of the processor by enhancing speed is the focus point. Vedic mathematics rules and Algorithms generate partial products concurrently and save time. This paper is a review of the application and modification of Vedic multiplier in different fields and a comparison of Vedic multiplier with other multipliers for enhancing performance parameters.
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Rashno, Meysam, Majid Haghparast et Mohammad Mosleh. « A new design of a low-power reversible Vedic multiplier ». International Journal of Quantum Information 18, no 03 (avril 2020) : 2050002. http://dx.doi.org/10.1142/s0219749920500021.

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In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.
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Kuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan et Abraham K. Thomas. « Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques ». Journal of Signal Processing 8, no 2 (22 juin 2022) : 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.

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Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.
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Ganjikunta, Ganesh Kumar, Sibghatullah I. Khan et M. Mahaboob Basha. « A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics ». Journal of Low Power Electronics 15, no 3 (1 septembre 2019) : 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.

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A high speed N × N bit multiplier architecture that supports signed and unsigned multiplication operations is proposed in this paper. This architecture incorporates the modified two's complement circuits and also N × N bit unsigned multiplier circuit. This unsigned multiplier circuit is based on decomposing the multiplier circuit into smaller-precision independent multipliers using Vedic Mathematics. These individual multipliers generate the partial products in parallel for high speed operation, which are combined by using high speed adders and parallel adder to generate the product output. The proposed architecture has regular-shape for the partial product tree that makes easy to implement. Finally, this multiplier architecture is implemented in UMC 65 nm technology for N = 8, 16 and 32 bits. The synthesis results shows that the proposed multiplier architecture improves in terms of speed and also reduces power-delay product (PDP), compared to the architectures in the literature.
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Safoev, Nuriddin, et Jun-Cheol Jeon. « Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata ». Electronics 9, no 6 (23 juin 2020) : 1036. http://dx.doi.org/10.3390/electronics9061036.

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A multiplier is one of the main units for digital signal processing and communication systems. In this paper, a high speed and low complexity multiplier is designed on the basis of quantum-dot cellular automata (QCA), which is considered promising nanotechnology. We focus on Vedic multiplier architectures according to Vedic mathematics from ancient Indian sculptures. In fact, an adder is an important block in the design of almost all types of multipliers and a ripple carry adder is used to design simple multiplier implementations. However, a high-speed multi-bit multiplier requires high-speed adder owing to carry propagation. Cell-interaction-based QCA adders have better improvements over conventional majority-gate-based adders. Therefore, a two-bit Vedic multiplier is proposed in QCA and it is used to implement a four-bit form of the multiplier. The proposed architecture has a lower cell count and area compared to other existing structures. Moreover, simulation results demonstrate that the proposed design is sustainable and can be used to realize complex circuit designs for QCA communication networks.
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CVS, Chaitanya, Sundaresan C, P. R. Venkateswaran, Keerthana Prasad et V. Siva Ramakrishna. « Design of High-Speed Multiplier Architecture Based on Vedic Mathematics ». International Journal of Engineering & ; Technology 7, no 2.4 (10 mars 2018) : 105. http://dx.doi.org/10.14419/ijet.v7i2.4.11228.

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High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyamsutra of Vedic Multiplication has been presented in this paper. The multiplier architecture is implemented using Verilog coding and synthesise during Cadence RTL Compiler. Physical design is implemented using Cadence Encounter RTL-to-GDSII System using standard 180nm technology. The proposed multiplier architecture is compared with the conventional multiplier and the results show significant improvement in speed and power dissipation.
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C, Pradeepa S., Gowri G. Bennur, Hruthika G, Adithya M et Acharya Vinay Vasudeva. « Design and VLSI Implementation of Vedic Multiplier using 45nm Technology ». International Journal for Research in Applied Science and Engineering Technology 11, no 5 (31 mai 2023) : 964–68. http://dx.doi.org/10.22214/ijraset.2023.51676.

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Abstract: This paper proposes low-power multiplier architectures based on Vedic mathematics, which is a set of ancient Indian techniques for performing arithmetic operations. The proposed architectures use the Urdhva-Tiryagbhyam sutra from Vedic mathematics, which enables the efficient multiplication of numbers with fewer partial products. The proposed architectures have been implemented and simulated using the 45-nm CMOS technology. The simulation results demonstrate that the proposed architectures achieve significant power savings compared to conventional multipliers while maintaining reasonable area and delay. Therefore, the proposed architectures are suitable for use in low-power and high-performance applications. The Vedic multiplier consists of several sub-modules, each of which performs a specific function in the multiplication process. These submodules include the partial product generator, the multiplier, and the adder. The partial product generator generates partial products based on the input numbers and the Vedic sutras. The multiplier module then combines these partial products to create the final product. Finally, the adder module adds the product to the previous state of the circuit to generate the final result.
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Bhairannawar, Satish s., Raja K B, Venugopal K R et L. M. Patnaik. « EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER ». INTERNATIONAL JOURNAL OF COMPUTERS & ; TECHNOLOGY 12, no 5 (30 janvier 2014) : 3452–63. http://dx.doi.org/10.24297/ijct.v12i5.2915.

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Most of the algorithms which are used in DSP, image and video processing, computer graphics, vision and high performance supercomputing applications require multiplication and matrix operation as the kernel operation.In this paper, we propose Efficient FPGA based matrix multiplication using MUX and Vedic multiplier. The 2x2, 3x2 and 3x3 MUX based multipliers are designed. The basic lower order MUX based multipliers are used to design higher order MxN multipliers with a concept of UrdhvaTiryakbyham Vedic approach. The proposed multiplier is used for image processing applications. It is observed that the device utilization and combinational delay are less in the proposed architecture compared to existing architectures.
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Nandha Kumar, P. « Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology ». Asian Journal of Electrical Sciences 11, no 2 (15 décembre 2022) : 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.

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Multipliers are the basic building blocks in various digital signal processing applications such as convolution, correlation, and filters. However, conventional array multipliers, vedic multipliers were resulted in higher area, power, delay consumptions. Therefore, this work is focused on design and implementation of variable width Radix-4 booth multiplier using Data Scaling Technology (DST). The radix-4 modified booth encoding was used in the production of these incomplete items. In accumulation, the bits of the fractional products are added in a parallel manner with decreased stages using a multi-stage carry propagation adder (MSCPA). The simulation demonstrated that the suggested DST-Radix-4 booth multiplier (DST-R4BM) resulted in higher performance in comparison to traditional multiplies in terms of area, delay, and power.
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Thèses sur le sujet "VEDIC MULTIPLIER"

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ANTONY, SAJI M. « DESIGN OF ENERGY EFFICIENT TRANSCEIVER BLOCKS FOR WIRELESS SENSOR NODES ». Thesis, DELHI TECHNOLOGICAL UNIVERSITY, 2020. http://dspace.dtu.ac.in:8080/jspui/handle/repository/18771.

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Sensor networks have been recognised as one of the most advanced technologies of the 21st century with vast practical applications. The life of a sensor network is mainly determined by its energy consumption. Commercially available sensor nodes are battery driven devices. As most sensor nodes are deployed widely scattered and in isolated areas, replacing battery is not an option. This dissertation focuses on extending the lifespan of sensor networks by reducing energy consumption in design and operation of sensor nodes. The study goes in depth to analyse the state of art technology to achieve energy efficiency in sensor nodes and identify scope for further research in this field. In the architecture of sensor nodes, multipliers are the main blocks for designing an energy efficient processor. Vedic Mathematics provides principles of high speed multiplication. The main reason for power dissipation in multiplier circuit is due to power dissipation of full adder circuit. Low power multipliers have been designed by using low power adders. Motivated by this, a high speed Vedic multiplier has been designed using multiplexer based adder. When compared with existing Vedic multipliers, proposed designs showed significant improvement in reduction of delay and energy consumption. Sensor nodes consume maximum power during data communication. So processing data locally at each node in a sensor network is important for minimizing power consumption. High processing speed and low area designs are in ever growing demand. In order to predict outcomes, based on previous inputs, ALU can be designed with neurons. Processing speed of ALU can be improved by replacing conventional multipliers with Vedic multipliers. This research work suggests implementation of high speed ALU using Vedic neurons. The analysis of the results shows that the proposed design leads to x reduction in the delay and reduction in LUT count (an indicator of area) of the ALU. Use of energy efficient power amplifiers is an essential requirement for sensor nodes, as power amplifiers are responsible for the main power consumption in the transceivers of sensor nodes. Again, wider band width is another important requirement for power amplifiers used in sensor transceivers especially in wireless visual sensor networks and wireless multimedia sensor networks. Reliability of a power amplifier can be increased by designing it at smaller supply voltage. This thesis suggests improvements in design of power amplifier in class E configuration, for transceivers in wireless sensor nodes. In order to achieve wider band width, cascade of common drain followed by common source in class E configuration has been designed; and for more reliable operation with higher efficiency, class E in double cascoded has been implemented. The proposed designs, when simulated in SPICE, higher efficiencies and band widths have been achieved. This research also explored to design a robust solar energy harvesting system to enhance life time of sensor nodes. Proposed solar energy supply system mainly consists of a solar panel, rechargeable battery and a control circuit. To obtain sufficient voltage to charge battery, electrical energy generated through panel is boosted by boost converter. Different sensor nodes are supplied with energy from this system. An inverter is also designed for AC applications. Experimental results show that this compact, self-sufficient system enables outdoor based wireless sensor network nodes to operate successfully for longer periods.
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Zanchi, Chiara. « Multiple preverbs in ancient Indo-European languages : a comparative study on Vedic, Homeric Greek, Old Church Slavic and Old Irish ». Doctoral thesis, Università degli studi di Bergamo, 2018. http://hdl.handle.net/10446/104992.

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This thesis describes and analyzes multiple preverb composites in a sample of ancient Indo-European languages, including Vedic (R̥g-Veda), Homeric Greek (Iliad, Odyssey), Old Church Slavic (Codices Marianus, Zographensis, Suprasliensis), and Old Irish (Milan and Priscian Glosses). While preverbs and single preverbation are two well-studied topics in Indo-European linguistics, this is not the case for multiple preverb composites, whereby two or more such morphemes attach onto the same simplex verb (e.g. Ved. adhí ní √dhā- ‘over-down-put’ →‘deposit for’, Hom.Gr. ep-ana-títhēmi ‘on-upward-put’ → ‘shut’, OCS prědъ-po-lagati ‘in front of-along-lay’ → ‘distribute to’, OIr. do·aithchuiredar ‘to-back-put’ → ‘return’). After an introduction describing the aims of this work and the sample texts, the present thesis opens with a theoretical chapter devoted to the tools necessary to study preverbs (Cognitive Grammar, grammaticalization theory, semantic roles, aspect and actionality), and with a general and typological overview of preverbs. The thesis provides thereafter quantitative data as for the number of multiple preverb composites, multiple preverb combinations, and verbal roots modified by multiple preverbs. Moreover, it thoroughly carries out philological, formal, semantic, and syntactic analyses on multiple preverb composites. On the one hand, the results of such analyses deliver to us two similar scenarios for Vedic and Homeric Greek, whereby multiple preverbs still retain much of their original functions and syntactic behavior. By contrast, the grammaticalization and lexicalization paths are far more advanced in Old Church Slavic and in Old Irish. On the other hand, the comparison also points out a number of similarities among the developments undergone by multiple preverbs in the sample languages. Specifically, a process of ‘recomposition’ (i.e. step by step accumulation) most likely lies behind the formation of multiple preverb composites in all languages. In addition, preverb ordering can be similarly explained, based on an account integrating different kinds of factors: (a) semantic solidarity holding between preverbs and verbs; (b) preverbs’ tendency to be specified by further event participants; (c) specific etymologies of specific preverbs; (d) calques/influence from other languages. By means of concrete examples, it is also shown that cognate or semantically similar preverbs tend to undergo similar semantic shifts. Crucially, by analyzing a relatively small array of multiple preverb composites and by integrating the findings achieved by previous works on different languages, this thesis also contributes to shedding light on the common reasons behind the well-known preverbs’ grammaticalization and lexicalization. These developments were understood as two distinct re-analyses, both triggered by the same pivotal factor, specifically, the mentioned semantic solidarity that came to make preverbs’ semantic contributions be felt as redundant. Preverbs were thus either reassigned salient pieces of information as markers of actionality (grammaticalization), or were reinterpreted as part of the verbal stem (lexicalization).
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ZANCHI, CHIARA. « Multiple preverbs in ancient Indo-European languages : a comparative study on Vedic, Homeric Greek, Old Church Slavic and Old Irish ». Doctoral thesis, Università degli studi di Pavia, 2018. https://hdl.handle.net/11571/1466705.

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This thesis describes and analyzes multiple preverb composites in a sample of ancient Indo-European languages, including Vedic (R̥g-Veda), Homeric Greek (Iliad, Odyssey), Old Church Slavic (Codices Marianus, Zographensis, Suprasliensis), and Old Irish (Milan and Priscian Glosses). While preverbs and single preverbation are two well-studied topics in Indo-European linguistics, this is not the case for multiple preverb composites, whereby two or more such morphemes attach onto the same simplex verb (e.g. Ved. adhí ní √dhā- ‘over-down-put’ →‘deposit for’, Hom.Gr. ep-ana-títhēmi ‘on-upward-put’ → ‘shut’, OCS prědъ-po-lagati ‘in front of-along-lay’ → ‘distribute to’, OIr. do·aithchuiredar ‘to-back-put’ → ‘return’). After an introduction describing the aims of this work and the sample texts, the present thesis opens with a theoretical chapter devoted to the tools necessary to study preverbs (Cognitive Grammar, grammaticalization theory, semantic roles, aspect and actionality), and with a general and typological overview of preverbs. The thesis provides thereafter quantitative data as for the number of multiple preverb composites, multiple preverb combinations, and verbal roots modified by multiple preverbs. Moreover, it thoroughly carries out philological, formal, semantic, and syntactic analyses on multiple preverb composites. On the one hand, the results of such analyses deliver to us two similar scenarios for Vedic and Homeric Greek, whereby multiple preverbs still retain much of their original functions and syntactic behavior. By contrast, the grammaticalization and lexicalization paths are far more advanced in Old Church Slavic and in Old Irish. On the other hand, the comparison also points out a number of similarities among the developments undergone by multiple preverbs in the sample languages. Specifically, a process of ‘recomposition’ (i.e. step by step accumulation) most likely lies behind the formation of multiple preverb composites in all languages. In addition, preverb ordering can be similarly explained, based on an account integrating different kinds of factors: (a) semantic solidarity holding between preverbs and verbs; (b) preverbs’ tendency to be specified by further event participants; (c) specific etymologies of specific preverbs; (d) calques/influence from other languages. By means of concrete examples, it is also shown that cognate or semantically similar preverbs tend to undergo similar semantic shifts. Crucially, by analyzing a relatively small array of multiple preverb composites and by integrating the findings achieved by previous works on different languages, this thesis also contributes to shedding light on the common reasons behind the well-known preverbs’ grammaticalization and lexicalization. These developments were understood as two distinct re-analyses, both triggered by the same pivotal factor, specifically, the mentioned semantic solidarity that came to make preverbs’ semantic contributions be felt as redundant. Preverbs were thus either reassigned salient pieces of information as markers of actionality (grammaticalization), or were reinterpreted as part of the verbal stem (lexicalization).
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Jiang, CunHao, et 蔣存皓. « An Efficient Vedic Multiplier Design ». Thesis, 2017. http://ndltd.ncl.edu.tw/handle/65n6nm.

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碩士
國立臺北科技大學
電子工程系研究所
105
Multiplier is one of core operations of the digital signal processing and microprocessor. the multiplier in the digital circuit needs to increase the speed, decrease the area and consume less memory. So an efficient multiplier is very important in nowadays. This paper is about designing traditional Vedic multiplier through the Urdhva-Tiryagbhyam sutra. Changing the adder from the traditional Vedic multiplier which designed with the sutra, it can become two kinds of efficient Vedic multipliers. After designing 4-bit, 8-bit, 16-bit, 32-bit traditional Vedic multiplier and two kinds of efficient Vedic multipliers, their time delay and areas are analyzed through the Quartus II. According to the results of the experiment, time delay of the original efficient Vedic multiplier decreases 5.88％ but the area increases 37.298%. Besides, time delay of the resolved efficient Vedic multiplier decreases 7.4% but the area increases 21.6%. If the multiplier needs to be faster on work afterwards, 4-bit and 16-bit original efficient Vedic multiplier and 8-bit, 32-bit and 64-bit resolved efficient Vedic multiplier are suggested. If the multiplier needs to be smaller, traditional Vedic multiplier is suggested. If both delay time and chip area cost are considered comprehensively, 8-bit or 64-bit resolved efficient Vedic multiplier are suggested.
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RUHELA, DIKSHA. « DESIGN AND IMPLEMENTATION OF EFFICIENT REVERSIBLE MULTIPLIER USING VEDIC MATHEMATICS TOOL ». Thesis, 2016. http://dspace.dtu.ac.in:8080/jspui/handle/repository/14759.

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Multiplier is one of the important block in almost all the arithmetic logic units. These multipliers are mostly used in the fields of the Digital Signal Processing (DSP), Fast Fourier Transform, convolution, filtering and microprocessor applications. A system's performance is generally determined by the performance of the multiplier, because the multiplier is generally the slowest element in the system. Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the multiplier is a major design issue. Since multiplier is the main component and hence a high speed and area efficient multiplier can be achieve by using Vedic mathematics. In this work we have implemented the Vedic multiplier using Chinese Abacus Adder with and without using Reversible logic gates. Reversible logic is one of the promising fields for future low power design technologies. Since one of the requirements of all DSP processors and other embedded devices is to minimize power dissipation multipliers with high speed and lower dissipations are critical. This work is devoted to the design of a high speed Vedic multiplier using reversible logic gates. For arithmetic multiplication, various Vedic multiplication techniques like Urdhva Tiryakbhyam, Nikhilam and Anurupye have been thoroughly discussed. It has been found that Urdhva Tiryakbhyam Sutra is the most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large. Further, the Verilog HDL coding of Urdhva Tiryakbhyam Sutra for 32x32 bits and 64x64 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool on Spartan 3E kit have been done. The synthesis results show that the computation time for calculating the product of 4x4 multiplication is less as compared with other conventional multipliers.
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KUMAR, SHIVAM. « DESIGN AND IMPLEMENTATION OF EFFICIENT MATRIX MULTIPLICATION USING VARIOUS ARCHITECTURE ». Thesis, 2023. http://dspace.dtu.ac.in:8080/jspui/handle/repository/19896.

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The semiconductor industry plays a crucial role in the design and manufacture of integrated circuits (ICs) used in a wide range of electronic devices. VLSI technology allows for the integration of millions of transistors onto a single chip, enabling the creation of highly complex and powerful devices such as computers, smart phones, and other electronic devices. The VLSI industry is a key driver of innovation in the electronics industry and has played a major role in the development of new technologies and the proliferation of electronic devices in our daily lives. Consequently, area, speed, and power play a critical role in any circuit design .A circuit must be created to meet the present trend's requirements with minimal space and minimal time limitations. Matrix multiplication is of significant importance in various fields and applications. Matrix multiplication plays a fundamental role in linear algebra, solving system of linear equations, data analysis and machine learning, computer graphics and computer vision, network theory and graph algorithm, etc. This thesis gives a thorough investigation into how the Wallace tree multiplier, Vedic multiplier, and parallel prefix adders might be combined to enhance matrix multiplication performance. These techniques contribute to achieving significant speed improvements, reduced and optimized resource utilization. The findings of this study add to understanding of digital circuit design by offering suggestions for choosing and incorporating effective multiplication methods for matrix operations. The thesis provides helpful advice to researchers and designers of digital circuits by explaining the trade-offs, benefits, and drawbacks of the integrated architecture. Firstly, Ripple Carry adders, Kogge Stone adders, and Han Carlson adders have been designed and analyzed. After that, the Wallace tree multiplier and Vedic multiplier are designed using these adders. By combining both multiplier and adder, matrix multiplication designs, analyses the performance data, and interprets the results obtained from the experiments. Using the ISE Design Suite tools in Verilog, all circuits are created and simulations are run. The XC6SLX150T are the devices used for synthesis.
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Livres sur le sujet "VEDIC MULTIPLIER"

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Design of a High Speed Multiplier (Ancient Vedic Mathematics Approach) . Innovative Research Publications, 2013.

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Geslani, Marko. Rites of the God-King. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780190862886.001.0001.

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Most accounts of Hinduism posit a radical difference between the aniconic fire sacrifice (yajña) and temple-based image worship (pūjā). The historical distinction between ancient Vedism and medieval Hinduism is often premised on this basic ritual opposition. Through an exacting study of ritual manuals, Rites of the God-King offers an alternative account of the formation of mainstream Hindu ritual through the history of śānti, or “appeasement,” a form of aspersion or bathing, developed in order to counteract inauspicious omens. This ritual, which originated at the nexus of the fourth and somewhat marginal Veda (Atharvaveda) and the emergent tradition of astronomy-astrology (Jyotiḥśāstra), would come to have far-reaching consequences on the ideal ritual life of the king in early medieval Brahmanical society—and on the ideal ritual life of images. The mantric substitutions involved in this history helped to produce a politicized ritual culture that could encompass both traditional Vedic and newer Hindu practices and performers. From astrological appeasement to gifting, coronation, and image worship, the author chronicles the multiple lives and afterlives of a single ritual mode, disclosing the always inventive work of priesthood to imagine and enrich royal power. Along the way, he reveals the surprising role of astrologers in Hindu history, elaborates concepts of sin and misfortune, and forges new connections between medieval texts and modern practice. Detailing forms of ritual that were dispersed widely across Asia, he concludes with a reflection on the nature of orthopraxy, ritual change, and the problem of presence in the Hindu tradition.
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Chapitres de livres sur le sujet "VEDIC MULTIPLIER"

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Sudhamsu Preetham, J. V. R., Perli Nethra, D. Chandrasekhar, Mathangi Akhila, N. Arun Vignesh et Asisa Kumar Panigrahy. « Vedic Multiplier for High-Speed Applications ». Dans Communication, Software and Networks, 349–56. Singapore : Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-4990-6_31.

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Pavan Kumar, N., et K. Shashi Raj. « Delay Analysis of Hybrid Vedic Multiplier ». Dans Advances in Intelligent Systems and Computing, 91–103. Singapore : Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7330-6_8.

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Udaya Kumar, N., K. Bala Sindhuri, U. Subbalakshmi et P. Kiranmayi. « Performance Evaluation of Vedic Multiplier Using Multiplexer-Based Adders ». Dans Lecture Notes in Electrical Engineering, 349–56. Singapore : Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1906-8_36.

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Lachireddy, Dhanunjay, et S. R. Ramesh. « Power and Delay Efficient ALU Using Vedic Multiplier ». Dans Lecture Notes in Electrical Engineering, 703–11. Singapore : Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-5558-9_61.

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Kumari, Sabita, et Kanchan Sharma. « Implementation of Nobel Vedic Multiplier Using Arithmetic Adder ». Dans Data Intelligence and Cognitive Informatics, 209–16. Singapore : Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-6460-1_15.

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Awade, Anirudh, Prachi Jain, S. Hemavathy et V. S. Kanchana Bhaaskaran. « Design of Vedic Multiplier Using Reversible Logic Gates ». Dans Lecture Notes in Electrical Engineering, 435–48. Singapore : Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-9019-1_38.

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Srimani, Supriyo, Diptendu Kumar Kundu, Saradindu Panda et B. Maji. « Implementation of High Performance Vedic Multiplier and Design of DSP Operations Using Vedic Sutra ». Dans Computational Advancement in Communication Circuits and Systems, 443–49. New Delhi : Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2274-3_49.

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Thakare, Laxman P., A. Y. Deshmukh et Gopichand D. Khandale. « VHDL Implementation of Complex Number Multiplier Using Vedic Mathematics ». Dans Proceedings of International Conference on Soft Computing Techniques and Engineering Application, 403–10. New Delhi : Springer India, 2013. http://dx.doi.org/10.1007/978-81-322-1695-7_46.

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Khan, Angshuman, et Rupayan Das. « Novel Approach of Multiplier Design Using Ancient Vedic Mathematics ». Dans Advances in Intelligent Systems and Computing, 265–72. New Delhi : Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2247-7_28.

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Giridaran, S., Prithvik Adithya Ravindran, G. Duruvan Raj et M. Janarthanan. « Design of Low Power Vedic Multiplier Using Adiabatic Techniques ». Dans Cognitive Informatics and Soft Computing, 403–15. Singapore : Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-8763-1_33.

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Actes de conférences sur le sujet "VEDIC MULTIPLIER"

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Kahar, Dravik KishorBhai, et Harsh Mehta. « High speed vedic multiplier used vedic mathematics ». Dans 2017 International Conference on Intelligent Computing and Control Systems (ICICCS). IEEE, 2017. http://dx.doi.org/10.1109/iccons.2017.8250742.

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G, Shanthi K., Sandhiya G, Abinaya K, Akula Sangeetha, Aruna T et Aswini R. « Performance Analysis of Vedic Multiplier and Modified Vedic Multiplier in Direct Digital Synthesizer ». Dans 2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC). IEEE, 2022. http://dx.doi.org/10.1109/icesc54411.2022.9885340.

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N., Noorja, et Sujithamol S. « Convolution Using Modified Vedic Multiplier ». Dans Proceedings of the Advances in Technology, Engineering and Computing A Multinational Colloquium - 2017. Singapore : Research Publishing Services, 2017. http://dx.doi.org/10.3850/978-981-11-0744-3_c66.

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Kodali, Ravi Kishore, C. Sivakumar, Vishal Jain et Lakshmi Boppana. « Low-power modified Vedic multiplier ». Dans 2015 International Conference on Control Communication & Computing India (ICCC). IEEE, 2015. http://dx.doi.org/10.1109/iccc.2015.7432939.

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Pranav, K., et P. Pramod. « Pipelined convolution using Vedic multiplier ». Dans 2015 IEEE Recent Advances in Intelligent Computational Systems (RAICS). IEEE, 2015. http://dx.doi.org/10.1109/raics.2015.7488384.

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Ram, G. Challa, Y. Rama Lakshmanna, D. Sudha Rani et K. Bala Sindhuri. « Area efficient modified vedic multiplier ». Dans 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT). IEEE, 2016. http://dx.doi.org/10.1109/iccpct.2016.7530294.

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Patel, Chiranjit R., Vivek Urankar, Vivek B. A et V. Keshav Bharadwaj. « Vedic Multiplier in 45nm Technology ». Dans 2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC). IEEE, 2020. http://dx.doi.org/10.1109/iccmc48092.2020.iccmc-0004.

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Harish Babu N, Satish Reddy N, Bhumarapu Devendra et Jayakrishanan P. « Pipelined architecture for vedic multiplier ». Dans 2014 International Conference on Advances in Electrical Engineering (ICAEE). IEEE, 2014. http://dx.doi.org/10.1109/icaee.2014.6838437.

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Pichhode, Khushboo, Mukesh D. Patil, Divya Shah et B. Chaurasiya Rohit. « FPGA implementation of efficient vedic multiplier ». Dans 2015 International Conference on Information Processing (ICIP). IEEE, 2015. http://dx.doi.org/10.1109/infop.2015.7489448.

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Bansal, Malti, et Jasmeet Singh. « Comparative Analysis of 4-bit CMOS Vedic Multiplier and GDI Vedic Multiplier using 18nm FinFET Technology ». Dans 2020 International Conference on Smart Electronics and Communication (ICOSEC). IEEE, 2020. http://dx.doi.org/10.1109/icosec49089.2020.9215317.

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