Bibliographies thématiques / Turbo-product-code decoder

Littérature scientifique sur le sujet « Turbo-product-code decoder »

Auteur : Grafiati
Publié le 14 mars 2023

Créez une référence correcte selon les styles APA, MLA, Chicago, Harvard et plusieurs autres

Choisissez une source :

Sommaire

Consultez les listes thématiques d’articles de revues, de livres, de thèses, de rapports de conférences et d’autres sources académiques sur le sujet « Turbo-product-code decoder ».

À côté de chaque source dans la liste de références il y a un bouton « Ajouter à la bibliographie ». Cliquez sur ce bouton, et nous générerons automatiquement la référence bibliographique pour la source choisie selon votre style de citation préféré : APA, MLA, Harvard, Vancouver, Chicago, etc.

Vous pouvez aussi télécharger le texte intégral de la publication scolaire au format pdf et consulter son résumé en ligne lorsque ces informations sont inclues dans les métadonnées.

Articles de revues sur le sujet "Turbo-product-code decoder"

1

Boudaoud, A., M. El Haroussi et E. Abdelmounim. « VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes ». International Journal of Electrical and Computer Engineering (IJECE) 7, no 4 (1 août 2017) : 1824. http://dx.doi.org/10.11591/ijece.v7i4.pp1824-1832.

Texte intégral
Résumé :
This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital transmission chains. For example, for the Turbo decoder based on the product code DSC (21.11)² with a quantization of 5 bits and for one complete iteration, the results show the possibility of integration of our entire turbo decoder on a single chip, with lower latency at 0.23 microseconds and data rate greater than 500 Mb/s.
Styles APA, Harvard, Vancouver, ISO, etc.
2

Zhou, Li, Hengzhu Liu et Botao Zhang. « Flexible and high-efficiency turbo product code decoder design ». IEICE Electronics Express 9, no 12 (2012) : 1044–50. http://dx.doi.org/10.1587/elex.9.1044.

Texte intégral
Styles APA, Harvard, Vancouver, ISO, etc.
3

Dong, Jie, Yong Li, Rui Liu, Taolin Guo et Francis C. M. Lau. « Efficient Decoder for Turbo Product Codes Based on Quadratic Residue Codes ». Electronics 11, no 21 (3 novembre 2022) : 3598. http://dx.doi.org/10.3390/electronics11213598.

Texte intégral
Résumé :
In this letter, we study turbo product codes with quadratic residue codes (called QR-TPCs) as the component codes. We propose an efficient decoder based on Chase-II algorithm with two convergence conditions for the iterative decoding of QR-TPCs. For each row and column, the Chase-II decoder will stop immediately when one of the conditions is met. The simulation results show that the proposed algorithm has a lower computational complexity compared with existing decoding methods. Moreover, a comparison with 5G low-density parity-check codes shows that the proposed turbo product codes have better performance for short code lengths.
Styles APA, Harvard, Vancouver, ISO, etc.
4

Ghaith, Alaa. « Improvement Of Block Product Turbo Coding By Using A New Concept Of Soft Hamming Decoder ». European Scientific Journal, ESJ 12, no 18 (29 juin 2016) : 167. http://dx.doi.org/10.19044/esj.2016.v12n18p167.

Texte intégral
Résumé :
The block product turbo code (BPTC) is classified as one of block turbo code concatenation forms. The Hamming code can detect two-bit error and correct one-bit error. The BPTC uses two Hamming codes for "column" coding and "row" coding, it has improved the Hamming code correcting only one error. In addition, the BPTC carries out block interleaving coding for disorganizing the transmission sequence before transmission, so as to avoid burst errors when the signal meets multi-path channel in the channel. This paper will discuss the decoding mechanism of the BPTC and analyze the efficiency of using a soft decoding algorithm in the decoding process. The soft Hamming Decoder is based on error patterns which belong to the same syndrome. It is shown that it is sufficient to investigate error patterns with one and two errors to gain up to 1.2 dB compared to hard decision decoding. Here, we will consider also the error patterns with three errors which belong to the determined syndrome, which increases the gain and improves the quality of the soft-output due to the increased number of comparisons with valid code words, in despite that, it will increase the complexity of the decoding process. The system is based on two Hamming block channel code combinations, which can be similar or different, a block interleaving to construct a BPSK modulation and BPTC coding system in the concept of feedback encoding in turbo code over an AWGN channel. To observe its coding improvement, we present the simulation results for the soft decoding of the BPTC codes of a code word length from 49 bits (using two (7,4) codes) up to 1440 bits (using two (127,120) codes).
Styles APA, Harvard, Vancouver, ISO, etc.
5

Leroux, Camille, Christophe Jego, Patrick Adde, Deepak Gupta et Michel Jezequel. « Turbo Product Code Decoder Without Interleaving Resource : From Parallelism Exploration to High Efficiency Architecture ». Journal of Signal Processing Systems 64, no 1 (14 avril 2010) : 17–29. http://dx.doi.org/10.1007/s11265-010-0478-5.

Texte intégral
Styles APA, Harvard, Vancouver, ISO, etc.
6

He, Yejun, Francis C. M. Lau et Chi K. Tse. « Study of bifurcation behavior of two-dimensional turbo product code decoders ». Chaos, Solitons & ; Fractals 36, no 2 (avril 2008) : 500–511. http://dx.doi.org/10.1016/j.chaos.2006.06.101.

Texte intégral
Styles APA, Harvard, Vancouver, ISO, etc.
7

Le Bidan, Raphaël, Camille Leroux, Christophe Jego, Patrick Adde et Ramesh Pyndiah. « Reed-Solomon Turbo Product Codes for Optical Communications : From Code Optimization to Decoder Design ». EURASIP Journal on Wireless Communications and Networking 2008, no 1 (8 mai 2008). http://dx.doi.org/10.1155/2008/658042.

Texte intégral
Styles APA, Harvard, Vancouver, ISO, etc.

Thèses sur le sujet "Turbo-product-code decoder"

1

Bade, Peter. « A 1Mbps 0.18μm CMOS Soft-output Decoder for Product Turbo Codes ». Thesis, 2009. http://hdl.handle.net/1807/17493.

Texte intégral
Résumé :
A product turbo code (PTC) decoder application specific integrated circuit (ASIC) is designed in 0.18μm 1P6M CMOS with embedded SRAM. From simulation, an operating frequency of 73.1 MHz at typical conditions is obtained, yielding a throughput of 3.8 Mbps with 4 decoding iterations, while consuming 103.4 mW. The total area is 5.13 mm2. Assuming the ASIC would be used as a hard macro, the area could be reduced to 1.7 mm2. The ASIC was tested at 20 MHz under typical conditions, which resulted in a throughput of 1.0 Mbps at 1.8V supply while consuming 36.6 mW. By making a slight modification, this design can be easily scaled to support IEEE 802.16d WiMAX. Allow for this, and moving to a 45nm process an estimated throughput of 9.44 Mbps with 4 iterations can be obtained. Total macro area would be approximately 0.11 mm2.
Styles APA, Harvard, Vancouver, ISO, etc.

Chapitres de livres sur le sujet "Turbo-product-code decoder"

1

Nair, Gana C., B. Yamuna, Karthi Balasubramanian et Deepak Mishra. « Hardware Design of a Turbo Product Code Decoder ». Dans Lecture Notes in Electrical Engineering, 249–55. Singapore : Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-4866-0_31.

Texte intégral
Styles APA, Harvard, Vancouver, ISO, etc.
2

Shivanna, Gautham, B. Yamuna, Karthi Balasubramanian et Deepak Mishra. « Design of High-Speed Turbo Product Code Decoder ». Dans Lecture Notes in Electrical Engineering, 175–86. Singapore : Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-6977-1_15.

Texte intégral
Styles APA, Harvard, Vancouver, ISO, etc.
3

Khavya, S., Karthi Balasubramanian, B. Yamuna et Deepak Mishra. « Design and Analysis of a Secure Coded Communication System Using Chaotic Encryption and Turbo Product Code Decoder ». Dans Lecture Notes in Electrical Engineering, 657–66. Singapore : Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-6977-1_48.

Texte intégral
Styles APA, Harvard, Vancouver, ISO, etc.

Actes de conférences sur le sujet "Turbo-product-code decoder"

1

Wu, Xiaoxiao, Yejun He et Guangxi Zhu. « Performance of Improved Three-Dimensional Turbo Product Code Decoder ». Dans 2007 IEEE International Conference on Integration Technology. IEEE, 2007. http://dx.doi.org/10.1109/icitechnology.2007.4290380.

Texte intégral
Styles APA, Harvard, Vancouver, ISO, etc.
2

Kuang, Wen, Renzhong Zhao et Zhu Juan. « FPGA implementation of a modified turbo product code decoder ». Dans 2017 IEEE 9th International Conference on Communication Software and Networks (ICCSN). IEEE, 2017. http://dx.doi.org/10.1109/iccsn.2017.8230081.

Texte intégral
Styles APA, Harvard, Vancouver, ISO, etc.
3

Leroux, Camille, Christophe Jego, Patrick Adde, Michel Jezequel et Deepak Gupta. « A highly parallel Turbo Product Code decoder without interleaving resource ». Dans 2008 IEEE Workshop on Signal Processing Systems (SiPS). IEEE, 2008. http://dx.doi.org/10.1109/sips.2008.4671728.

Texte intégral
Styles APA, Harvard, Vancouver, ISO, etc.
4

Wang, Yaqi, Jun Lin et Zhongfeng Wang. « A 100 Gbps Turbo Product Code Decoder for Optical Communications ». Dans 2019 IEEE 5th International Conference on Computer and Communications (ICCC). IEEE, 2019. http://dx.doi.org/10.1109/iccc47050.2019.9064204.

Texte intégral
Styles APA, Harvard, Vancouver, ISO, etc.
5

Kishore, J. Hari, B. Yamuna et Karthi Balasubramanian. « Design of a Fast Chase Algorithm based High Speed Turbo Product Code Decoder ». Dans 2021 10th International Conference on Advances in Computing and Communications (ICACC). IEEE, 2021. http://dx.doi.org/10.1109/icacc-202152719.2021.9708201.

Texte intégral
Styles APA, Harvard, Vancouver, ISO, etc.
6

Nageen, Nitin, Subhashini et Vikas Bhatia. « An Efficient FPGA implementation of Turbo Product Code decoder with single and double error correction ». Dans 2020 National Conference on Communications (NCC). IEEE, 2020. http://dx.doi.org/10.1109/ncc48643.2020.9055995.

Texte intégral
Styles APA, Harvard, Vancouver, ISO, etc.
Nous offrons des réductions sur tous les plans premium pour les auteurs dont les œuvres sont incluses dans des sélections littéraires thématiques. Contactez-nous pour obtenir un code promo unique!

Vers la bibliographie