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Littérature scientifique sur le sujet « Threshold circuits »

Auteur : Grafiati
Publié le 9 mars 2023
Mis à jour le 10 mars 2023

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Articles de revues sur le sujet "Threshold circuits"

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Uchizawa, Kei, Rodney Douglas et Wolfgang Maass. « On the Computational Power of Threshold Circuits with Sparse Activity ». Neural Computation 18, no 12 (décembre 2006) : 2994–3008. http://dx.doi.org/10.1162/neco.2006.18.12.2994.

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Circuits composed of threshold gates (McCulloch-Pitts neurons, or perceptrons) are simplified models of neural circuits with the advantage that they are theoretically more tractable than their biological counterparts. However, when such threshold circuits are designed to perform a specific computational task, they usually differ in one important respect from computations in the brain: they require very high activity. On average every second threshold gate fires (sets a 1 as output) during a computation. By contrast, the activity of neurons in the brain is much sparser, with only about 1% of neurons firing. This mismatch between threshold and neuronal circuits is due to the particular complexity measures (circuit size and circuit depth) that have been minimized in previous threshold circuit constructions. In this letter, we investigate a new complexity measure for threshold circuits, energy complexity, whose minimization yields computations with sparse activity. We prove that all computations by threshold circuits of polynomial size with entropy O(log n) can be restructured so that their energy complexity is reduced to a level near the entropy of circuit states. This entropy of circuit states is a novel circuit complexity measure, which is of interest not only in the context of threshold circuits but for circuit complexity in general. As an example of how this measure can be applied, we show that any polynomial size threshold circuit with entropy O(log n) can be simulated by a polynomial size threshold circuit of depth 3. Our results demonstrate that the structure of circuits that result from a minimization of their energy complexity is quite different from the structure that results from a minimization of previously considered complexity measures, and potentially closer to the structure of neural circuits in the nervous system. In particular, different pathways are activated in these circuits for different classes of inputs. This letter shows that such circuits with sparse activity have a surprisingly large computational power.
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Goldmann, Mikael, et Marek Karpinski. « Simulating Threshold Circuits by Majority Circuits ». SIAM Journal on Computing 27, no 1 (février 1998) : 230–46. http://dx.doi.org/10.1137/s0097539794274519.

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LAPPAS, G., R. J. FRANK et A. A. ALBRECHT. « A COMPUTATIONAL STUDY ON CIRCUIT SIZE VERSUS CIRCUIT DEPTH ». International Journal on Artificial Intelligence Tools 15, no 02 (avril 2006) : 143–61. http://dx.doi.org/10.1142/s0218213006002606.

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We investigate the circuit complexity of classification problems in a machine learning setting, i.e. we attempt to find some rule that allows us to calculate a priori the number of threshold gates that is sufficient to achieve a small error rate after training a circuit on sample data [Formula: see text]. The particular threshold gates are computed by a combination of the classical perceptron algorithm with a specific type of stochastic local search. The circuit complexity is analysed for depth-two and depth-four threshold circuits, where we introduce a novel approach to compute depth-four circuits. For the problems from the UCI Machine Learning Repository we selected and investigated, we obtain approximately the same size of depth-two and depth-four circuits for the best classification rates on test samples, where the rates differ only marginally for the two types of circuits. Based on classical results from threshold circuit theory and our experimental observations on problems that are not linearly separable, we suggest an upper bound of [Formula: see text] threshold gates as sufficient for a small error rate, where [Formula: see text].
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Hansen, Kristoffer Arnsfelt, et Vladimir V. Podolskii. « Polynomial threshold functions and Boolean threshold circuits ». Information and Computation 240 (février 2015) : 56–73. http://dx.doi.org/10.1016/j.ic.2014.09.008.

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Mahajan, Meena. « Depth-2 Threshold Circuits ». Resonance 24, no 3 (mars 2019) : 371–80. http://dx.doi.org/10.1007/s12045-019-0786-4.

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WANG, YU, HUAZHONG YANG et HUI WANG. « SIGNAL-PATH-LEVEL DUAL-Vt ASSIGNMENT FOR LEAKAGE POWER REDUCTION ». Journal of Circuits, Systems and Computers 15, no 02 (avril 2006) : 197–216. http://dx.doi.org/10.1142/s021812660600299x.

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Along with the fast development of dual-threshold voltage (dual-Vt) and multi-threshold technology, it is possible to use them to reduce static power in low-voltage high-performance circuits. In this paper, we propose a new method to realize CMOS digital circuits that are implemented with dual-Vt technology. We first present a new signal-path-level circuit model which effectively deals with the fact that there can be two threshold voltages assigned to a single gate. In order to assign proper threshold voltage to all the signal-paths in the circuit, our new algorithms introduce the concept of subcircuit extraction and include the hierarchy algorithms which are effective and fast. Experimental results show that our algorithms produce a significant reduction for the ISCAS85 benchmark circuits.
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Thakral, Bindu, Arti Vaish et Rama Koteswara Rao Alla. « Design of Squarer Circuit in Sub-threshold Mode ». International Journal of Engineering & ; Technology 7, no 2.11 (3 avril 2018) : 38. http://dx.doi.org/10.14419/ijet.v7i2.11.11004.

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Historically, analog designs have been assumed as a voltage mode based signal processing. However, the necessity of high speed circuits operating at reduced supply voltage has lead to a development of new circuit topology referred as current-mode designs. For low power low voltage designs the applications using translinear principle based circuits has become an area of research and interest. It has wide application in nonlinear signal processing and to build basic active elements. Mode of MOS transistor used in analog circuit realization of is important parameter deciding the performance of the circuit. In this paper, a squarer circuit is proposed based on sub threshold-mode MOS transistors exhibiting the exponential current-voltage characteristic. The simulations have been performed on model files of TSMC 0.18 micrometer technology with the help of ELDO Simulator.
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SUZUKI, AKIRA, KEI UCHIZAWA et XIAO ZHOU. « ENERGY-EFFICIENT THRESHOLD CIRCUITS COMPUTING MOD FUNCTIONS ». International Journal of Foundations of Computer Science 24, no 01 (janvier 2013) : 15–29. http://dx.doi.org/10.1142/s0129054113400029.

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We prove that the modulus function MODm of n variables can be computed by a threshold circuit C of energy e and size s = O(e(n/m)1/(e − 1)) for any integer e ≥ 2, where the energy e is defined to be the maximum number of gates outputting "1" over all inputs to C, and the size s to be the number of gates in C. Our upper bound on the size s almost matches the known lower bound s = Ω(e(n/m)1/e). We also consider an extreme case where threshold circuits have energy 1, and prove that such circuits need at least 2(n − m)/2 gates to compute MODm of n variables.
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Ghavami, Behnam. « Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits ». COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 37, no 3 (8 mai 2018) : 1189–203. http://dx.doi.org/10.1108/compel-03-2016-0118.

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Purpose Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits. Design/methodology/approach In this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment. Findings Experimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits. Originality/value The proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.
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Heo, Jae, Kyung-Tae Kim, Seok-Gyu Ban, Yoon-Jeong Kim, Daesik Kim, Taehoon Kim, Yongtaek Hong, In-Soo Kim et Sung Park. « Stable Logic Operation of Fiber-Based Single-Walled Carbon Nanotube Transistor Circuits Toward Thread-Like CMOS Circuitry ». Materials 11, no 10 (1 octobre 2018) : 1878. http://dx.doi.org/10.3390/ma11101878.

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A fiber-based single-walled carbon nanotube (SWCNT) thin-film-transistor (TFT) has been proposed. We designed complementary SWCNT TFT circuit based on SPICE simulations, with device parameters extracted from the fabricated fiber-based SWCNT TFTs, such as threshold voltage, contact resistance, and off-/gate-leakage current. We fabricated the SWCNTs CMOS inverter circuits using the selective passivation and n-doping processes on a fiber substrate. By comparing the simulation and experimental results, we could enhance the circuit’s performance by tuning the threshold voltage between p-type and n-type TFTs, reducing the source/drain contact resistance and off current level, and maintaining a low output capacitance of the TFTs. Importantly, it was found that the voltage gain, output swing range, and frequency response of the fiber-based inverter circuits can be dramatically improved.
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Thèses sur le sujet "Threshold circuits"

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LEPORATI, ALBERTO OTTAVIO. « Threshold Circuits and Quantum Gates ». Doctoral thesis, Università degli Studi di Milano, 2003. http://hdl.handle.net/10281/43616.

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Maciel, Alexis. « Threshold circuits of small majority-depth ». Thesis, McGill University, 1995. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=28830.

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We investigate the complexity of computations with constant-depth threshold circuits. Such circuits are composed of gates that determine if the sum of their inputs is greater than a certain threshold. When restricted to polynomial size, these circuits compute exactly the functions in the class TC$ sp0$.
These circuits are usually studied by measuring their efficiency in terms of their total depth. Using this point of view, the best division and iterated multiplication circuits have depth three and four, respectively.
In this thesis, we propose a different approach. Since threshold gates are much more powerful than AND-OR gates, we allow the explicit use of AND-OR gates and consider the main measure of complexity to be the majority-depth of the circuit, i.e. the maximum number of threshold gates on any path in the circuit. Using this approach, we obtain division and iterated multiplication circuits of total depth four and five, but of majority-depth two and three.
The technique used is called Chinese remaindering. We present this technique as a general tool for computing functions with integer values and use it to obtain depth-four threshold circuits of majority-depth two for other arithmetic problems such as the logarithm and power series approximation. We also consider the iterated multiplication problem for integers modulo q and for finite fields.
The notion of majority-depth naturally leads to a hierarchy of subclasses of TC$ sp0$. We investigate this hierarchy and show that it is closely related to the usual depth hierarchy.
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PALANISWAMY, ASHOK KUMAR. « SYNTHESIS AND TESTING OF THRESHOLD LOGIC CIRCUITS ». OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/963.

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Threshold logic gates gaining more importance in recent years due to the significant development in the switching devices. This renewed the interest in synthesis and testing of circuits with threshold logic gates. Two important synthesis considerations of threshold logic circuits are addressed namely, threshold logic function identification and reducing the total number of threshold logic gates required to represent the given boolean circuit description. A fast method to identify the given Boolean function as a threshold logic function with weight assignment is introduced. It characterizes the threshold logic function based on the modified chows parameters which results in drastic reduction in time and complexity. Experiment results shown that the proposed method is at least 10 times faster for each input and around 20 times faster for 7 and 8 input, when comparing with the algorithmic based methods. Similarly, it is 100 times faster for 8 input, when comparing with asummable method. Existing threshold logic synthesis methods decompose the larger input functions into smaller input functions and perform synthesis for them. This results in increase in the number of threshold logic gates required to represent the given circuit description. The proposed implicit synthesis methods increase the size of the functions that can be handled by the synthesis algorithm, thus the number of threshold logic gates required to implement very large input function decreases. Experiment results shown that the reduction in the TLG count is 24% in the best case and 18% on average. An automatic test pattern generation approach for transition faults on a circuit consisting of current mode threshold logic gates is introduced. The generated pattern for each fault excites the maximum propagation delay at the gate (the fault site). This is a high quality ATPG. Since current mode threshold logic gate circuits are pipelined and the combinational depth at each pipeline stage is practically one. It is experimentally shown that the fault coverage for all benchmark circuits is approximately 97%. It is also shown that the proposed method is time efficient.
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Caicedo, Jhon Alexander Gomez. « CMOS low-power threshold voltage monitors circuits and applications ». reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2016. http://hdl.handle.net/10183/144080.

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Um monitor de tensão de limiar (VT0) é um circuito que, idealmente, entrega o valor do VT0 como uma tensão na saída, para uma determinada faixa de temperatura, sem a necessidade de polarização externa, configurações paramétricas, ajuste de curvas ou qualquer cálculo subsequente. Estes circuitos podem ser usados em sensores de temperatura, referências de tensão e corrente, dosímetros de radiação e outras aplicações, uma vez que a dependência do VT0 nas condições de operação é um aspecto bem modelado. Além disso, estes circuitos podem ser utilizados para monitoramento de processos de fabricação e para compensação da variabilidade do processo, uma vez que o VT0 é um parâmetro chave para o comportamento do transistor e sua modelagem. Nesta tese, são apresentadas três novas topologias de circuitos, duas são monitores de VT0 NMOS e a terceira é um monitor de VT0 PMOS. As três estruturas são topologias de circuito auto-polarizadas que não utilizam resistências, e apresentam alta rejeição a variações na alimentação, baixa sensibilidade de Linea, e permitem a extração direta da tensão de limiar para grandes intervalos de temperatura e de tensão de alimentação, com pequeno erro. Sua metodologia de projeto é baseada no modelo unificado controlado por corrente (UICM), um modelo MOSFET que é contínuo, desde o nível de inversão fraca a forte e para as regiões de operação de triodo e saturação. Os circuitos ocupam uma pequena área de silício, consomem apenas dezenas de nanowatts, e podem ser implementados em qualquer processo padrão CMOS digital, uma vez que só utilizam transistores MOS (não precisa de nenhum resistor). Os monitores de VT0 são utilizados em diferentes aplicações, a fim de investigar a sua funcionalidade e comportamento como parte de um sistema. As aplicações variam de uma tensão de referência, que apresenta um desempenho comparável ao estado da arte, para uma configuração que permite obter uma menor variabilidade com processo na saída de um circuito auto-polarizado que gera um tensão CTAT. Além disso, explorando a capacidade de funcionar como um gerador de corrente específica (ISQ) que os monitores de VT0 aqui apresentados oferecem, introduz-se um novo circuito auto-polarizado que gera um tensão CTAT, que é menos sensível a variações de processo, e pode ser usado em referências de tensão band-gap.
A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature range, without external biases, parametric setups, curve fitting or any subsequent calculation. It can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications since the MOSFET VT0 dependence on the operation conditions is a very well modeled aspect. Also, it can be used for fabrication process monitoring and process variability compensation, since VT0 is a key parameter for the transistor behavior and modeling. In this thesis, we present three novel circuit topologies, two of them being NMOS VT0 monitors and the last one being a PMOS VT0 monitor. The three structures are resistorless self-biased circuit topologies that present high power supply rejection, low line sensitivity, and allow the direct extraction of the threshold voltage for wide temperature and power supply voltage ranges, with small error. Its design methodology is based on the Unified Current Control Model (UICM), a MOSFET model that is continuous from weak to strong inversion and from triode to saturation regions. The circuits occupy small silicon area, consume just tens of nanoWatts, and can be implemented in any standard digital CMOS process, since they only use MOS transistors (does not need any resistor). The VT0 monitors are used in different applications in order to prove their functionality, and behavior as part of a system. The applications vary from a reference voltage, that presents performance comparable with state-of-the-art works, to a configuration that allows to obtain a lower process variability, in the output of a self-biased circuit that generates a complementary to the absolute temperature (CTAT) voltage. In addition, exploiting the ability to operate as an specific current (ISQ) generator, that the VT0 monitors presented here offer, we introduced a new self-biased circuit that produces a CTAT voltage and is less sensitive to process variations, and can be used in band-gap voltage references.
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Narendra, Siva G. (Siva Gurusami) 1971. « Effect of MOSFET threshold voltage variation on high-performance circuits ». Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8341.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
Includes bibliographical references (p. 95-101).
The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in threshold voltage variation due to worsening short channel effect. This thesis will address three specific circuit design challenges arising from increased threshold voltage variation and present prospective solutions. First, with supply voltage scaling, control of die-to-die threshold voltage variation becomes critical for maintaining high yield. An analytical model will be developed for existing circuit technique that adaptively biases the body terminal of MOSFET devices to control this threshold voltage variation. Based on this model, recommendations on how to effectively use the technique in future technologies will be presented. Second, with threshold voltage scaling, sub-threshold leakage power is expected to be a significant portion of total power in future CMOS systems. Therefore, it becomes imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and a circuit technique to reduce system leakage without reducing system performance will be discussed.
(cont.) Finally, due to different processing steps and short channel effects, threshold voltage of devices of same or different polarities in the same neighborhood may not be matched. This will introduce mismatch in the device drive currents that will not be acceptable in some high performance circuits. In the last part of the thesis, voltage and current biasing schemes that minimize the impact of neighborhood threshold voltage mismatch will be introduced.
by Siva G. Narendra.
Ph.D.
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Silva, Augusto Neutzling. « Syhthesis of thereshold logic based circuits ». reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/119435.

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Circuitos baseados em portas lógicas de limiar (threshold logic gates – TLG) vem sendo estudados como uma alternativa promissora em relação ao tradicional estilo lógico CMOS, baseado no operadores AND e OR, na construção de circuitos integrados digitais. TLGs são capazes de implementar funções Booleanas mais complexas em uma única porta lógica. Diversos novos dispositivos, candidatos a substituir o transistor MOS, não se comportam como chaves lógicas e são intrinsicamente mais adequados à implementação de TLGs. Exemplos desses dispositivos são os memristores, spintronica, diodos de tunelamento ressonante (RTD), autômatos celulares quânticos (QCA) e dispositivos de tunelamento de elétron único (SET). Para o desenvolvimento de um fluxo de projeto de circuitos integrados baseados em lógica threshold, duas etapas são fundamentais: (1) identificar se uma dada função Booleana corresponde a uma função lógica threshold (TLF), isto é, pode ser implementada em um único TLG e computar os pesos desse TLG; (2) se uma função não é identificada como TLF, outro método de síntese lógica deve construir uma rede de TLGs otimizada que implemente a função. Este trabalho propõe métodos para atacar cada um desses dois problemas, e os resultados superam os métodos do estado-da-arte. O método proposto para realizar a identificação de TLFs é o primeiro método heurístico capaz de identificar todas as funções de cinco e seis variáveis, além de identificar mais funções que os demais métodos existentes quando o número de variáveis aumenta. O método de síntese de redes de TLGs é capaz de sintetizar circuitos reduzindo o número de portas TLG utilizadas, bem como a profundidade lógica e o número de interconexões. Essa redução é demonstrada através da síntese dos circuitos de avaliação da MCNC em comparação com os métodos já propostos na literatura. Tais resultados devem impactar diretamente na área e desempenho do circuito.
In this work, a novel method to synthesize digital integrated circuits (ICs) based on threshold logic gates (TLG) is proposed. Synthesis considering TLGs is quite relevant, since threshold logic has been revisited as a promising alternative to conventional CMOS IC design due to its suitability to emerging technologies, such as resonant tunneling diodes, memristors and spintronics devices. Identification and synthesis of threshold logic functions (TLF) are fundamental steps for the development of an IC design flow based on threshold logic. The first contribution is a heuristic algorithm to identify if a function can be implemented as a single TLG. Furthermore, if a function is not detected as a TLF, the method uses the functional composition approach to generate an optimized TLG network that implements the target function. The identification method is able to assign optimal variable weights and optimal threshold value to implement the function. It is the first heuristic algorithm that is not based on integer linear programming (ILP) that is able to identify all threshold functions with up to six variables. Moreover, it also identifies more functions than other related heuristic methods when the number of variables is more than six. Differently from ILP based approaches, the proposed algorithm is scalable. The average execution time is less than 1 ms per function. The second major contribution is the constructive process applied to generate optimized TLG networks taking into account multiple goals and design costs, like gate count, logic depth and number of interconnections. Experiments carried out over MCNC benchmark circuits show an average gate count reduction of 32%, reaching up to 54% of reduction in some cases, when compared to related approaches.
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Ting, Darwin Ta-Yueh. « Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs ». Ohio University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1219672300.

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Dhillon, Yuvraj Singh. « Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability ». Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6935.

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Power consumption and soft-error tolerance have become major constraints in the design of DSM CMOS circuits. With continued technology scaling, the impact of these parameters is expected to gain in significance. Furthermore, the design complexity continues to increase rapidly due to the tremendous increase in number of components (gates/transistors) on an IC every technology generation. This research describes an efficient and general CAD framework for the optimization of critical circuit characteristics such as power consumption and soft-error tolerance under delay constraints with supply/threshold voltages and/or gate sizes as variables. A general technique called Delay-Assignment-Variation (DAV) based optimization was formulated for the delay-constrained optimization of directed acyclic graphs. Exact mathematical conditions on the supply and threshold voltages of circuit modules were developed that lead to minimum overall dynamic and static power consumption of the circuit under delay constraints. A DAV search based method was used to obtain the optimal supply and threshold voltages that minimized power consumption. To handle the complexity of design of reliable, low-power circuits at the gate level, a hierarchical application of DAV based optimization was explored. The effectiveness of the hierarchical approach in reducing circuit power and unreliability, while being highly efficient is demonstrated. The usage of the technique for improving upon already optimized designs is described. An accurate and efficient model for analyzing the soft-error tolerance of CMOS circuits is also developed.
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Parthasarathy, Krupa. « Aging Analysis and Aging-Resistant Design for Low-Power Circuits ». University of Cincinnati / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1415615574.

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Gopalakrishnan, Harish. « Energy Reduction for Asynchronous Circuits in SoC Applications ». Wright State University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=wright1324264498.

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Livres sur le sujet "Threshold circuits"

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Anis, Mohab, et Mohamed Elmasry. Multi-Threshold CMOS Digital Circuits. Boston, MA : Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0391-0.

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Kursun, Volkan. Multiple supply and threshold voltage CMOS circuits. Chichester, England : John Wiley, 2006.

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1943-, Elmasry Mohamed I., dir. Multi-threshold CMOS digital circuits : Managing leakage power. Boston : Kluwer Academic Publishers, 2003.

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Anis, Mohab. Multi-Threshold CMOS Digital Circuits : Managing Leakage Power. Boston, MA : Springer US, 2003.

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Anis, Mohab. Multi-threshold CMOS digital circuits : Managing leakage power. Boston, MA : Kluwer Academic Publishers, 2004.

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Meer, P. R. Low-Power Deep Sub-Micron CMOS Logic : Sub-threshold Current Reduction. Boston, MA : Springer US, 2004.

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P. R. van der Meer. Low-power deep sub-micron CMOS logic : Sub-threshold current reduction. Boston : Kluwer Academic, 2004.

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Circuits and Systems Advances in Near Threshold Computing. MDPI, 2021. http://dx.doi.org/10.3390/books978-3-0365-0721-7.

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Anis, Mohab, et Mohamed Elmasry. Multi-Threshold CMOS Digital Circuits : Managing Leakage Power. Springer, 2003.

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Multi-Threshold CMOS Digital Circuits : Managing Leakage Power. Springer, 2012.

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Chapitres de livres sur le sujet "Threshold circuits"

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Anis, Mohab, et Mohamed Elmasry. « MTCMOS Sequential Circuits ». Dans Multi-Threshold CMOS Digital Circuits, 135–61. Boston, MA : Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0391-0_5.

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Anis, Mohab, et Mohamed Elmasry. « MTCMOS Dynamic Circuits ». Dans Multi-Threshold CMOS Digital Circuits, 163–93. Boston, MA : Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0391-0_6.

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Hansen, Kristoffer Arnsfelt, et Vladimir V. Podolskii. « Polynomial Threshold Functions and Boolean Threshold Circuits ». Dans Mathematical Foundations of Computer Science 2013, 516–27. Berlin, Heidelberg : Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-40313-2_46.

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Anis, Mohab, et Mohamed Elmasry. « Embedded MTCMOS Combinational Circuits ». Dans Multi-Threshold CMOS Digital Circuits, 45–72. Boston, MA : Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0391-0_3.

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Anis, Mohab, et Mohamed Elmasry. « MTCMOS Current-Steering Circuits ». Dans Multi-Threshold CMOS Digital Circuits, 195–214. Boston, MA : Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0391-0_7.

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Razborov, Alexander A. « On small depth threshold circuits ». Dans Algorithm Theory — SWAT '92, 42–52. Berlin, Heidelberg : Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/3-540-55706-7_4.

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Anis, Mohab, et Mohamed Elmasry. « MTCMOS Combinational Circuits Using Sleep Transistors ». Dans Multi-Threshold CMOS Digital Circuits, 73–133. Boston, MA : Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0391-0_4.

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Anis, Mohab, et Mohamed Elmasry. « Introduction ». Dans Multi-Threshold CMOS Digital Circuits, 1–3. Boston, MA : Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0391-0_1.

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Anis, Mohab, et Mohamed Elmasry. « Leakage Power : Challenges and Solutions ». Dans Multi-Threshold CMOS Digital Circuits, 5–44. Boston, MA : Springer US, 2003. http://dx.doi.org/10.1007/978-1-4615-0391-0_2.

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Albrecht, A., E. Hein, D. Melzer, K. Steinhöfel et M. Taupitz. « CT Image Classification by Threshold Circuits ». Dans Bildverarbeitung für die Medizin 2001, 362–66. Berlin, Heidelberg : Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/978-3-642-56714-8_67.

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Actes de conférences sur le sujet "Threshold circuits"

1

Hansen, Kristoffer Arnsfelt, et Vladimir V. Podolskii. « Exact Threshold Circuits ». Dans 2010 IEEE 25th Annual Conference on Computational Complexity (CCC). IEEE, 2010. http://dx.doi.org/10.1109/ccc.2010.33.

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Yao, Jia, et Vishwani D. Agrawal. « Dual-threshold design of sub-threshold circuits ». Dans 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) (Formerly known as SOI Conference). IEEE, 2013. http://dx.doi.org/10.1109/s3s.2013.6716544.

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Goldmann, Mikael, et Marek Karpinski. « Simulating threshold circuits by majority circuits ». Dans the twenty-fifth annual ACM symposium. New York, New York, USA : ACM Press, 1993. http://dx.doi.org/10.1145/167088.167234.

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« Session MC1 : Multi-Threshold Circuits ». Dans IEEE International SOC Conference, 2004. Proceedings. IEEE, 2004. http://dx.doi.org/10.1109/socc.2004.1362335.

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Khatir, Mehrdad, Hassan Ghasemzadeh Mohammadi et Alireza Ejlali. « Sub-threshold charge recovery circuits ». Dans 2010 IEEE International Conference on Computer Design (ICCD 2010). IEEE, 2010. http://dx.doi.org/10.1109/iccd.2010.5647815.

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Hajnal, Andras, Wolfgang Maass, Pavel Pudlak, Mario Szegedy et Gyorgy Turan. « Threshold circuits of bounded depth ». Dans 28th Annual Symposium on Foundations of Computer Science. IEEE, 1987. http://dx.doi.org/10.1109/sfcs.1987.59.

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Pham, Cong-Kha. « Simple Logic Threshold Conversion Circuits ». Dans 2006 13th IEEE International Conference on Electronics, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/icecs.2006.379777.

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Zhanbossinov, Askhat, Kamilya Smagulova et Alex Pappachen James. « CMOS-memristor dendrite threshold circuits ». Dans 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2016. http://dx.doi.org/10.1109/apccas.2016.7803914.

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Razavi, Hassan M. « Realistic Realizations Of Threshold Circuits ». Dans OE LASE'87 and EO Imaging Symp (January 1987, Los Angeles), sous la direction de Raymond Arrathoon. SPIE, 1987. http://dx.doi.org/10.1117/12.939919.

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Kim, Namsung, et Radu Zlatanovici. « Session details : Sub-threshold circuits ». Dans ISLPED'09 : International Symposium on Low Power Electronics and Design. New York, NY, USA : ACM, 2009. http://dx.doi.org/10.1145/3253814.

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