Thèses sur le sujet « SW Engineering »
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Egerton, David. « Automated generation of SW design constructs from MESA source code / ». Online version of thesis, 1993. http://hdl.handle.net/1850/12144.
Texte intégralSuljevic, Benjamin. « Mapping HW resource usage towards SW performance ». Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-44176.
Texte intégralPacourek, Kryštof. « Využití workshopů při analýze požadavků softwarového projektu ». Master's thesis, Vysoká škola ekonomická v Praze, 2013. http://www.nusl.cz/ntk/nusl-197824.
Texte intégralChee, Kenneth W. « APPLIED HW/SW CO-DESIGN : Using the Kendall Tau Algorithm for Adaptive Pacing ». DigitalCommons@CalPoly, 2013. https://digitalcommons.calpoly.edu/theses/1038.
Texte intégralSeidi, Nahid. « Document-Based Databases In Platform SW Architecture For Safety Related Embedded System ». Thesis, Blekinge Tekniska Högskola, Institutionen för programvaruteknik, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-3122.
Texte intégralNowicki, Lisa Ann. « Engineering geology considerations for realignment of interstate 70/76 across the landslide at New Baltimore, Somerset County, SW Pennsylvania ». Kent State University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=kent1302399443.
Texte intégralRenbi, Abdelghani. « Power and Energy Efficiency Evaluation for HW and SW Implementation of nxn Matrix Multiplication on Altera FPGAs ». Thesis, Jönköping University, JTH, Computer and Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-10545.
Texte intégralIn addition to the performance, low power design became an important issue in the design process of mobile embedded systems. Mobile electronics with rich features most often involve complex computation and intensive processing, which result in short battery lifetime and particularly when low power design is not taken in consideration. In addition to mobile computers, thermal design is also calling for low power techniques to avoid components overheat especially with VLSI technology. Low power design has traced a new era. In this thesis we examined several techniques to achieve low power design for FPGAs, ASICs and Processors where ASICs were more flexible to exploit the HW oriented techniques for low power consumption. We surveyed several power estimation methodologies where all of them were prone to at least one disadvantage. We also compared and analyzed the power and energy consumption in three different designs, which perform matrix multiplication within Altera platform and using state-of-the-art FPGA device. We concluded that NIOS II\e is not an energy efficient alternative to multiply nxn matrices compared to HW matrix multipliers on FPGAs and configware is an enormous potential to reduce the energy consumption costs.
Tiejun, Hu Di Wu. « Design of Single Scalar DSP based H.264/AVC Decoder ». Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2812.
Texte intégralH.264/AVC is a new video compression standard designed for future broadband network. Compared with former video coding standards such as MPEG-2 and MPEG-4 part 2, it saves up to 40% in bit rate and provides important characteristics such as error resilience, stream switching etc. However, the improvement in performance also introduces increase in computational complexity, which requires more powerful hardware. At the same time, there are several image and video coding standards currently used such as JPEG and MPEG-4. Although ASIC design meets the performance requirement, it lacks flexibility for heterogeneous standards. Hence reconfigurable DSP processor is more suitable for media processing since it provides both real-time performance and flexibility.
Currently there are several single scalar DSP processors in the market. Compare to media processor, which is generally SIMD or VLIW, single scalar DSP is cheaper and has smaller area while its performance for video processing is limited. In this paper, a method to promote the performance of single scalar DSP by attaching hardware accelerators is proposed. And the bottleneck for performance promotion is investigated and the upper limit of acceleration of a certain single scalar DSP for H.264/AVC decoding is presented.
Behavioral model of H.264/AVC decoder is realized in pure software during the first step. Although real-time performance cannot be achieved with pure software implementation, computational complexity of different parts is investigated and the critical path in decoding was exposed by analyzing the first design of this software solution. Then both functional acceleration and addressing acceleration were investigated and designed to achieve the performance for real-time decoding using available clock frequency within 200MHz.
Nilsson, Per. « Hardware / Software co-design for JPEG2000 ». Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5796.
Texte intégralFor demanding applications, for example image or video processing, there may be computations that aren’t very suitable for digital signal processors. While a DSP processor is appropriate for some tasks, the instruction set could be extended in order to achieve higher performance for the tasks that such a processor normally isn’t actually design for. The platform used in this project is flexible in the sense that new hardware can be designed to speed up certain computations.
This thesis analyzes the computational complex parts of JPEG2000. In order to achieve sufficient performance for JPEG2000, there may be a need for hardware acceleration.
First, a JPEG2000 decoder was implemented for a DSP processor in assembler. When the firmware had been written, the cycle consumption of the parts was measured and estimated. From this analysis, the bottlenecks of the system were identified. Furthermore, new processor instructions are proposed that could be implemented for this system. Finally the performance improvements are estimated.
Andersson, Mikael, et Per Karlström. « Parallel JPEG Processing with a Hardware Accelerated DSP Processor ». Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2615.
Texte intégralThis thesis describes the design of fast JPEG processing accelerators for a DSP processor.
Certain computation tasks are moved from the DSP processor to hardware accelerators. The accelerators are slave co processing machines and are controlled via a new instruction set. The clock cycle and power consumption is reduced by utilizing the custom built hardware. The hardware can perform the tasks in fewer clock cycles and several tasks can run in parallel. This will reduce the total number of clock cycles needed.
First a decoder and an encoder were implemented in DSP assembler. The cycle consumption of the parts was measured and from this the hardware/software partitioning was done. Behavioral models of the accelerators were then written in C++ and the assembly code was modified to work with the new hardware. Finally, the accelerators were implemented using Verilog.
Extension of the accelerator instructions was given following a custom design flow.
Pizzoleto, Alessandro Viola [UNESP]. « Ontologia empresarial do modelo de referência MPS para software (MR-MPS-SW) com foco nos níveis G e F ». Universidade Estadual Paulista (UNESP), 2013. http://hdl.handle.net/11449/98685.
Texte intégralEste trabalho apresenta uma proposta que objetiva contribuir com a compreensão do Modelo de Referência MPS para Software (MR-MPS-SW), facilitando a sua implantação, principalmente em micros, pequenas e médias empresas (mPME) produtoras de software. Outro objetivo é contribuir com a uniformização do conhecimento do MR-MPS-SW entre todos os envolvidos nos processos de implantação, consultoria e avaliação do modelo. O MR-MPS-SW possui sete níveis de maturidade, de A (maior nível) a G (menor nível). A proposta trata de uma nova forma de organizar o conhecimento do MR-MPS-SW através da definição de uma ontologia empresarial implementada em OWL para os níveis G e F. Esses níveis requerem grandes desafios na mudança da cultura organizacional, bem como no gerenciamento de projetos, garantia da qualidade e medições. Para apoiar o usuário com uniformização dos termos de Gerência de Projetos, foram associados conceitos e terminologia do PMBOK (Project Management Body of Knowledge). Indicadores do modelo BSC (Balanced Scorecard) foram integrados ao modelo MR-MPS-SW para facilitar futuras iniciativas de alinhamento com o planejamento estratégico da empresa e modelo de negócios. Para isso, este trabalho providenciou uma sistemática para avaliação de uma versão alpha da ontologia, através de técnicas usadas em testes de usabilidade na Engenharia de Software. Essa avaliação mostrou como a ontologia facilitou o entendimento de usuários com diferentes níveis de conhecimento no MR-MPS-SW. Também proporcionou recomendações para melhorias na ontologia. Uma versão beta foi disponibilizada em repositórios gratuitos para ser avaliada por mPME e pessoas interessadas no modelo MPS-SW
This work presents a proposal that aims to contribute to the understanding of MPS Reference Model for Software (MPS-SW), facilitating its deployment, especially in micro, small and medium enterprises (MSME) of software development. Another goal is to contribute to the standardization of the knowledge of the MPS-SW among stakeholders in the process of implantation, consulting and evaluation of the model. The MPS-SW has seven levels of maturity, from A (highest level) to G (lower level). This proposal is a new way of organizing knowledge of the MPS-SW through the definition of an enterprise ontology in OWL for G and F levels. These levels require great efforts in changing organizational culture, as well as project management, quality assurance and measurements. . Terminology and concepts of the PMBOK (Project Management Body of Knowledge) were associated to the ontology, in order, to support the user in terms of standardization of project management. Indicators of the BSC Model (Balanced Scorecard) were integrated into the MPS-SW model to facilitate future initiatives for alignment with the strategic planning and business model. For this purpose this work provided a systematic evaluation of an alpha release of the ontology using techniques of usability testing in Software Engineering. The evaluation showed how ontology facilitated the understanding of users with different levels of knowledge on the MRMPS-SW. It also provided the definition of recommendations for improvements in the ontology. A beta version was made available in free ontology repositories to be evaluated by MSME and people interested in the MPS-SW model
Pizzoleto, Alessandro Viola. « Ontologia empresarial do modelo de referência MPS para software (MR-MPS-SW) com foco nos níveis G e F / ». São José do Rio Preto, 2013. http://hdl.handle.net/11449/98685.
Texte intégralBanca: Kechi Hirama
Banca: João Porto
Resumo: Este trabalho apresenta uma proposta que objetiva contribuir com a compreensão do Modelo de Referência MPS para Software (MR-MPS-SW), facilitando a sua implantação, principalmente em micros, pequenas e médias empresas (mPME) produtoras de software. Outro objetivo é contribuir com a uniformização do conhecimento do MR-MPS-SW entre todos os envolvidos nos processos de implantação, consultoria e avaliação do modelo. O MR-MPS-SW possui sete níveis de maturidade, de A (maior nível) a G (menor nível). A proposta trata de uma nova forma de organizar o conhecimento do MR-MPS-SW através da definição de uma ontologia empresarial implementada em OWL para os níveis G e F. Esses níveis requerem grandes desafios na mudança da cultura organizacional, bem como no gerenciamento de projetos, garantia da qualidade e medições. Para apoiar o usuário com uniformização dos termos de Gerência de Projetos, foram associados conceitos e terminologia do PMBOK (Project Management Body of Knowledge). Indicadores do modelo BSC (Balanced Scorecard) foram integrados ao modelo MR-MPS-SW para facilitar futuras iniciativas de alinhamento com o planejamento estratégico da empresa e modelo de negócios. Para isso, este trabalho providenciou uma sistemática para avaliação de uma versão alpha da ontologia, através de técnicas usadas em testes de usabilidade na Engenharia de Software. Essa avaliação mostrou como a ontologia facilitou o entendimento de usuários com diferentes níveis de conhecimento no MR-MPS-SW. Também proporcionou recomendações para melhorias na ontologia. Uma versão beta foi disponibilizada em repositórios gratuitos para ser avaliada por mPME e pessoas interessadas no modelo MPS-SW
Abstract: This work presents a proposal that aims to contribute to the understanding of MPS Reference Model for Software (MPS-SW), facilitating its deployment, especially in micro, small and medium enterprises (MSME) of software development. Another goal is to contribute to the standardization of the knowledge of the MPS-SW among stakeholders in the process of implantation, consulting and evaluation of the model. The MPS-SW has seven levels of maturity, from A (highest level) to G (lower level). This proposal is a new way of organizing knowledge of the MPS-SW through the definition of an enterprise ontology in OWL for G and F levels. These levels require great efforts in changing organizational culture, as well as project management, quality assurance and measurements. . Terminology and concepts of the PMBOK (Project Management Body of Knowledge) were associated to the ontology, in order, to support the user in terms of standardization of project management. Indicators of the BSC Model (Balanced Scorecard) were integrated into the MPS-SW model to facilitate future initiatives for alignment with the strategic planning and business model. For this purpose this work provided a systematic evaluation of an alpha release of the ontology using techniques of usability testing in Software Engineering. The evaluation showed how ontology facilitated the understanding of users with different levels of knowledge on the MRMPS-SW. It also provided the definition of recommendations for improvements in the ontology. A beta version was made available in free ontology repositories to be evaluated by MSME and people interested in the MPS-SW model
Mestre
Pasca, Vladimir. « Développement d'architectures HW/SW tolérantes aux fautes et auto-calibrantes pour les technologies Intégrées 3D ». Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00838677.
Texte intégralAburawi, Abdulrahman, et Sarija Salic. « Emergency Communication ». Thesis, Malmö högskola, Fakulteten för teknik och samhälle (TS), 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:mau:diva-20568.
Texte intégralKhlif, Manel. « Analyse de diagnosticabilité d'architecture de fonctions embarquées - Application aux architectures automobiles ». Phd thesis, Université de Technologie de Compiègne, 2010. http://tel.archives-ouvertes.fr/tel-00801608.
Texte intégralBICCHIERAI, IRENE. « An Ontological Approach Supporting the Development of Safety-Critical Software ». Doctoral thesis, 2014. http://hdl.handle.net/2158/851497.
Texte intégralKandasamy, Santheeban. « Dynamic HW/SW Partitioning : Configuration Scheduling and Design Space Exploration ». Thesis, 2007. http://hdl.handle.net/10012/3042.
Texte intégralTrommelen, Michelle Suzanne. « Quaternary stratigraphy and glacial history of the Fort Nelson (southeast) and Fontas River (southwest) map areas (NTS 094J/SE and 0941/SW), northeastern British Columbia ». Thesis, 2006. http://hdl.handle.net/1828/2009.
Texte intégralJuliato, Marcio. « Fault Tolerant Cryptographic Primitives for Space Applications ». Thesis, 2011. http://hdl.handle.net/10012/5876.
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