Thèses sur le sujet « Supply-Embedded »

Le ultime novita in ambito automotive sono dovute principalmente ai compoenenti elettronici ed elettrici che favoriscono la riduzione dei livelli di emissione e creano maggiore sicurezza e comfort. L’utilizzo di questi componenti sta aumentando sempre di più, ed essendo generalmente connessi tramite dei bus, stanno rendendo il sistema di cablaggio sempre piu complesso fino a renderlo uno dei blocchi piu critici da progettare. Pertanto, si stanno cercando nuove tecniche per ridurre il numero di interconnessioni. In questo lavoro si analizza un nuovo metodo per integrare la comunicazione e l'alimentazione su un unico bus differenziale. Diversamente dai metodi Power over Ethernet (PoE), l'implementazione proposta si basa sull’iniezione di cariche ben definite sul bus di comunicazione, che allo stesso tempo alimenta i vari dispositivi, al fine di generare dei pulsi. Sono proposti due approcci basati su capacità di commutazione: il Charge Alternation (CA) e il Charge Pump (CP). Il metodo CA, a 2Mbps, richiede solo il 50% della potenza di modulazione del carico resistivo, e il CP migliora ancora di più le prestazioni grazie alla capacità di riutilizzare parzialmente la carica immagazinata. Entrambe i circuiti di transmissione sono validati da una scheda dimostrativa e da un test chip in tecnologia 180nm BCD-on-SOI da cui si sono ottenuti risultati eccellenti. Inoltre, un circuito di ricezione é mostrato ed implementato in un test chip che quindi realizza un ricetrasmettitore completo. La tesi é organizzata come segue: l'introduzione e le motivazioni alla base di questa attivitá sono mostrate nel Capitolo 1. Nel capitolo 2 sono analizzati il concetto basico di transmissione e la modellazione del bus differenziale. Il Capitolo 3 sono esaminate entrambe le implementazioni di trasmettitori proposti, andando nel dettaglio della caratteristica dei pulsi, della codifica e del consumo energetico. Una scheda dimostrativa fatta di componenti discreti e i relativi test sono presentati nel capitolo 4, rimpiazzando con successo un layer fisico di un applicazione simil-CAN per illuminazione interna delle auto. Vengono mostrati anche i risultati sulle emissioni elettromagnetiche che sono in linea con i requisiti standard. L'implentazione in silicio del trasmettitore, includendo entrambi circuiti sviluppati, é descritta dettagliatamente nel capitolo 5. Viene mostrata l’architettura degli switch ad alta tensione, la protezione ESD che fornisce un livello di HBM > 8kV e tutti i blocchi necessari per il funzionamento del chip. Alla fine dello stesso capitolo vengono mostrate le prestazioni del chip integrato. Nel Capitolo 6 si propone il circuito di ricezione e il composizione del chip che implementa il ricetrasmettitore completo in una struttura simile a quella precedente. I test top level del chip sono quindi esplicati prima di trarre le conclusioni finali.
The advancements in modern vehicles are mainly due to electrical and electronic components that support an increasing demand for lower emission levels, higher safety and comfort. Increasingly, these components are connected by bus systems, which lead to more complex wire harnesses in modern cars, than ever before. Because of this, the wire harness of a car became one of the most complex building blocks. Therefore, techniques to reduce the wiring overhead are becoming increasingly important. In this work, a new method for integrating the communication and power supply of network participants on one differential bus, is investigated. Different to methods such as Power over Ethernet (PoE), the proposed implementations are using charges to emit defined pulses in to the communication bus, that is also carrying the power supply. Two switched capacitor approaches are proposed, the charge alternation (CA) and the charge pump (CP) method. While the suggested CA mode, operating at 2, requires only 50% of the power of a resistive load modulation that reaches a comparable signal level, the CP mode improves this even further due to the inherent charge-reuse capability of the concept. The approaches are verified with a demonstrator and a transmitter test chip fabricated in a 180nm BCD-on-SOI technology, that both shows the excellent performance of the concept and the silicon implementation. Furthermore, the receiver is discussed and implemented as part of a transceiver test chip, fabricated in the same technology. The reminder of the work is organized as follows: After the introduction and motivation for this research project in chapter 1, basic transmission concepts are described as well as the modelling of the differential bus based on a twisted pair, is analysed in chapter 2. Chapter 3 examines both switched capacitor transmission concepts in detail, regarding pulse shape, encoding, and power consumption. To check the proposed transmission schemes in a real-world environment, a demonstrator using off-the-shelf components will be discussed and evaluated in chapter 4, that successfully replaces the existing physical layer of a CAN-like state-of-the-art application for interior car illumination. It shows also, that standards for electromagnetic emissions can be met with the proposed solutions. A silicon implementation for the transmitter part, realizing both methods, is described in detail in chapter 5. The architecture of the required high-voltage switches, the design of the ESD protection that withstand an HBM stress level > 8 and all necessary building blocks for a chip implementation that can work in a real network environment, are discussed. At the end of this chapter, the performance of the real silicon results are discussed. Chapter 6 proposes the receiver concept, and the transceiver chip level implementation using the same framework as developed with the transmitter test chip. The top-level verification of the build transceiver test chip is presented before conclusions are drawn.

Negli ultimi anni si è assistito ad un sensazionale aumento della presenza di sistemi e sensori elettronici all'interno delle automobili, che ha portato il sistema di interconnessioni ad essere uno degli aspetti maggiormenti critici e degni di attenzione durante le fasi di progettazione. E' divenuto quindi necessario studiare nuovi metodi di comunicazione al fine di gestire al meglio tale livello di complessità e favorire lo sviluppo dell'automobile del futuro. Nell'ambito di questa attività di ricerca, è stata proposta la progettazione di un ricetrasmettitore Supply-Embedded Communication (SEC) con caratteristiche tali da fornire vantaggi in termini economici, in semplicità costruttiva e relativamente al peso del veicolo stesso. Infatti nel sistema Supply-Embedded Communication utilizzato, l’alimentazione è unita al bus di comunicazione, portando ad una drastica riduzione del numero d'interconnessioni. Pertanto il metodo di comunicazione proposto si pone l'obiettivo di essere un layer fisico addizionale al Controller Area Network (CAN), il bus attualmente più diffuso nell’industria automotive, permettendo il raggiungimento di una velocità di trasmissione dati di diversi Mbps. Sono stati realizzate due diverse tipologie di trasmettitori basati su capacita di commutazione, implementati in un primo test chip in tecnologia 180nm CMOS SOI. Il prototipo realizzato è stato validato da test di comunicazione svolti in laboratorio, connettendo il chip stesso con una scheda dimostrativa a componenti discreti che funge da ricevitore. Inoltre un circuito di ricezione, basato su due latch StrongArm, è stato proposto ed integrato nella seconda versione del prototipo per realizzare il ricetrasmettitore SEC completo. Paragonato alle soluzioni già disponibili sul mercato, il metodo presentato in questa tesi può raggiungere una velocità di trasmissione di 2Mbps, rendendolo in grado d'implementare reti ad alta velocità come avviene nel bus CAN. Come progetto secondario è stato sviluppato un circuito di bandgap reference con compensazione al secondo ordine. I bandgap reference sono presenti ormai in quasi tutti i circuiti integrati e ve ne è presente uno anche nel ricetrasmettitore SEC oggetto di questa tesi, al fine di fornire la necessaria corrente di polarizzazione ai circuiti. Nonostante il progetto principale sia realizzato in tecnologia 180nm, il progetto secondario è svolto in 110nm per scopi didattici. Il circuito proposto è stato validato da simulazioni svolte in un range di temperature da -40°C a 175°C in un processo a 6σ.La compensazione al secondo ordine apporta vantaggi notevoli, in quanto fornisce un massima variazione dalla temperatura ambiente inferiore ad 1mV nel corner tipico e di 1.3mV nel corner peggiore.
Automotive wire harness has become nowadays a very complex system as the number of electronic systems and sensors inside a vehicle has increased dramatically. To manage this complexity, and to support the automotive systems of tomorrow, new communication methods need to be investigated. In this research activity, a Supply-Embedded Communication (SEC) transceiver for differential automotive networks is developed to provide advantages in cost, complexity, and weight. In a Supply-Embedded Communication system, the power supply is merged on the communication bus and hence the number of interconnections is drastically reduced. The proposed approach is intended to be an effective additional physical layer to the Controller Area Network (CAN) which is the most widespread bus in the automotive industry, and hence transmission speed in the order of some Mbps is desired. Two transmitter topologies based on switching capacitors and their implementation in a first test chip in 180nm CMOS SOI technology are presented. The prototype is validated by communication tests in the laboratory connecting it to a discrete component-based demonstrator receiver board through an unshielded twisted pair cable. A receiver circuit based on StrongArm Latches is designed and integrated into the second version of the prototype to realize a full SEC transceiver. Compared to commercially available solutions, the proposed approach can reach a data transmission rate of 2Mbps making it able to implement high-speed event-driven networks, such as the CAN. As a side project, a second order curvature compensated bandgap reference circuit is proposed. Voltage references are used in almost every integrated circuit and, one of them is also present in the SEC transceiver prototype to furnish the required bias to the circuit. Although the main project is done in 180nm technology, the side project is developed in 110nm technology for educational purposes. The proposed circuit is validated by simulation in a temperature range from -40°C to 175°C in a 6σ process spread. The second order compensation introduces a considerable improvement in performance by reducing the maximum variation from the room temperature to a value lower than 1mV in the typical corner and to 1.3mV in the worst corner.

This study was aimed at exploring data analysis techniques for generating accurate estimates of the loss in quality of fresh fruits, vegetables and cut flowers in chilled supply chains based on data from advanced sensors. It was motivated by the recent interest in the application of advanced sensors, by emerging concepts in quality controlled logistics, and by the desire to minimise quality losses during transport and storage of the produce. Cut roses were used in this work although the findings will also be applicable to other produce. The literature has reported that whilst temperature was considered to be the most critical post-harvest factor, others such as growing conditions could also be important in the senescence of cut roses. Kinetic modelling was the most commonly used modelling approach for shelf life predictions of foods and perishable produce, but not for estimating vase life (VL) of cut flowers, and so this was explored in this work along with multiple linear regression (MLR) and partial least squares (PLS). As the senescence of cut roses is not fully understood, kinetic modelling could not be implemented directly. Consequently, a novel technique, called Kinetic Linear System (KLS), was developed based on kinetic modelling principles. Simulation studies of shelf life predictions for tomatoes, mushrooms, seasoned soybean sprouts, cooked shrimps and other seafood products showed that the KLS models could effectively replace the kinetic ones. With respect to VL predictions KLS, PLS and MLR were investigated for data analysis from an in-house experiment with cut roses from Cookes Rose Farm (Jersey). The analysis concluded that when the initial and final VLs were available for model calibration, effective estimates of the post-harvest loss in VL of cut roses could be obtained using the post-harvest temperature. Otherwise, when the initial VLs were not available, such effective estimates could not be obtained. Moreover, pre-harvest conditions were shown to correlate with the VL loss but the correlation was too weak to produce or improve an effective estimate of the loss. The results showed that KLS performance was the best while PLS one could be acceptable; but MLR performance was not adequate. In another experiment, boxes of cut roses were transported from a Kenyan farm to a UK distribution centre. Using KLS and PLS techniques, the analysis showed that the growing temperature could be used to obtain effective estimates of the VLs at the farm, at the distribution centre and also the in-transit loss. Further, using post-harvest temperature would lead to a smaller error for the VL at the distribution centre and the VL loss. Nevertheless, the estimates of the VL loss may not be useful practically due to the excessive relative prediction error. Overall, although PLS had a slightly smaller prediction error, KLS worked effectively in many cases where PLS failed, it could handle constraints while PLS could not.In conclusion, KLS and PLS can be used to generate effective estimates of the post-harvest VL loss of cut roses based on post-harvest temperature stresses recorded by advanced sensors. However, the estimates may not be useful practically due to significant relative errors. Alternatively, pre-harvest temperature could be used although it may lead to slightly higher errors. Although PLS had slightly smaller errors KLS was more robust and flexible. Further work is recommended in the objective evaluations of product quality, alternative non-linear techniques and dynamic decision support system.

As the use of electric vehicles increases, the need for electric vehicle supply equipment to have more advanced functionality also increases. The HomePlug Green PHY standard was developed to allow more advanced communication between electric vehicles and electric vehicle supply equipment. This more advanced form of communication can solve problems such as load balancing during busy charging and seamless payment methods. There are some modem solutions that are based on the Qualcomm QCA7000 chip that allows for implementation of the HomePlug Green PHY standard.             This thesis explores and highlights the implementation of the hardware for the HomePlug Green PHY standard into a solution that is nearly plug and play for most electric vehicles. A module in the form of a PCB based around one of these modem solutions is developed that allows modular expansion of a traditional electric vehicle supply equipment to gain the functionality of HomePlug Green PHY. The final PCB is a near plug and play solution on the hardware side however, the software needs further development.

Informationssäkerhet är en viktig aspekt i företagande. Informationssäkerhet har länge betraktats som ett IT-initiativ men har på senare år breddats till en affärsangelägenhet vilket ökat intresset hos företagsledningar. Litteraturen inom informationssäkerhet fokuserar på hur företag upprätthåller säkra system som motstånd för cyberattacker och oönskad tillgång till information. Forskning identifierar nya säkerhetshot som uppkommit efter framsteg inom internetteknik men lite är känt om hur dessa hot kan hanteras. Forskare efterfrågar undersökning om hur samarbete i försörjningskedjor utgör risker mot säker informationshantering. Logistikföretag förser kunder med logistiktjänster som lagerhantering, transport, orderläggning och packning. Logistikföretag är en central nod i försörjningskedjor. De deltar ofta i flera försörjningskedjor i olika branscher. Den omfattande sammankopplingen av företag utgör en säkerhetsrisk. Det gör också att logistikföretag kan ses som måltavlor för cyberattacker. Studiens syfte har med den anledningen varit att skapa en förståelse för vilka utmaningar logistikföretag står inför vid hantering av informationssäkerhet i försörjningskedjan. Studiens forskningsfråga har besvarats genom att intervjua representanter från logistikföretag. Den empiriska data har tematiserats och analyserats. Studiens resultat visar att hanteringen av informationssäkerhet varierar mellan företagen. Studiens slutsatser presenterar rekommendationer. Rekommendationerna beskriver hur logistikföretag kan hantera informationssäkerhet i försörjningskedjan.
Information security is an important aspect when running a business. Before, information security has been separated to the business area of IT. But lately this issue has broadened and become an important part of business-activity. This has resulted in a growing interest among business leaders. Literature within the subject information security mainly focuses on how organizations maintain safe systems and protect themselves from cyber-attacks and information infringements. Existing literature identifies new security threats that have emerged after advances in internet technology, but little is known about how these threats can be managed. Researchers request research on how cooperation in supply chains poses risks to secure information management. Logistics companies provide customers with logistics services such as warehouse management, transport, order processing and packaging. Logistics companies are a central node in supply chains. They often participate in several supply chains in different industries. The extensive interconnection of companies poses a security risk. It also means that logistics companies can be seen as targets for cyber-attacks. The purpose of the study has therefore been to create an understanding of the challenges logistics companies face in managing information security in the supply chain.   The research question has been answered by interviewing representatives from logistics organizations. The empirical data has undergone a thematic analysis. The results of the study show that the management of information security varies between companies. The study’s conclusions present recommendations. The recommendations describe how logistics companies can manage information security in the supply chain.

La produzione agricola industriale su larga scala e il commercio di prodotti sono sempre più connessi a fenomeni di deforestazione e degradazione delle foreste tropicali. Tale fenomeno è descritto tramite il concetto di ‘rischio di deforestazione’ o forest-risk. I prodotti agricoli i cui processi produttivi implicano deforestazione e rimozione della vegetazione autoctona, sono classificati beni a rischio deforestazione (forest risk commodities). Carne bovina, soia, olio di palma e legname – i beni a rischio deforestazione – sono considerati ‘i grandi 4’ tra le forest-risk commodities. A causa della complessità dei sistemi globali di produzione e commercio alcuni beni sono indirettamente legati a tale rischio, poiché derivano da aree deforestate senza essere essi stessi causa diretta di deforestazione. Questa dimensione del rischio viene spesso tralasciata e permane un tema secondario nel dibattito sulla deforestazione derivata dalla produzione e il commercio di beni di consumo. La distinzione tra beni con un legame causale diretto con la deforestazione e beni che includono nella propria filiera il rischio di deforestazione incide su come la responsabilità della deforestazione viene attribuita e considerata sia tramite misure legali che tramite standard volontari di auto-regolamentazione. Pertanto risulta necessario sviluppare una concettualizzazione migliore per concordare una terminologia da utilizzare sia nella letteratura accademica che in quella informale e raggiungere delle decisioni politiche basate su un approccio scientifico. Nella ricerca effettuata si è voluto espandere la concettualizzazione di deforestation risk facendo riferimento al caso delle pelli bovine (di qui in avanti semplicemente, pelli) e in particolare al caso della produzione di pelli/prodotti di conceria in Brasile. Il focus sulle pelli ha molteplici ragioni. In primo luogo, mentre il ruolo degli allevamenti zootecnici come causa di deforestazione in Brasile è soggetto ad una crescente attenzione da parte dell’opinione pubblica, la filiera di produzione delle pelli rimane ancora inesplorata. Fatta eccezione per poche imprese leader del settore dei prodotti in pelle, il dibattito sulla trasparenza di questa filiera e il rischio di deforestazione ad essa associato è praticamente assente. In secondo luogo, la filiera della pelle è di norma molto più complessa rispetto a quella della carne bovina e coinvolge numerosi attori sia a livello nazionale che internazionale, ivi compresi gli intermediari, le concerie, le case di moda, ecc. Ciò crea delle discontinuità nella tracciabilità della pelle e complica l’identificazione del rischio di deforestazione lungo la filiera. Infine, la pelle è un bene che per propria stessa natura è legato a rapporti di forza squilibrati tra gli attori della filiera. Una terza ragione per la scelta del settore della pelle è data dal fatto che, poiché la pelle è spesso considerata un prodotto di scarto secondario della carne bovina, ne consegue che gli attori coinvolti nella filiera sostengono di avere uno scarso potere di negoziazione per imporre i loro standard e delle condizioni di non-deforestazione ai produttori. Al contempo, gli attori a valle della filiera, come le case di moda, sono maggiormente esposti a rischi di natura reputazionale rispetto alle imprese del settore della carne. In conseguenza di tale situazione vi è il fatto che la pelle è un bene con costi e benefici distribuiti in maniera asimmetrica all’interno della filiera. Mentre a monte gli allevatori mancano delle risorse per rispettare standard di sostenibilità e spesso non beneficiano di nessuna compensazione economica per il pellame dei propri bovini, i prodotti finiti in pelle sono visti come beni di lusso, con elevati margini di guadagno per le aziende che li producono e commerciano. Questa ricerca impiega sia dati primari che secondari. I dati primari sono principalmente di tipo qualitativo e derivano da trentanove interviste semi-strutturate e audio-registrate condotte sotto forma sia di colloqui vis-à-vis che a distanza (video-chiamate) durante una missione in Brasile tra maggio e agosto 2018. Tali dati sono stati utilizzati prevalentemente ai fini dell’analisi del discorso (discourse analysis) presentata nel secondo capitolo e come riferimenti interpretativi e di lettura del contesto per l’analisi dei dati quantitativi secondari presentata nei rimanenti capitoli. I dati e le informazioni secondari sono stati derivati da un’estesa analisi della letteratura e analisi di dati statistici relativi a mattatoi, registri su pelli bovine grezze e semilavorate e processi di deforestazione; sono stati inoltre considerati dati geospaziali relativi alle aree deforestate e alla localizzazione dei mattatoi e delle concerie; da ultimo sono stati considerati dati relativi al commercio di pelli e prodotti derivati tra Brasile e Italia. Nessun intervallo di tempo specifico è stato selezionato a priori per l’analisi dei dati: le serie temporali sono state selezionate a seconda della disponibilità di dati e delle necessità relative alle singole tipologie di analisi impiegate. Dai risultati emerge che la filiera delle pelli ha un rischio deforestazione significativo nonostante il pellame non sia un prodotto primario dell’allevamento bovino e un fattore diretto di deforestazione. Il rischio si colloca principalmente nel legame con le attività zootecniche e di allevamento, nell’incompleta tracciabilità della filiera così come nel commercio interno e internazionale di pelle. Le pelli prodotte in Brasile e importate per essere successivamente lavorate in Italia incorporano un livello significativo di rischio di deforestazione a causa degli intensi scambi commerciali tra i due Paesi. Il rischio di deforestazione legato alle pelli è affrontato in maniera diversa dai diversi discorsi esistenti sul tema e pone in evidenza come l’articolarsi della trama di ciascun discorso comporti l’attenzione sia su aspetti visibili che invisibili rispetto alla sostenibilità, all’equità e alla legalità delle filiere in questione. I risultati mettono in risalto l’importanza del ruolo e della voce degli agricoltori di frontiera, mostrando come la loro visione e interpretazione informi un discorso politico incentrato sul tema della sopravvivenza e del sostentamento. È quindi necessaria una maggiore attenzione da parte dell’opinione pubblica sulle filiere produttive, ivi comprese quelle delle pelli e dei prodotti derivati, e in particolare sulle relazioni non eque di potere, così come sull’importanza di un’inclusione significativa di gruppi vulnerabili della popolazione. L’industria del pellame e i grandi marchi dovrebbero essere più proattivi, inviando al mercato un chiaro segnale per cui la deforestazione e altre forme di illegalità non possono essere tollerate. Una piena tracciabilità della filiera e il coinvolgimento dei produttori è imprescindibile se l’industria mira a produrre e commerciare prodotti che non siano responsabili di o coinvolti in processi di deforestazione.
Large-scale industrial agricultural production and commodity trade are increasingly linked to deforestation and forest degradation in the tropics. This link is described via the concept of ‘deforestation risk’. Agricultural products whose production or extraction involves deforestation and native vegetation clearing are classified as forest-risk commodities. Beef, soybean, palm oil, and timber - the commodities with deforestation risk - are considered the “big four” of forest-risk commodities. Due to the complexity of global production and trade systems there are commodities that possess the risk of originating from deforested areas without being direct deforestation/forest degradation drivers. This dimension of the risk is either overlooked or held as secondary in the debates about commodity-driven deforestation. Differentiation between commodities with direct causal links and those with the exposure to deforestation in their supply chain has impact on how responsibility and accountability is constructed both through legal measures and self-regulatory voluntary standards. Better conceptualization is needed to approximate the usage of the terms both in grey and academic literature and to achieve science backed policy decisions. By referring to the case of bovine leather (hereinafter just leather) and the case of Brazilian leather production we aim to expand the conceptualization of deforestation risk. We focus on leather for multiple reasons. First, while the role of cattle in driving deforestation in Brazil is subject to increasing public scrutiny, the leather commodity chain largely remains in the shadow. Except for a few leading firms in leather goods, public discussion about transparency across the leather supply chain and associated deforestation risk is mostly absent. Second, leather supply chains are more complex compared to beef and involve many national and international players, including intermediary sellers, tanneries, fashion houses, etc. This creates traceability gaps and complicates identifying deforestation risk along the chain. Third, leather is a commodity with inherently uneven power relations among the actors in the supply chain and with costs and benefits unevenly distributed across the chain. Often considered a waste or by-product to beef meat, actors in the leather supply chain argue to lack important negotiation power to impose their standards and no deforestation conditions upon producers. At the same time, downstream actors of leather supply chain, such as fashion brands, are more susceptible to reputational risks compared to that of beef. While upstream farmers lack resources to adhere to sustainability standards and hardly get any financial compensation for the skin of their cattle, finished leather products are often regarded as luxury products presenting very high price margins for producing/trading brands. This research employs both primary and secondary data. Primary data is mostly qualitative and entails thirty-nine semi-structured, recorded, and transcribed interviews, in the form of both face-to-face and video call interviews conducted during extended field visit to Brazil in May-August 2018. This data is mainly used for the discourse analysis in the second chapter and for interpretative and contextual purposes to analyse the secondary quantitative data in the other chapters. Secondary information consists of extensive literature review, statistical data on annual slaughter, bovine hide/leather registry and annual deforestation, geospatial data on deforestation, slaughterhouse and tannery locations, as well as, trade statistics on Brazilian-Italian leather trade. No specific time frame was chosen to analyse the data and time series for each data set were selected according to availability and the specific requirements of each type of analysis. The results show that bovine leather supply chains possess significant risk of embedded deforestation despite leather not being a primary product of cattle ranching and driver of deforestation. The risk reveals itself in the link with cattle ranching, incomplete supply chain traceability, as well as in interstate and international leather trade. The Brazilian-Italian bovine leather has significant level of embedded deforestation due to intensive trade relations. Different discourses articulate deforestation risk of bovine leather differently and highlight how the storylines of each discourse bring attention both to what is made visible and invisible in relation to sustainability, legitimacy, and fairness. The results emphasise the importance of the role and voice of frontier settlers, by presenting how their storylines inform a political discourse on livelihoods. There is a need for increased public scrutiny of supply chains, including the leather one, and for special attention to unequal power relations and the importance of meaningful inclusion of vulnerable groups and populations. The leather industry and big brands need to be more proactive by sending clear market signals that deforestation and other illegalities are not tolerated. Full coverage and traceability of the supply chain and engagement with the producers is necessary if the industry wants to produce and trade deforestation-free products.

This thesis entails the design and fabrication of a smartphone charger that is powered by a bicycle dynamo hub. In addition to the design and validation of the charger prototype, this thesis involves the testing and characterization of the dynamo hub power source, the design and construction of specialized test equipment, and the design and prototyping of a handlebar-mounted case for the smartphone and charging electronics. With the intention of making the device a commercial product, price, aesthetics, and marketability are of importance to the design. An appropriate description of the charger circuit is a microcontroller-based energy management system, tailored to meet strict power demands of current smartphones. The system incorporates a switched-mode power supply, lithium polymer battery, microcontroller, and specialized protection circuitry. Prototype testing confirms that the circuit meets the charging requirements of the smartphone at bicycle speeds ranging from 7 miles per hour to as high as 55 miles per hour.

The objective of the proposed research is to design, fabricate, characterize and test silicon-embedded magnetic components for on-chip integrated power applications. Driven by the trend towards continued system multi-functionality and miniaturization, MEMS technology can be used to enable fabrication of three-dimensional (3-D) functional devices into the silicon bulk, taking advantage of the 'dead volume' in the substrate and achieving a greater level of miniaturization and integration. As an example, one of the challenges in realizing ultra-compact high-frequency power converters lies in the integration of magnetic components due to their relatively large volume. Embedding 3-D magnetic components within the wafer volume and implementing high-power, through-wafer interconnect for connection to circuitry on the wafer surface is a promising solution for achieving ultra-compact power converters, in which digital control circuitry and power switches are located on the wafer surface, and suitable magnetic components are embedded within the silicon substrate. In order to do this, key tasks in the following areas have been accomplished: development of new fabrication technologies for silicon embedding and 3-D structure realization; creation of high-current, through-wafer interconnects for connection of the device to circuitry; ability to incorporate a variety of magnetic materials when performance enhancement of the device is needed; exploration of a new design space for the devices due to ultra-compactness and silicon interaction; understanding of the complicated loss mechanisms in the embedded devices; and demonstration of device performance and in-circuit operation.

This study presents a methodology and the necessary analytical tools to evaluate the alternatives to provide Internet access with embedded power generation in remote areas. The objective is to provide a screening tool for policy makers to analyze possible telecom and power alternatives. Results from the study demonstrate the technical alternatives to providing sustainable Internet and power access. The dissertation investigates innovative telecom technologies currently available on the market, and develops a model that generates a Telecom-and-Internet access map of a region or a small country. The map illustrates the combination of technologies and their locations that can provide wide-area Internet access to cover a majority of the population at the least cost. The model then looks at the design of a small-scale power system for a remote location where grid power is unavailable or unreliable. The methodology takes into account locally available energy resources, technical and economic parameters of each power generating technology, and the trade-off among investment costs, environmental costs and system robustness. Lastly, a computer simulation is conducted to verify that the power system design has the ability to meet the demand at the level of required reliability. A remote area of a developing country (Chittagong and Chittagong Hill Tracts - Bangladesh) is selected as a case study. Several scenarios are simulated in order to explore the possibility of extending the reach of the Internet and electric power to the remote area, and to conceptualize pilot projects as building blocks to build a countrywide infrastructure. Since the selected area is one of the least developed and most difficult to access in Bangladesh, demonstrating that the Internet and local power access can be provided to this area can serve as a model for similar places around the world.
Ph. D.

The integration of dispatchable renewable energies like biomass, geothermal and reservoir hydro technologies into an electrical network present no greater challenge than the integration of conventional power technologies for which are well understood by Eskom engineers. However, renewable energies that are based on resources that fluctuate throughout the day and from season to season, like wind and solar, introduce a number of challenges that Eskom engineers have not dealt with before. It is current practice for Eskom‟s generation to follow the load in order to balance the demand and supply. Through Eskom‟s load dispatching desk at National Control, generator outputs are adjusted on an hourly basis with balancing reserves making up only a small fraction of the total generation. Through the Integrated Resource Plan for Electricity of 2010, the Department of Energy has set some targets towards integrating renewable energy, including wind and solar generation, into the South African electricity market consequently introducing variability on the supply side. With demand that varies continually, maintaining a steady balance between supply and demand is already a challenging task. When the supply also becomes variable and less certain with the introduction of non-dispatchable renewable energy, the task becomes even more challenging. The aim of this research study is to determine whether the resources that previously helped to balance the variability in demand will still be adequate to balance variability in both demand and supply. The study will only concentrate on variable or non-dispatchable renewable energies as will be added to the South African electrical network according to the first two rounds of the Department of Energy‟s Renewable Energy Independent Power Producer Procurement Programme. This research study only looks into the balancing challenge and does not go into an analysis of voltage stability or network adequacy, both of which warrant in depth analysis.
Thesis (MIng (Development and Management Engineering))--North-West University, Potchefstroom Campus, 2013.

L’émergence des circuits complexes numériques, ou System-On-Chip (SOC), pose notamment la problématique de la consommation énergétique. Parmi les blocs fonctionnels significatifs à ce titre, apparaissent les mémoires et en particulier les mémoires statiques (SRAM). La maîtrise de la consommation énergétique d’une mémoire SRAM inclue la capacité à rendre la mémoire fonctionnelle sous très faible tension d’alimentation, avec un objectif agressif de 300 mV (inférieur à la tension de seuil des transistors standard CMOS). Dans ce contexte, les travaux de thèse ont concerné la proposition d’un point mémoire SRAM suffisamment performant sous très faible tension d’alimentation et pour les nœuds technologiques avancés (CMOS bulk 28nm et FDSOI 28nm). Une analyse comparative des architectures proposées dans l’état de l’art a permis d’élaborer deux points mémoire à 10 transistors avec de très faibles impacts de courant de fuite. Outre une segmentation des ports de lecture, les propositions reposent sur l’utilisation de périphéries adaptées synchrones avec notamment une solution nouvelle de réplication, un amplificateur de lecture de données en mode tension et l’utilisation d’une polarisation dynamique arrière du caisson SOI (Body Bias). Des validations expérimentales s’appuient sur des circuits en technologies avancées. Enfin, une mémoire complète de 32kb (1024x32) a été soumise à fabrication en 28 FDSOI. Ce circuit embarque une solution de test (BIST) capable de fonctionner sous 300mV d’alimentation. Après une introduction générale, le 2ème chapitre du manuscrit décrit l’état de l’art. Le chapitre 3 présente les nouveaux points mémoire. Le 4ème chapitre décrit l’amplificateur de lecture avec la solution de réplication. Le chapitre 5 présente l’architecture d’une mémoire ultra basse tension ainsi que le circuit de test embarqué. Les travaux ont donné lieu au dépôt de 4 propositions de brevet, deux conférences internationales, un article de journal international est accepté et un autre vient d’être soumis
Emergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal

The use of SMPS (Switched mode power supply) in embedded systems is continuously increasing. The technological requirements of these systems include simultaneously a very good voltage regulation and a strong compactness of components. SEPIC ( Single-Ended Primary Inductor Converter) is a DC/DC switching converter which possesses several advantages with regard to the other classical converters. Due to the difficulty in control of its 4th-order and non linear property, it is still not well-exploited. The objective of this work is the development of successful strategies of control for a SEPIC converter on one hand and on the other hand the effective implementation of the control algorithm developed for embedded applications (FPGA, ASIC) where the constraints of Silicon surface and the loss reduction factor are important. To do it, two non linear controls and two observers of states and load have been studied: a control and an observer based on the principle of sliding mode, a deadbeat predictive control and an Extended Kalman observer. The implementation of both control laws and the Extended Kalman observer are implemented in FPGA. An 11-bit digital PWM has been developed by combining a 4-bit Δ-Σ modulation, a 4-bit segmented DCM (Digital Clock Management) phase-shift and a 3-bit counter-comparator. All the proposed approaches are experimentally validated and constitute a good base for the integration of embedded switching mode converters

碩士
義守大學
資訊工程學系碩士班
98
This thesis presents a high efficiency AC-DC power module suitable for embedded x86 system. The total output power of the module is 180W. A forward power switching circuit is used to supply the main power. A synchronous buck technology is used to supply two sets of power (+5V/8A and +3.3V/8A) in the secondary-side. The flyback converter is used to supply the power (+5V/1.5A) when the system is in the standby mode. Compared to the traditional power supply, this architecture not only increases the overall efficiency of the module but also reduces the cost and volume of the module.

碩士
國立雲林科技大學
電子工程系
106
In recent years, advances in integrated circuit manufacturing processes have led to the continuous shrinkage of transistors, which has increased the density of MOS transistor per unit area, and the operating speed has continuously increased. As a result, the power density of the system chip has become higher and higher, and the operating temperature of the chip has increased. In general, an integrated circuit chip easily causes malfunction or crash in a high-temperature environment. In addition to effective heat dissipation, more and more embedded temperature sensing circuits are used in the system chip to sense the temperature and monitor the temperature in real time, and the overheat protection circuit is used to achieve the normal operation of the chip. Therefore, this thesis focuses on the issue of chip temperature sensing and studies the embedded sensing circuit. Embedded temperature sensors are analyzed from the literature the imbedded temperature sensors classified as analog and digital types depending on the circuit style. The analog temperature sensor, although it has a good temperature sensing response and excellent resolution, the analog circuit is not easy to migrate in a different process, and the analog temperature sensing circuit integrated into the digital system will also have some difficulties. Therefore, this thesis also studies the simpler all-digital temperature sensor applied to the digital system. The literature on digital temperature sensors can be divided into delay type and ring type temperature sensors. From the literature study, it is known that ring oscillators are simple and small in the area when used as temperature sensor components, and are suitable for digital embedded system chip designs. However, ring-oscillating temperature sensors are very susceptible to fluctuations in the supply voltage and increase the error in temperature sensing. The ring-oscillating temperature sensor is susceptible to the supply voltage. This thesis proposes an all-digit differential delay cell circuit with supply voltage variation and negative feedback compensation to instantly compensate for the slight change in voltage. The proposed ring-oscillating temperature sensor only reacts to the output oscillation frequency when the temperature changes. In this thesis, when the delayed cell element connected to a ring oscillator, the temperature can sense temperature changes by quantifying the oscillation frequency. This circuit simulated in a 0.18μm CMOS process. The temperature range is 0°C~100°C, and the temperature resolution is 0.1°C. The supply voltage is 1.8V±10%, and the voltage variation sensitivity is as low as 0.016MHz. /mV, compared to the traditional differential ring oscillator, the voltage sensitivity can be improved by up to 90%.

碩士
國立清華大學
產業研發碩士積體電路設計專班
98
Charge pump circuits (CPCs) are commonly used for pumping charge upward to produce higher than the regular supply voltage or downward to negative voltage on a chip, and have been widely used in non-volatile memories (NVMs) for many years since the NVMs require a high voltage to program floating-gate devices. Power integrity has become more important as scaling down the supply voltage in SOC designs, the largest power noise and ground bounce occur in high voltage generator as CPC for embedded NVMs such as Flash memory, OTP and EEPROM since periodical switching clock s cause serious power peak current and suffer inductive effect on package bond wire. Suppressing power peak current (PPC) is the most key point for a low noise design. This study proposes new 4-phase with distributed local control scheme that each charge pump module operates not at the same time, therefore the peak current would be degraded and switching power noise due to dI/dt is greatly reduced The Low Noise Charge Pump (LNCP) is fabricated in 90nm CMOS technology. The measurement results demonstrate that the power noise can be reduced more than 60% from 10MHz to 16.7MHz and better power efficiency about 7% comparing to conventional 4-phase CP with less than 3% area penalty. Moreover, LNCP can be achieved to high speed with new 4-phase clock control in the future.

碩士
雲林科技大學
電子與資訊工程研究所
98
With SoC and System in Package SiP, the density of transistor on IC has being increased, and heat problem in the operating chip has become more critical. For this reason, in addition to the passive heat dissipation enhancement in high density VLSI chip, active temperature monitoring and further power management is more considerable. For future high-performance chips, both active and passive protections are necessary for preventing IC from errors due to the rising temperature, or even resulting in damage. Moreover, there are more functional blocks and wider temperature distribution inside larger ICs. The application of multi-point temperature sensing system in these ICs, therefore, is to monitor temperature change between dies in SiP according to different functional blocks. A monitoring system with all digital multi-point temperature can effectively reach the purpose of monitoring, and that has come to preliminary results in our laboratory. According to our previous work, it is found that the temperature sensing circuits based on ring oscillator have the advantage of small area. Nonetheless, except the reaction to temperature change, the oscillated frequency is also sensitive to the fluctuation in power supply voltage. Taking traditional single-ended ring oscillator as the example, if there is ±10% fluctuation in power supply voltage, the change of oscillated frequency is up to ±12%; and, if it responds to temperature, the error will be over 50℃. To solve the problem, the differential ring oscillator in latch compensation system is applied into this thesis so as to overcome the problem of power supply voltage fluctuation affecting oscillator frequency but not to reduce the sensitivity to temperature in the oscillator. In this case, this thesis aims to design a temperature sensor with all digital and power supply voltage fluctuation immunization. Besides, the timing between the temperature sensor and temperature monitoring system is re-designed to improve the stability of previously studied and developed bi-directional signal transmission system. The circuits in this thesis are simulated with tsmc 90nm Mixed-Signal SALICIDE (1P9M, 1.0V/3.3V) technology with the temperature resolution 0.08℃, sampling rate 6.1K samples/sec., temperature measurement range 0℃~100℃, the highest power dissipation 30.14μW, and the consume energy 4.9nJ of the temperature sensing system completing a temperature sampling. Under the condition of DC power supply voltage 1V with ±10% amplitude fluctuation, the average temperature error is only ±1℃, whose improvement has reached 98% in comparison with the error of traditional differential ring oscillator being 50℃ in average. The circuits in this thesis are implemented with tsmc 0.18μm Mixed-Signal SALICIDE（1P6M, 1.8V/3.3V）technology. A temperature sampling system and two sets of temperature sensing circuits are included in the circuit layout, where the area of the temperature monitoring system circuits is only 0.0151mm2 and the circuit area of each set of temperature sensor is 0.0061 mm2.

碩士
國立清華大學
電機工程學系
99
In recent years, portable devices such as media player, digital camera, smart phone, and tablet, are developed greatly. Non-volatile memories are used generally because these devices are not always turned on. Embedded non-volatile memories require a high voltage to attract electrons into the floating gate and an enough current to finish program operation in recent SoCs. Charge pump circuit is used in these chips to generate the high voltage. The supply voltage becomes lower and lower with more advanced process, but the high voltage can’t decrease because of endurance. Besides, the operating time is a very important specification for portable devices and using green power is the trend in future. Reducing supply voltage to 0.5V can fit these requirements. Traditional charge pumps can’t generate enough voltage and current and become slow and large at low supply voltage. In this work, we propose different structure and use hybrid devices with four-phase clock signals. The proposed circuit generates the first boosted voltage by clock pump and provides pumped clocks to main pump through level shifters. ALL blocks except main pump can use standard devices to reduce area because the first boosted voltage is only 1V. The low voltage charge pump was fabricated in UMC 90nm 1P9M process. It can meet the same specification at 0.5v supply voltage by measuring result. The structure can save about 15% area at the same voltage. Its speed at low voltage is almost equal to traditional pump at 1V. ALL of our goals are achieved.

With growing connectivity in the modern era, the risk of encrypted data stored in hardware being exposed to third-party adversaries is higher than ever. The security of encrypted data depends on the secrecy of the stored key. Conventional methods of storing keys in Non-Volatile Memory have been shown to be susceptible to physical attacks. Physically Unclonable Functions provide a unique alternative to conventional key storage. SRAM PUFs utilize inherent process variation caused during manufacturing to derive secret keys from the power-up values of SRAM memory cells. This thesis analyzes the effect of supply ramp-up times on the reliability of SRAM PUFs. We use SPICE simulations as the platform to observe the effect of supply ramp times at the circuit level using carefully controlled supply voltages during power-up. We also measure the effect of supply ramp times on commercially available SRAM ICs by performing reliability and uniqueness measurements on two commercial SRAM models. Finally, a hardware implementation is proposed in a commercial 16nm FinFET technology to establish the design flow for taping out a custom SRAM IC with separated peripheral and core power supplies that would allow for experimental evaluation of sequenced power supplies on the SRAM PUF.

碩士
國立交通大學
電機工程學系
102
In recent years, rapid growth of the semiconductor technology and electronic devices continuously enriches our daily life. Conventional single-function products gradually fade out from the market because those cannot satisfy the consumers’ expectations anymore. Especially for the portable devices such as smart phones and tablet PCs, power management integrated circuits (PMICs) become an essential block to deal with the various requirements from different circuits on silicon chips. This thesis focuses on digital low dropout regulator designs. Low-power, high power supply rejection (PSR), and capable of working under low-voltage environment power management module can be achieved through deliberated circuit designs. In general, most of analog low dropout regulators rely on the negative feedback mechanism to stabilize the output voltage. To make analog circuit working properly, the input voltage needs a relative high level. Taking the CMOS technologies as an example, when the input voltage falls below one volt, several stacking architectures like cascode stages are no longer useful. Biasing scheme becomes extremely difficult and therefore it increases the design effort. Besides, with the progress of the logic/mix-mode technologies, the ratio of transistor threshold voltage to nominal supply gradually increases. The supply voltage is also decreased to prevent the device from being damaged in deep sub-micron and nano-scale technologies. This trend forces us to consider the impact of the process evolution during the design jobs. This thesis proposes a resistance-locked loop embedded digital low dropout regulator to improve the PSR in advanced CMOS technologies. The bidirectional asynchronous wave pipeline architecture doesn’t need the external clock reference and thus the quiescent current can be minimized in steady-state. Moreover, the controller can work under a very lower input voltage. The ratio of the output voltage to input supply can be improved to avoid unnecessary loss. As for the resistance locked loop, it helps the output node free from noise generated by the switching regulator, providing a high quality output for the loading. The test chip was fabricated in UMC 40nm low-power CMOS process. Experimental results show a 77% noise suppression. The minimum supply voltage can be down to 0.6V and a 0.4 V regulated output can be guaranteed.

碩士
國立政治大學
企業管理研究所(MBA學位學程)
106
Because of the characteristics of long product life cycle of embedded industry, it requires stable quality performance and long-term supply, this will differentiate the supply chain strategy from consumer electronics industry. As this study focus on a private brand project of the company, it has applied some knowledge sharing methodologies such as e-commerce and online communities, it would be worth to explore and implications of supply chain management. This study examines the impact of supply chain integration on supply chain performance. In the literature review, the facets of supply chain integration are divided into three aspects: suppliers, customers, and internal integration combined with the supply chain management mentioned in the literature and linked to the performance evaluation indicators in the SCOR model. The above review brings out the supply chain integration method which will be discussed in this study. This study uses a qualitative case interview method to investigate the embedded brand company's own brand product line, and explores the positive effect of supply chain integration on the supply chain performance in project management scope. This study finds that in the project management, in addition to the supply chain integration mentioned in the research framework, the supply chain integration in practice guided by each functional unit has a positive impact on performance. In the conclusion, the study focused on three different supply chain integration facets, collated the direct and indirect impacts of SCOR performance indicators in the supply chain integration method, and providing the corresponding suggestion in the conclusions.

碩士
國立臺灣大學
電信工程學研究所
101
To alleviate the limitations imposed on CMOS technique, some design techniques are developed for CMOS millimeter-wave integrated circuits, such as frequency synthesizer, frequency doubler and voltage-controlled oscillator in this thesis. In chapter 2, alow power Ka-bandfrequency synthesizer is presented and with good bandwidth for CMOS RF frontends circuits. The circuit employs a transformer-feedback voltage-controlled oscillator and an injection-locked frequency divider, so it can achieve low power design and possess a good bandwidth specification. In this chapter, we also focus on the study and analysis of the Ka-band frequencysynthesizer closed loop design and the phase noise consideration, and we also focus on the design and analysis of the subcircuits, such as voltage-controlled oscillator, injection-locked frequency divider, CML divider, multi-modulars divider and charge pump, etc. In chapter 3, a low power 24GHz quasi-injection-locked voltage-controlled oscillator is proposed. The circuit using a novel design methodology about the loop gain achieves wide bandwidth property and is applicable to the wide bandwidth RF system.In this chapter, a theoreticalanalysis for quasi-injection-locked technique and the comparison between the conventional injection locking are accomplished. This circuit employs a paralleled capacitor to suppress unwanted harmonic signals and embedded an on-chip Marchand balun to translate a single-ended signal to a differential input signal. In chapter 4, a supply-regulated transformer-feedback-complementary VCO with adjustable regulator embedded is proposed. By tuning the resistor in the feedback network, the VCO can have frequency tuning mechanism without using tuning varactors. Because of without using the tuning varactors, which are low quality factor device, and the regulator possessing the supply-regulated property against the noise, the VCO would have better phase noise performance. In order to have high F.o.M. performance, the complementary VCO adopts the three-coil transformer-feedback to have low dc power comsumption while maintaining good phase noise performance. Chapter 1 and chapter 5 are the introduction and the conclusion about this thesis, respectively.

In this work, power supply noise contribution, at a particular node on the power grid, from clock/power gated blocks is maximized at particular time and the synthetic gating patterns of the blocks that result in the maximum noise is obtained for the interval 0 to target time. We utilize wavelet based analysis as wavelets are a natural way of characterizing the time-frequency behavior of the power grid. The gating patterns for the blocks and the maximum supply noise at the Point of Interest at the specified target time obtained via a Linear Programming (LP) formulation (clock gating) and Genetic Algorithm based problem formulation (Power Gating).

This is the thirteenth workshop to be organised under the postgraduate programmes in electrical and electronic engineering (EEE). In total, twenty-nine papers, divided into eight themes, comprise the Proceedings.

A dissertation submitted to the Faculty of Engineering and the Built Environment, University of the Witwatersrand, Johannesburg, in fulfilment of the requirements for the degree of Master of Science in Engineering, 2016
The water-energy nexus considers the relationship between water and energy resources. Increases in environmental degradation and social pressures in recent years have necessitated the development of manufacturing processes that are conservative with respect to both these resources, while maintaining financial viability. This can be achieved by process integration (PI); a holistic approach to design which emphasises the unity of processes. Within the realm of PI, water network synthesis (WNS) explores avenues for reuse, recycle and regeneration of effluent in order to minimise freshwater consumption and wastewater production. When regeneration is required, membrane-based treatment processes may be employed. These processes are energy intensive and result in a trade-off between water and energy minimisation, thus creating an avenue for optimisation. Previous work in WNS employed a black box approach to represent regenerators in water minimisation problems. However, this misrepresents the cost of regeneration and underestimates the energy requirements of a system. The aim of the research presented in this dissertation is to develop an integrated water regeneration network synthesis model to simultaneously minimise water and energy in a water network. A novel MINLP model for the design of an electrodialysis (ED) unit that is capable of treating a binary mixture of simple salts was developed from first principles. This ED model was embedded into a water network superstructure optimisation model, where the objective was to minimise freshwater and energy consumption, wastewater productions, and associated costs. The model was applied to a pulp and paper case study, considering several scenarios. Global optimisation of the integrated water network and ED design model, with variable contaminant removal ratios, was found to yield the best results. A total of 38% savings in freshwater, 68% reduction in wastewater production and 55% overall cost reduction were observed when compared with the original design. This model also led to a 80% reduction in regeneration (energy) cost.
GS2016