Thèses sur le sujet « Successione digitale »
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1
La, Russa Francesco. « La successione mortis causa nel c.d. patrimonio digitale ». Doctoral thesis, Università degli studi di Padova, 2018. http://hdl.handle.net/11577/3425380.
Texte intégralRésumé :
Study of inheritance profiles of digital assets disseminated on the internetL'elaborato indaga circa i profili successori dei beni c.d. digitali diffusi su internet, interrogandosi anzitutto sul diritto applicabile, sulla natura dei beni predetti, per giungere ad una rivisitazione dei principi generali dell'istituto della successione per causa di morte in applicazione ai nuovi tipi di beni (c.d. digitali diffusi su internet).
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Radhakrishnan, Ram Harshvardhan. « Accelerated Successive Approximation Technique for Analog to Digital Converter Design ». OpenSIUC, 2015. https://opensiuc.lib.siu.edu/theses/1630.
Texte intégralRésumé :
This thesis work presents a novel technique to reduce the number of conversion cycles for Successive Approximation register (SAR) Analog to Digital Converters (ADC), thereby potentially improving the conversion speed as well as reducing its power consumption. Conventional SAR ADCs employ the binary search algorithm and they update only one bound, either the upper or lower bound, of the search space during one conversion cycle. The proposed method, referred to as the Accelerated-SAR or A-SAR, is capable of updating both the lower and upper bounds in a single conversion cycle. Even in cases that it can update only one bound, it does more aggressively. The proposed technique is implemented in a 10-bit SAR ADC circuit with 0.5V power supply and rail-to-rail input range. To cope with the ultra-low voltage design challenge, Time-to-Digital conversion techniques are used in the implementation. Important design issues are also discussed for the charge scaling array and Voltage Controlled Delay Lines (VCDL), which are important building blocks in the ADC implementation.
3
David, Christopher Leonidas. « All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters ». Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-dissertations/194.
Texte intégralRésumé :
The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.
4
Barton, Patrick Randal. « A synthesis program for CMOS successive approximation A/D and D/A converters ». Thesis, Georgia Institute of Technology, 1986. http://hdl.handle.net/1853/15347.
Texte intégral
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Yang, Kun. « A 16 Bit 500KSps low power successive approximation analog to digital converter ». Pullman, Wash. : Washington State University, 2009. http://www.dissertations.wsu.edu/Thesis/Fall2009/k_yang_111809.pdf.
Texte intégralRésumé :
Thesis (M.S. in electrical engineering)--Washington State University, December 2009.Title from PDF title page (viewed on Feb. 9, 2010). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 42-43).
6
Mahsereci, Yigit Uygar. « A Successive Approximation Register Analog-to-digital Converter For Low Cost Microbolometers ». Master's thesis, METU, 2012. http://etd.lib.metu.edu.tr/upload/12614031/index.pdf.
Texte intégralRésumé :
Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test electronics. Imaging ADCs are optimized only for the specific application in order to achieve the lowest power, yet the highest performance.
The successive approximation architecture is chosen, due to its low-power, small-area nature, high resolution potential, and the achievable speed, as the ADC needs to support a 160x120 imager at a frame rate of 25 frames/sec (fps). The resolution of the ADC is 14 bit at a sampling rate of 700 Ksample/sec (Ksps). The noise level is at the order of 1.3 LSBs. The true resolution of the ADC is set to be higher than the need of the current low-cost microbolometers, so that it is not the limiting factor for the overall noise specifications. The design is made using a 0.18µm CMOS process, for easy porting of design to the next generation low-cost microbolometers. An optional dual buffer approach is used for improved linearity, a modified, resistive digital-to-analog converter (DAC) is used for enhanced digital correction, and a highly configurable digital controller is designed for on-silicon modification of the device. Also, a secondary 16-bit high performance ADC with the same topology is designed in this thesis. The target of the high resolution ADC is low speed sensors, such as temperature sensors or very small array sizes of infrared sensors. Both of the SAR ADCs are designed without switched capacitor circuits, the operation speed can be minimized as low as DC if an extremely low power operation is required. A compact test setup is designed and implemented for the ADC. It consists of a custom designed proximity card, an FPGA card, and a PC. The proximity card is designed for high resolution ADC testing and includes all analog utilities such as voltage references, voltage regulators, digital buffers, high resolution DACs for reference generation, voltage buffers, and a very high resolution &Delta
-&Sigma
DAC for input voltage generation. The proximity card is fabricated and supports automated tests, because many components surrounding the ADC are digitally controllable. The FPGA card is selected as a commercially available card with USB control. The full chip functionalities and performances of both ADCs are simulated. The complete layouts of both versions are finished and submitted to the foundry. The ADC prototypes consist of more than 7500 transistors including the digital circuitry. The power dissipation of the 16-bit ADC is around 10mW, where the 14-bit device consumes 30mW. Each of the dies is 1mm x 5mm, whereas the active circuits occupy around 0.5mm x 1.5mm silicon area. These chips are the first steps in METU for the realization of the digital-in digital-out low cost microbolometers and low cost sensors.
7
Sekar, Ramgopal. « LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS ». OpenSIUC, 2010. https://opensiuc.lib.siu.edu/theses/350.
Texte intégralRésumé :
In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC design techniques, which are: 1) Low-power SAR-ADC design with split voltage reference, 2) Charge recycling techniques for low-power SAR-ADC design, 3) Low-power SAR-ADC design using two-capacitor arrays, 4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show that significant power reduction can be achieved by using the developed techniques. In addition, design issues such as area overhead, design complexity associated with the proposed low-power techniques are also discussed in the thesis.
8
Swindlehurst, Eric Lee. « High-Speed and Low-Power Techniques for Successive-Approximation-Register Analog-to-Digital Converters ». BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8923.
Texte intégralRésumé :
Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications. The proposed 8-bit, 10-GHz, 8× time-interleaved SAR ADC utilizes a constant-matching DAC with symmetrically grouped unit finger capacitors to maximize speed by reducing the total DAC capacitance to 32 fF and minimizing the bottom plate parasitic capacitance. The capacitance reduction also saves power as both the DAC size and the driving logic size are reduced. An optimized asynchronous comparator loop and smaller driver logic push the single channel speed of the SAR ADC to 1.25 GHz, thus minimizing the total number of timeinterleaved channels to 8 to reach 10 GHz. A dual-path bootstrapped switch improves the spurious-free dynamic range (SFDR) of the sampling by creating an auxiliary path to drive the non-linear N-well capacitance apart from the main signal path. Using these techniques, the ADC achieves a measured signal-to-noise-and-distortion ratio (SNDR) and SFDR of 36.9 dB and 59 dB, respectively with a Nyquist input while consuming 21 mW of power. The ADC demonstrates a record-breaking figure-of-merit of 37 fJ/conv.-step, which is more than 2× better than the next best published design, among reported ADCs of similar speeds and resolutions.
9
Chan, Ka Yan. « Applying the "split-ADC" architecture to a 16 bit, 1 MS/s differential successive approximation analog-to-digital converter ». Worcester, Mass. : Worcester Polytechnic Institute, 2008. http://www.wpi.edu/Pubs/ETD/Available/etd-043008-164352/.
Texte intégral
10
Parsons, Colton A. « Variable Precision Tandem Analog-to-Digital Converter (ADC) ». DigitalCommons@CalPoly, 2014. https://digitalcommons.calpoly.edu/theses/1255.
Texte intégralRésumé :
This paper describes an analog-to-digital signal converter which varies its precision as a function of input slew rate (maximum signal rate of change), in order to best follow the input in real time. It uses Flash and Successive Approximation (SAR) conversion techniques in sequence.
As part of the design, the concept of "total real-time optimization" is explored, where any delay at all is treated as an error (Error = Delay * Signal Slew Rate). This error metric is proposed for use in digital control systems. The ADC uses a 4-bit Flash converter in tandem with SAR logic that has variable precision (0 to 11 bits). This allows the Tandem ADC to switch from a fast, imprecise converter to a slow, precise converter. The level of precision is determined by the input’s peak rate of change, optimized for minimum real-time error; a secondary goal is to react quickly to input transient spikes.
The implementation of the Tandem ADC is described, along with various issues which arise when designing such a converter and how they may be dealt with. These include Flash ADC inaccuracies, rounding issues, and system timing and synchronization.
Most of the design is described down to the level of logic gates and related building blocks (e.g. latches and flip-flops), and various logic optimizations are used in the design to reduce calculation delays. The design also avoids active analog circuitry whenever possible – it can be almost entirely implemented with CMOS logic and passive analog components.
11
Brenneman, Cody R. « Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter ». Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-theses/423.
Texte intégralRésumé :
As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter.
12
DESAI, VANDANA. « TRANSISTOR-LEVEL SIMULATION OF A NOVEL CMOS BINARY SEARCH BASED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER CIRCUIT ». University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1148305344.
Texte intégral
13
Zhang, Dai. « Design and Evaluation of an Ultra-Low Power Successive Approximation ADC ». Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.
Texte intégralRésumé :
Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system. Usually, low power consumption is required for a long battery lifetime. In such application which requires low power consumption and moderate speed and resolution, one of the most prevalently used ADC architectures is the successive approximation register (SAR) ADC.This thesis presents a design of an ultra-low power 9-bit SAR ADC in 0.13μm CMOS technology. Based on a literature review of SAR ADC design, the proposed SAR ADC combines a capacitive DAC with S/H circuit, uses a binary-weighted capacitor array for the DAC and utilizes a dynamic latch comparator. Evaluation results show that at a supply voltage of 1.2V and an output rate of 1kS/s, the SAR ADC performs a total power consumption of 103nW and a signal-to-noise-and-distortion ratio of 54.4dB. Proper performance is achieved down to a supply voltage of 0.45V, with a power consumption of 16nW.
14
Kotti, Vivek. « Design of an 8-bit Successive Approximation Pipelined Analog to Digital Converter (SAP-ADC) in 90 nm CMOS ». Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright1503596547020087.
Texte intégral
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BHOOPATHY, MANIVANNAN. « EXPLOITING A MULTI-LEVEL MODELING TECHNIQUE WITH APPLICATION TO THE ANALYSIS OF A SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER ». University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1132016200.
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VALLARIELLO, VALENTINA. « Disposizioni testamentarie a contenuto non patrimoniale e nuove tecnologie informatiche ». Doctoral thesis, 2017. http://hdl.handle.net/2158/1103382.
Texte intégralRésumé :
La presente trattazione, prendendo le mosse da un'attenta analisi della successione testamentaria, si è proposta di mettere in luce le istanze di rinnovamento che negli ultimi tempi hanno spinto la dottrina e l'interprete a cercare di trovare delle possibili alternative contrattuali al testamento, quest'ultimo ritenuto dai più inadeguato a rispondere alle mutate condizioni sociali. In questa prospettiva è apparso significativo interrogarsi preliminarmente sulla natura del testamento, per poi procedere ad un'analisi dello stesso sotto il profilo dei contenuti. In particolare ci si è voluti concentrare sulla verifica dell'ammissibilità di un contenuto atipico a carattere non patrimoniale anche nell'ipotesi di successione mortis causa aventi ad oggetto files o dati digitali contenuti in spazi virtuali ovvero server remoti (il c.d. cloud). Più nello specifico, in un'ottica di revisione del diritto delle successioni, sono state messe in luce tutte le potenzialità connaturate agli atti di ultima volontà. Invero, prendendo le mosse dalla teoria patrimoniale del testamento e dunque dalla ripartizione tra disposizioni testamentarie a contenuto patrimoniale e disposizioni a contenuto non patrimoniale e considerando che l'ordinamento italiano contempla numerose ipotesi di atti di ultima volontà diversi dal testamento, si è giunti alla conclusione di ritenere che taluni interessi esistenziali post mortem della persona non reclamino necessariamente un testamento, ma possono trovare una collocazione anche all'interno della categoria degli atti di ultima volontà. È stato possibile ipotizzare che in un prossimo futuro la successione nel patrimonio digitale divenga regolata attraverso atti di ultima volontà non formali, ma perfettamente validi in ambito digitale.
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« Self-Calibration And Digital-Trimming Of Successive Approximation Analog-To-Digital Converters ». Doctoral diss., 2014. http://hdl.handle.net/2286/R.I.25930.
Texte intégralRésumé :
abstract: Several state of the art, monitoring and control systems, such as DC motor
controllers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.Dissertation/Thesis
Doctoral Dissertation Electrical Engineering 2014
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Hsieh, Tsung-Yin, et 謝宗殷. « A Digital Calibration Scheme for the Successive Approximation Analog-to-Digital Converter ». Thesis, 2009. http://ndltd.ncl.edu.tw/handle/45094349459182745945.
Texte intégralRésumé :
碩士國立交通大學
電機與控制工程系所
97
It is the mismatched capacitors due to process variation that mainly limit the resolution of conventional SAR ADCs. To address this issue, this thesis proposes a novel calibration scheme for SAR ADCs. The proposed calibration scheme first estimates the ratio errors of the capacitors under calibration in the weighted capacitive array. Then, the errors will be digitized and stored. During the normal conversion of SAR ADCs, the corresponding error code of every ADC’s output will be calculated according to the stored error codes. Finally, the error code will be compensated in digital domain. With the proposed calibration scheme, the resolution of the SAR ADC can be enhanced. The hardware overhead consists of several capacitors and a few of switches in addition to the digital function blocks. Since the proposed calibration scheme estimates and calibrates the errors digitally, it is very robust, low-power, and can be easily ported to advanced technologies. In practical implementation, only one reference voltage is necessary no matter the capacitor errors are positive or negative. Comparing with the state-of-the-art calibration schemes which require precisely symmetric dual reference voltages to handle the signed errors, the proposed calibration scheme is more practical and low-cost. We implemented a 1-V SAR ADC with the proposed calibration scheme in TSMC 0.18μm 1P6M CMOS process. Measurement results show that the SAR ADC can operate faster and has a wider effective resolution bandwidth after calibration. The DNL and INL values are enhanced from -1~+18 LSB and -8~+18 LSB to -1~+9 LSB and -6~+9 LSB after calibration. With the same input, the SNDR of the ADC can have up to 5dB improvement after calibration. It corresponds to around an additional effective number of bit (ENOB). The ADC consumes less than 20μW at 1-V.
19
Lin, Jhao-Huei, et 林昭輝. « All Digital Capacitance Calibration for Successive-Approximation Register Analog-to-Digital Converter ». Thesis, 2018. http://ndltd.ncl.edu.tw/handle/btzwa7.
Texte intégralRésumé :
碩士國立臺灣大學
電子工程學研究所
106
This thesis presents a 12-bit 1 MS/s high power-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with 0.7V supply voltage. By using detect-and-skip (DAS) algorithm, the capacitive digital-to-analog converter (DAC) switching power can be reduced. To be more power-efficient, the unit capacitance can shrink to decrease the DAC switching power largely. There is a bottleneck of weight compensation when the ADC takes the DAS algorithm to switch DAC. The weight-split compensation (WSC) can overcome this bottleneck perfectly. In the calibration mode, the reconfigurable redundancy can resolve the problem of the comparator offset. In addition, the Vcm-based tracking switching can enhance the resolution to decrease the calibration converge time. The propose ADC is fabricated using a 40-nm CMOS process. It consumes 2.47 W from a 0.7-V supply at a conversion-rate of 1 MS/s. After foreground calibration, the measured DNL and INL are +0.61/-0.57 and +0.93/-0.92 LSB. The measured SNDR and SFDR are at 66.54 dB and 89.55 dB, respectively. The ENOB performance is 10.75 b, which is equivalent to a Walden and Schreier figure-of-merit of 1.47 fJ/conversion-step and 179.6 dB, respectively.
20
Coe, Matthew T. « Digital implementation of a mismatch-shaping successive-approximation ADC ». Thesis, 2001. http://hdl.handle.net/1957/31137.
Texte intégralRésumé :
Utilizing a two-capacitor topology, the digital implementation of an audio-band
successive-approximation analog-to-digital converter (ADC) is explored in the
context of mismatch-shaping where the mismatch estimates are accurate to the first
order. A second-order ����� loop was found to be effective in system simulations
given a 0.1% capacitor mismatch. Spectral analysis of the ADC shows dramatic
improvements in total harmonic distortion as well as 87 dB SNDR (signal to noise
and distortion ratio) for an oversampling ratio of 10.Graduation date: 2002
21
Liao, Bo-Shi, et 廖柏詩. « Power-Efficient Successive-Approximation Register Analog-to-Digital Converter ». Thesis, 2016. http://ndltd.ncl.edu.tw/handle/88290005656371369947.
Texte intégralRésumé :
碩士國立臺灣大學
電子工程學研究所
104
Today analog to digital converter (ADC) plays an important role in electronic systems. It is a bridge between nature analog environment and digital world. Recently requirement of low power application grows gradually, especially in wireless communication, sensor network and biomedical system. As the result, how to decrease the power dissipation of ADC become big issues. In different types of ADC, successive approximation register (SAR) ADC does not have op-amplifier and most blocks are only digital circuits, so SAR ADC can achieve the low power specification. In the field of low power SAR ADC, an 12-bit 10MS/s single-channel SAR and 7-bit 2GS/s calibration-free time-interleaved ADC are presented. This thesis first proposes an energy-efficient high resolution SAR ADC with small unit capacitance and simple controller logic. In order to save digital power, it combined with arbitrary capacitor array, which tolerates errors of dynamic offset and capacitor settling in MSBs during conversion and a differential control logic circuit are proposed to decrease the circuit complexity. The technique are verified by TSMC 1P6M3X1Z1U 40nm Low Power CMOS process. This work operates at 10MS/s in 0.9V supply voltage. Its power dissipation is only 36.9μW and gets 10.05 bit ENOB performance after off-chip calibration with low-frequency input. As the result, the peak FoM performance is 3.48fJ/conversion-step. In the second design, in order to solve offset mismatch, an offset-compensation algorithm is proposed. It transforms offset mismatch to nonlinearity, and creates redundancy range to compensate it. In addition, a front-end track-and-hold circuit is implemented in order to eliminate time skew mismatch. This time-interleaved ADC in 55nm CMOS technology post-simulation achieves an ENOB of 6.8 and consumes 24.8mW. It results in a FoM of 117fJ/conversion-step.
22
Santos, Bruno Emanuel Silva Moreira. « A herança digital e a transmissão de conteúdos digitais em vida ». Master's thesis, 2016. http://hdl.handle.net/1822/50273.
Texte intégralRésumé :
Dissertação de mestrado em Direito e InformáticaCom a modernização tecnológica surgiram novos bens de que cada indivíduo pode ser titular. Nomeadamente, bens em formato digital, aos quais a legislação vigente precisa de dar resposta de modo a conferir segurança jurídica aos seus titulares. Ora, estes conteúdos digitais necessitam de ver regulada a sua transmissibilidade quer em vida, quer em morte. Sendo esse o âmbito de análise desta dissertação de mestrado. Com efeito, numa primeira parte deste trabalho será analisado o Direito Sucessório Português com o intuito de compreender o que se enquadra no âmbito de uma sucessão, quais os direitos que poderão ser transmitidos por morte do seu titular, e quem poderão ser os destinatários desses direitos, ou seja, quem serão os sucessores de uma pessoa falecida. De igual forma, nesta parte inicial será ainda abordado o tema da preservação digital com vista a compreender como pode ser mantida a acessibilidade dos conteúdos digitais à medida que os meios tecnológicos evoluem e estes sofrem desatualizações. Sendo realçado o papel vital que esta preservação terá na transmissão dos conteúdos digitais, tanto em vida como em morte. Por sua vez, na segunda parte desta dissertação irão ser procuradas as respostas jurídicas para duas questões fundamentais. Em primeiro lugar, procurará entender-se como podem os conteúdos digitais ser transmitidos em vida pelo seu titular, particularmente através de negócio jurídicos, quer onerosos, quer gratuitos (doações). Para tal será tomado em consideração o importante papel da autonomia privada no âmbito dos negócios jurídicos, bem como o seu corolário no princípio da liberdade contratual. Por último, pretende-se que seja analisada a possibilidade de existência de uma Herança Digital em função das disposições jurídicas vigentes no ordenamento jurídico português. Desse modo, será analisada a sua admissibilidade legal, subdividindo-se os conteúdos digitais entre aqueles que têm valor patrimonial e aqueles que são insuscetíveis de avaliação económica. Sendo também contemplada a possibilidade de realização de um testamento sobre este tipo de conteúdos. Finalmente, será realizada uma comparação com outros ordenamentos jurídicos, com particular destaque para países como o Brasil e os EUA.
With the modernization of technology, individuals have acquired new personal goods, in particular digital properties. The existence of these confirms the urgent need of the current legislation to give a response that grants juridical safety to their owners. Accordingly, these digital goods need a regulation for their transmissibility, either during their owners’ life or in death. That is the study subject of this Master’s Degree Dissertation. In the first part of this project, the Portuguese inheritance law will be analysed with the purpose of understanding what makes part of the succession range; which rights might be transmitted at the owners’ death and who may be the legal warden of those rights, i.e., who will be the successors of the deceased. The topic “digital preservation” will also be studied in the initial part of the thesis, with intuit of understanding how the accessibility of the digital goods can be kept, as the technological resources evolve and get out of date. Will be highlighted the vital role this preservation will have in the succession of the digital goods. In the second part, we are going to search for juridical answers to two fundamental issues. First, we are going to try to comprehend how digital properties can be transmitted during their owner’s life, particularly through contracts, either onerous or gratuitous (donations). Therefore, we are going to take into consideration the significant role of private autonomy in what concerns to contracts, as well as its corollary that results into the principle of contractual freedom. Finally, the possible existence of a Digital Inheritance is going to be scrutinized in the light of the current juridical provisions, in the legal system. Thus, the Digital Inheritance legal admissibility is going to be analysed, dividing up the digital goods into those which have patrimonial value and those which are not object of an economical estimate. Moreover, the possibility of making a will that includes these digital goods is also going to be comprised. We are also going to compare the Portuguese legal system to others, mainly to the Brazilian and American ones, to what extends the Digital Inheritance.
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Yeh, Kun-Ming, et 葉昆明. « Low Power Successive Approximation Register Analog to Digital Converter Design ». Thesis, 2013. http://ndltd.ncl.edu.tw/handle/52219798851756448222.
Texte intégralRésumé :
碩士國立中興大學
電機工程學系所
102
This thesis presents the design of an analog to digital converter (ADC) with low power consumption, which is suitable for portable electronic applications powered by batteries such as mobile phone, digital camera, PDA, etc. To reduce power consumption of conversion, a successive approximation registers (SAR) analog to digital converter can be used. An eight-bit SAR ADC utilized binary search charge distribution digital to analog converter to increase the circuit linearity. To obtain both high speed and low power, latch only comparator and bootstrapped switch are used. The SAR ADC is designed and simulated by HSPICE with TSMC 0.18μm 1P6M 1.8V/3.3V Mixed Signal CMOS technology. The supply voltage of the 8-bit SAR ADC is 1.8V and the sampling rate is 5KHz. Its power consumption is 1100μW.
24
Huang, Guan-Ying, et 黃冠穎. « Design of Energy Efficient Successive-Approximation Analog-to-Digital Converter ». Thesis, 2007. http://ndltd.ncl.edu.tw/handle/6cut26.
Texte intégralRésumé :
碩士國立成功大學
電機工程學系碩博士班
95
In this thesis, two successive-approximation (SAR) analog-to-digital converters (ADCs) are proposed. In the first ADC, a novel RC time constant capacitor array, which adjusts the numbers of switch, is used to speed up the conversion rate. And a self timing controller is used to control the comparator, which can save half of the power consumption of the comparator. Simulation results of the first ADC, an 8-bit 27 MS/s SAR ADC, show that the total power consumption is 385 μW and the average energy consumption per conversion step is 105 fJ in the TSMC 0.13 μm process. In order to further increase the conversion rate, a novel capacitor array with passive charge-sharing (PCS) technique, which can effectively reduce the total power consumption and the input capacitance, is used in the second ADC. Simulation results of the second ADC, an 8-bit 50 MS/s PCS SAR ADC, show that the total power consumption is 294 μW and the average energy consumption per conversion step is 41 fJ in the TSMC 0.13 μm process.
25
Kao, Ching-Ya, et 高靖亞. « Low Dropout Regulator with Successive Approximation Analog to Digital Converter ». Thesis, 2013. http://ndltd.ncl.edu.tw/handle/77112625875388205251.
Texte intégralRésumé :
碩士淡江大學
電機工程學系碩士班
101
Abstract: Soc circuit will produce a non-ideal effect with process, supply voltage, and temperature, which cause the chip does not work or lead to damage to the chip in serious. And how to design a low power consumption of the circuit is an important issue. We will design a circuit which use of the successive approximation analog to digital converter to replace error amplifier. Therefore, this paper the target for the design of a low dropout linear regulator with successive approximation analog to digital converter architecture. There are several key considerations of low dropout linear regulator characteristic parameters: (1) The output voltage difference (△ V) (2) linear regulator with quiescent current (The Quiescent Current, Iq) rate (Line Regulation, LNR) (3 ) load Regulation (Load Regulation, LDR); these parameters has a close relationship with the load current, precision, settling time. The circuit can be divided into three parts, the first part of the 8-bit successive approximation analog-to-digital converter architecture, the second part is the switching of the power transistor, the last part is the comparator. Using the signal from SAR ADC to control the power transistor to achieve the output voltage, and reduce the quiescent current in the steady state. First, compare the input voltage and the original supply voltage to control the feedback resistor switching. Second, current changes will control turn on the power transistor or turn off the power transistor. The simulation results are based on 0.18μm CMOS process. The current efficiency is 99.94%. Moreover, the quiescent current of the circuit is 15.8μA in a heavy load condition.
26
Jiang, Ru Hui, et 江茹慧. « Low Dropout Regulator for Successive Approximation Analog to Digital Converter ». Thesis, 2016. http://ndltd.ncl.edu.tw/handle/11364419615243477868.
Texte intégralRésumé :
碩士國立清華大學
電機工程學系
104
Low Dropout Linear Regulator has been widely used in a variety of 3C products, especially the popular portable electronic products in recent years, where extending battery life is the most important thing.Since there are many different modules on electronic circuit, so they need a variety of voltage levels of the DC supply voltage. Thus, the circuit of a system required use multiple voltage regulator circuit, voltage regulator IC plays a very important roles in the performance and stability characteristics of electronic products. In the field of analog IC design can be divided into several parts: A / D, D / A ,voltage source, current source, amplifier, and a voltage source which is the very important, because a stable voltage or current source is the basis of analog circuits. Electronic components diodes, resistors, capacitors and transistors, etc. are affected by changes of temperature. Analog design for only a few degrees Celsius temperature difference can cause a tremendous impact. In this paper, the research focus on the design of a low-dropout linear regulator with a stable voltage, the former includes voltage reference generator, error amplifier, feedback network, and Power MOS and is implemented with TSMC 65nm process, operating voltage at 2.5 volt. Due to the linear regulator circuit having a simple structure, low output ripple, less external components, low power consumption and other characteristics. So it is suitable for using in portable electronic products.
27
Wu, Po Chun, et 吳伯濬. « Time-interleaved Successive-Approximation Analog-to-Digital Converter with Redundancy ». Thesis, 2016. http://ndltd.ncl.edu.tw/handle/93721176098078768105.
Texte intégralRésumé :
碩士國立清華大學
電機工程學系
104
In recent years, the portable electronic device industry has been highly prosperous. The advance in wireless communication technology has dramatically improved people's lives. As the technologies progress constantly, analog-to-digital converter starts to play an important role in the era of digital. Analog-to-digital converter can convert nature signals into digital signals, then send the digital data to post-stage circuit. Thanks to the invention of the converts, technologies progress rapidly in these years. With the increase of the amount of data transmission and the growing demand of high-speed transmission, how to achieve high resolution and high sample rate analog-to-digital converter becomes one of the main issues. This thesis introduces algorithms with Redundancy, multi-channel time-interleaved and successive-approximation analog-to-digital converter. Eventually, we have completed a multi-channel time-interleaved successive-approximation analog-to-digital converter with redundancy. Its specifications is 10bits and sampling rate is 400MS/s. We used TSMC 65 nm CMOS process to do the simulation design. This design achieves signal to noise and distortion ratio of 62.46dB, equivalent to the effective number of bits 10.08. The average power consumption is 9.38mW.
28
Zeng, Jyun-Syuan, et 曾焌鉉. « A Successive-Approximation Analog-to-Digital Converter with half capacitance ». Thesis, 2013. http://ndltd.ncl.edu.tw/handle/18923140951377702775.
Texte intégralRésumé :
碩士國立清華大學
電機工程學系
101
Analog to digital converter are the essential bridge between nature world and digital world, and this thesis introduces a successive approximation analog to digital converter mainly used in the radar receiver, where the received RF signals are frequency-reduced after high-speed sampling, and then amplified by the baseband amplifier. The signals are then processed by the analog to digital converter and finally the converted digital signal to the computer for data analysis. In the thesis, we have proposed a successive approximation analog to digital converter, which has been greatly improved the capacitance matrix, making the size 50% less than traditional ones. The ADCs with monotonic structure capacitance matrix of different places are able to maintain the common-mode voltage, which is a huge benefit to avoid comparator from generating random offset voltages. The 10 bits in 20 million samples per second successive approximation analog to digital converter is implemented in a TSMC 65 nm CMOS process. The design is operated in 1V with ENOB 9.97 and perfect DNL, INL. The average power consumption is 620μW, and the average energy consumption is 30fJ each conversion.
29
Lin, Wei-Ting, et 林葦婷. « A Full Range Digital Calibration in 12-bit Successive Approximation Register Analog-to-Digital Converter ». Thesis, 2013. http://ndltd.ncl.edu.tw/handle/14040227441703086392.
Texte intégralRésumé :
碩士國立清華大學
電機工程學系
101
This thesis presents a 12-bit 100KS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. The A/D converter is designed in TSMC 0.18um CMOS process and operates at a supply voltage of 1.8V. The SAR A/D converter includes track-and-hold (T/H) stage, comparator, digital-to-analog converter and SAR control logic. Bootstrapped switch is used in S/H for improving circuit linearity and reducing the signal distortion. The comparator is composed of a dynamic latched regenerative circuit which gives comparator output better accuracy and higher speed because of positive feedback. Split capacitor array is used in D/A converter to decrease the total capacitance and save average power. Finally, the SAR control logic circuit uses a form of shift-registers-control conversion process and a row of D flip-flops for controlling the spilt capacitor array. The performance of the converter would be degraded due to the process variation and device mismatches. This thesis proposes self-correction circuits for comparator and D/A separately capacitor array calibration, larger LSB is chosen as a new reference unit capacitor, and produce a new binary-weighted capacitor array by charge redistribution. After D/A calibration, comparator input offset voltage needs to be calibrated and canceled. Because this offset is not linear, a new calibration method is proposed that divides input voltage into multiple windows and use piecewise linear approximation to predict and reduce input offset. Before normal operation, calibration mode is created to do DAC and comparator calibrations. Digital calibration codes are saved in latches, and these digital codes can be used in normal operation mode without wasting other clock cycles. After digital calibration, when sampling rate is 100KS/s, the SNDR is found to be 66.78dB, and ENOB is 10.8 bits. DNL and INL are found to be 0.69 and 0.86 LSB, respectively. Comparing to other calibration methods, the proposed calibration can predict and reduce offset for full range input voltages, thus has higher accuracy than other digital calibration methods. Since the digital calibration is used, calibration results are saved in flipflops and can be reused repeatedly. Smaller chip and shorter normal mode operation can be achieved. In addition, digital circuit is easier to scale and thus needs smaller area for advanced technologies.
30
Lin, Ding-Kuo, et 林鼎國. « Power-Efficient and High-Resolution Successive-approximation Register Analog-to-Digital Converter with Digital Calibration ». Thesis, 2018. http://ndltd.ncl.edu.tw/handle/332j2n.
Texte intégralRésumé :
碩士國立臺灣大學
電子工程學研究所
106
An analog-to-digital converter (ADC) transforming natural signals to digital form can be used for many digital signal processor (DSP) applications such as smartphone and computer. A 0.7V 12-bit 1MS/s ADC fabricated in 40nm CMOS is proposed in the thesis. The subranging architecture is used for improvement of speed and power. The detect-and-skip (DAS) algorithm and aligned switching method are adopted to reduce the switching energy of the DAC. To relax the noise design of comparator, tracking average is applied. With proposed capacitor calibration, we can use 0.5fF unit capacitor without affecting the performance of the ADC. The subranging SAR ADC achieves an ENOB of 10.75 at 1MS/s sampling rate with Nyquist input frequency. The active area is only 0.0198 mm2. It consumes 2.47uW and FoMw of 1.43fJ/conversion-step. It is suitable for portable, wearable and biomedical devices with low power consumption.
31
Yi-HsiangJuan et 阮翌翔. « A Digital Calibration Technique with Recursive Discrete Fourier Transform for Successive-Approximation Analog-to-Digital Converters ». Thesis, 2016. http://ndltd.ncl.edu.tw/handle/8y4aze.
Texte intégralRésumé :
博士國立成功大學
電機工程學系
105
Analog-to-digital converters (ADCs) are required for interfacing analog signals to digital signals in many applications, such as in biomedical acquisition systems, communication systems, or image processing systems. Among the existing ADC architectures, successive approximation (SAR) ADCs are popoular for their excellent energy efficiency and medium speed conversion, which makes them appropriate for use in biomedical signal acquisition. However, the high-performance limiataions that occur with SAR ADCs are mainly due to capacitor mismatch and DC offset, because of the problem of process variation. The capacitor mismatch and DC offset error in the characteristic function tends to immediately causes harmonic distortion, and these errors will then deteriorate the performance of the ADC. Calibration is thus essential to ensure system quality and enhance the performance of the ADC. The foreground digital calibration method proposed in this work is based on the recursive discrete Fourier transform (RDFT), recursive discrete cosine transform (RDCT) and matrix-form analysis (MFA), and is used to compensate for the capacitor mismatch error for the SAR ADC. The RDFT, RDCT and MFA calibration method, can be applied to evaluate the real radix of a DAC capacitor array with a new digital output to compensate for the errors caused by capacitor mismatch. In addition, the RDFT and RDCT calibration techniques can also eliminate the DC offset of a comparator circuit. In this proposed method, the RDFT and RDCT calibration method only needs to calculate the main and third harmonic tones, so the computational complexity of the RDFT/RDCT algorithm requires a total of (2N+2)/2N multiplications and (4N+2) additions. In addition, the transform length is selected to 4,096 and the world length of coefficient is set to 24 bits. For the ADC testing application, a self-testing platform with a foreground calibration technique for SAR ADC is presented. In this work, a high-accuracy DAC with digital control is used to generate the sinusoidal test signal. This signal is then implemented using an Arduino, and the clock signal is generated to test the ADCs. In addition, a fast Fourier transform (FFT) and RDFT processor is adopted to measure the dynamic performance and carry out the calibration, respectively. Therefore, this platform can help the designer to measure the dynamic performance of the ADC, and can also improve the performance of the ADC by using the proposed calibration technique. According to the simulation and measurement results, the proposed calibration method can reduce the harmonic distortion and improve the performance of the ADC. Here, the proposed calibration method has the advantage that it does not require extra analog circuit or complex digital circuits. Therefore, the proposed calibration method that utilizes the RDFT and RDCT processor instead of the FFT processor has the advantage of variable transform length, lower complexity, faster computation and less hardware cost. Comparing the computational complexity of the MFA technique with other state-of-the-art approaches, the proposed MFA algorithm dramatically reduces the multiplication by 99% and addition by 99%. As aresult, the proposed method can help designers to compensate for errors and enhance the performance of the ADC.
32
Chen, Hsin-cheng, et 陳信成. « Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter ». Thesis, 2015. http://ndltd.ncl.edu.tw/handle/xar24k.
Texte intégralRésumé :
碩士國立中山大學
資訊工程學系研究所
103
A high speed and low power Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter is proposed in this thesis. Using only two stage in the proposed ADC architecture, and reduce the requirement of power hungry operation amplifier. The pipelined stage replace the Flash ADC by SAR ADC. Removing the front-end sample-and-hold circuit by capacitor array in the SAR ADCs and sample switch. Hence, the whole circuit only requires one operation amplifier. Using dynamic comparators which consume no static power consumption. Capacitor arrays used in the SAR ADC adopt the monotonic switching procedure to achieve energy efficient and high speed applications. An additional comparator for MSB is designed for the ADC using in sample phase. The error correction Logic is employed for higher resolution.
33
Lee, Mao-Cheng, et 李茂誠. « Design of Low Power Successive Approximation Register Analog-to-Digital Converter ». Thesis, 2013. http://ndltd.ncl.edu.tw/handle/91556839843235408859.
Texte intégralRésumé :
碩士國立交通大學
電子工程學系 電子研究所
102
To date ADCs play essential roles in the communication fields and in the bio-sensor applications. High-speed and low-power Analog-to-Digital converters (ADCs) are required in these applications. However, with the development of the CMOS technology, the design of high quality analog circuits becomes a challenge. The Successive approximation Register (SAR) architectures primarily consist of digital circuits. With this property, the SAR ADCs are more suitable fabricated in advanced CMOS technology than other structures. In this thesis, we present two SAR ADC architectures: a R-2R ladder DAC and a binary capacitive DAC. For the high speed applications, we chose a R-2R resistive DAC in our first work. We design a 10-bit R-2R ladder SAR ADC in TSMC 65nm CMOS technology. In addition, for the high resolution applications, we design a 12-bit capacitive SAR ADC in TSMC 65nm CMOS technology and we introduce two digital calibration technologies in this work.
34
Lin, Jing Heng, et 林敬恆. « A 100MS/s Successive-Approximation Analog-to-Digital Converter with Redundancy ». Thesis, 2015. http://ndltd.ncl.edu.tw/handle/29066498543349448830.
Texte intégralRésumé :
碩士國立清華大學
電機工程學系
103
The development of Wireless communication technology has greatly improved our lives. 4G communication systems provide high data transmission speeds. It allows people to communicate with high-quality voice or even video calls. Behind the amazing applications, the high speed ADC is an essential block in the system. It’s the only block that can convert the nature signal to digital signal. There many types of ADC keep improving their ability. But the SAR ADC is more popular in recent years, because it takes a lot of advantage of technology scales. In the thesis, we have proposed a high speed SAR ADC with redundancy algorithm. The algorithm combines the criterion of capacitor mismatch and DAC settling time. The radix of each stage can be calculated precisely under 100 million samples per second. The 10 bits SAR ADC is implemented in a TSMC 65 nm CMOS process with 1V supply voltage. The full rail-to-rail input swing is 1.9V peak to peak. This design achieve signal to noise and distortion ratio of 62.09dB, equivalent to the effective number of bits 10.02.The peak DNL values are -0.4 to +0.6 LSB and the peak INL values are -0.4 to +0.63 LSB. The average power consumption is 2.02mW.
35
Wang, Hongtao. « A Column-Parallel Two-Step Successive Approximation Analog-To-Digital Converter ». 2013. https://scholarworks.umass.edu/theses/1091.
Texte intégralRésumé :
The ever-increasing resolution of CMOS imagers has steadily driven the requirements of readout circuitry. As the number of sensors on a chip increases, the bandwidth of the readout circuit must be increased correspondingly to maintain a constant frame rate. Column parallel A/D converters are commonly used to divide the conversions among many converters. However, implementing high-speed, high-resolution A/D converters at the column level is challenging because the entire circuit needs to be as narrow as the sensor.
This thesis presents the design of a 10-bit, one million conversions per second column-parallel A/D converter. A factor of four increase in speed over conventional converters was achieved by combining techniques of successive approximation and two-step subranging in a distributed column-parallel architecture. The speed of the converter makes it suitable to be integrated with a 1-megapixel sensor array providing a frame rate at 1000fps with 11µm pixels in a 0.35µm CMOS technology.
36
Ming-LunFan et 范銘倫. « Successive-Approximation Analog-to-Digital Converter for Low-Power System Applications ». Thesis, 2012. http://ndltd.ncl.edu.tw/handle/24078815364182330693.
Texte intégralRésumé :
碩士國立成功大學
電機工程學系碩博士班
100
This thesis presents the two analog-to-digital converters for low-power system applications, and the circuit design is realized by using TSMC 0.18μm 1P6M process. The first architecture is a single-ended SAR-ADC, the PMOS and NMOS are adopted in the input differential stage of comparator to ensure the input signal range would be equal to the value of supply voltage. Besides, the realization of digital-to-analog converter is using switch-capacitor technique, which could reduce the static power dissipation. The result of 1.8V 1MS/s 8-bit SAR-ADC, shows the SNDR is 46.219 dB with 499.023 kHz input signal, INL and DNL is -0.37 ~ 0.31 LSB and -0.37 ~0.51 LSB, total power consumption is 273 μW, and the area of layout (including PAD) is 780 μm × 780 μm. The second architecture is a fully-differential SAR-ADC. The modified two-stage comparator design except the bias circuit could reach the zero static power dissipation. Owing to the characteristic of differential circuit, it could reduce the noise effect to improve the SNR of circuits. The result of 1V 1MS/s 10-bit SAR-ADC, shows the SNDR is 57.02 dB by using the 149.4 kHz input signal, INL and DNL is -2.1 ~ 2.1 LSB and -1 ~2.2 LSB, total power consumption is 22 μW, and energy efficient is 38fJ/conversion-step.
37
Lin, Pin-Hong, et 林品宏. « A 160MS/s 10-bit Successive-Approximation Analog-to-Digital Converter ». Thesis, 2018. http://ndltd.ncl.edu.tw/handle/ng3ba5.
Texte intégralRésumé :
碩士國立清華大學
電機工程學系所
106
The development of Wireless communication technology has greatly improved our lives. 4G communication systems provide high data transmission speeds. It allows people to communicate with high-quality voice or even video calls. Behind the amazing applications, the high speed ADC is an essential block in the system. It’s the only block that can convert the nature signal to digital signal. There many types of ADC keep improving their ability. But the SAR ADC is more popular in recent years, because it takes a lot of advantage of technology scales. In the thesis, we have proposed a high speed SAR ADC. It combined the redundancy algorithm and the optimization of digital circuit to speed up the conversion. Metal-finger capacitors has smaller capacitance. Then, the area of DAC array can be scaled down and the power consumption can be improved. Application of dynamic logic make ADC become faster. It also make the area smaller then static logic because of less transistors. This ADC has high speed performance and low area cost. It can be applied to Time-interleaved ADC. The operation speed will be enhance by channel shunting. The 10 bits SAR ADC is implemented in a TSMC 65 nm CMOS process with 1.2V supply voltage. The full rail-to-rail input swing is 1.8V peak to peak. This design achieve signal to noise and distortion ratio of 62.15dB, equivalent to the effective number of bits 10.029.The peak DNL values are -0.01 to +0.01 LSB and the peak INL values are -0.04to +0.04 LSB. The average power consumption is 3.28mW. The area is 90μm×189μm = 0.01701mm2. After digital circuit simplification, the average power consumption becomes 1.851mW and the area becomes 74μm×178μm = 0.01317mm2.
38
LIN, YOU-REN, et 林祐任. « A 12bit Successive Approximation Analog-to-Digital Converter for Electrochemical Analysis ». Thesis, 2019. http://ndltd.ncl.edu.tw/handle/p8x27j.
Texte intégralRésumé :
碩士南臺科技大學
電子工程系
107
As the era progresses towards a smart life, many products are also advancing to include more science and technology, such as in daily necessities, wearable devices, medical supplies and others. However, most of these products require an analog-to-digital converter to change discrete signals into digital forms for analysis. An electrochemical measuring device is an important bridge of data transmission; thus, it is possible to reduce the device into smaller and portable form, while the medium used in contact should be more affordable, as well as disposable. Cyclic voltammetry of electrochemistry in this study was one of the most commonly used methods. Primarily, a potential function was first applied to generate a current for analysis. The potential scan would start with a positive potential or potential and returned in a cycle after reaching the terminal potential, in which such cycle could allow the plotting of CV for the oxidation reaction. A tri-electrode system was used, where screen printing used three electrodes, which were respectively the working electrode, the reference electrode and the auxiliary electrode. The 12-bit successive-approximation analog-to-digital converter was used in this study, with the algorithm based on binary search, where the intermediate value was used for comparison and the comparative result was temporarily registered each time, until successively approximated to the exact value of the input voltage drop. The architecture of the analog-to-digital converter included a sample-and-hold circuit, a comparator circuit and a successive-approximation logic control circuit, a control switch circuit and a capacitor array circuit. By double-ended differential input, the system could be effectively shielded from noises and it would be quite helpful for signal accuracy. The capacitor array was consisted of MOM capacitors (Metal-oxide-metal) and used five layers of metal in form of Pillar structure, in order to constitute a small unit capacitance value. When the sampling frequency is 8.928571429 MHz and clock of 125MHz. The signal-to-noise ratio during pre-simulation was 72.704 dB and the effective bit was 12.3694 bits. SNDR of post-simulation was 47.2578 dB and the effective bit was 8.1425 bits. The circuit layout used a TSMC 0.18μm CMOS process, with a size of 1.2mm x 1.2mm.
39
Chun-ChengLiu et 劉純成. « Design of High-Speed Energy-Efficient Successive-Approximation Analog-to-Digital Converters ». Thesis, 2010. http://ndltd.ncl.edu.tw/handle/05987973186744581135.
Texte intégralRésumé :
博士國立成功大學
電機工程學系碩博士班
98
This dissertation proposes three circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-of-concept prototypes, the proposed techniques are able to improve the operating speed and achieve excellent energy efficiency. The proposed techniques and chip measurement results are sketched as follows: The first technique is a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total sampling capacitance are reduced by about 81.3% and 50%, respectively. A 10-bit, 50-MS/s SAR ADC with the proposed monotonic capacitor switching procedure is implemented in a 0.13-?m 1P8M CMOS technology. The prototype ADC consumes 0.92 mW from a 1.2-V supply, and the effective number of bit (ENOB) is 8.48 bits. The resulting figure of merit (FOM) is 52 fJ/conversion-step. However, the signal-dependent offset caused by the variation of the input common-mode voltage degrades the linearity of ADC. We proposed an improved comparator design to avoid the linearity degradation. Besides, to avoid a clock signal with frequency higher than sampling rate, we used an asynchronous control circuit to internally generate the necessary control signals. The revised prototype is also implemented in a 0.13-?m 1P8M CMOS technology. It consumes 0.826 mW from a 1.2-V supply and achieves an ENOB of 9.18 bits. The resultant FOM is 29 fJ/conversion-step. The second technique is a binary-scaled error compensation method. In a medium-to-high resolution case, the DAC settling issue limits the operating speed of a SAR ADC, because it is not easy for the capacitive DAC to stabilize in a short time interval. We insert extra binary-scaled compensation bits to compensate for the DAC settling error. Accordingly, the comparator can perform comparison before the DAC is completely settled, resulting in improved operating speed. A 10-bit, 100-MS/s SAR ADC using the binary-scaled error compensation method is implemented in a 65-nm 1P6M CMOS technology. The prototype consumes 1.13 mW from a 1.2-V supply and achieves an ENOB of 9.51 bits. The resultant FOM is 15.5 fJ/conversion-step. The third technique is a predictive capacitor switching method that uses a predictive circuit to avoid unnecessary switching in a DAC network. This method saves 40~45% switching energy. Combined with the first technique, the average switching energy is reduced by about 90% than the conventional one. In addition, this technique improves static and dynamic performance of a SAR ADC. A 10-bit, 10-MS/s SAR ADC using this method is implemented in a 0.18-?m 1P6M CMOS technology. The prototype consumes 98 ?W from a 1-V supply and achieves an excellent ENOB of 9.83 bits. The resultant FOM is only 11 fJ/conversion-step.
40
Huang, Yi-ting, et 黃意婷. « A 6-bit 220-MS/s Successive-Approximation Analog-to-Digital Converter ». Thesis, 2008. http://ndltd.ncl.edu.tw/handle/87422351608283333666.
Texte intégralRésumé :
碩士國立成功大學
電機工程學系碩博士班
97
This thesis reports the implementation of a 6-bit 220-MS/s low-power high-speed successive-approximation (SAR) analog-to-digital converter (ADC). A set-and-down switching sequence technique is proposed to reduce the power consumption of the ADC. Compared to the conventional switching method, the average switching energy is reduced by 81%. This proposed ADC is fabricated in TSMC 0.18-�慆 1P5M digital CMOS process, and only occupies 0.24 mm �e 0.13 mm active area. Measurement results show that the maximum effective number of bits (ENOB) is 5.13 bits and the power consumption is 6.8 mW at the sampling frequency of 220 MHz. Also, the effective resolution bandwidth (ERBW) is 200 MHz. Accordingly, the figure-of-merit (FOM) is only 0.88 pJ/conversion-step.
41
Lin, Han-Chiang, et 林翰江. « Design and Implementation of Energy Efficient Successive-Approximation Analog-to-Digital Converters ». Thesis, 2013. http://ndltd.ncl.edu.tw/handle/40290650543742542238.
Texte intégralRésumé :
碩士國立臺灣師範大學
應用電子科技學系
101
With the development of modern CMOS fabrication, the advancement of fabrication processing is capable of reducing the area of integrated circuit layout and lowering the voltage during circuit operation, producing a constant stream of low-power and high-performance circuits. With the raising number of portable electronic devices, portability as well as battery endurance have become the mainstream of chips performance. Especially in the application of human or biological implantation, the importance of low-power circuit design become much greater. Among different type of analog-to-digital converters (ADC), successive approximation register (SAR) is the most appropriate for low-power designs. Becouse it only takes one comparator to complete the whole sampling data during each conversion phase, which significantly reduces the power dissipation. In this thesis, there are two schemes：(1) double partial FCS scheme based single-ended SAR ADC, (2) the partial FCS scheme based differential SAR ADC .Applying double partial FCS scheme based single-ended SAR ADC can efficiently reduce 97.57% of average switching energy compared to the conventional DAC approach. Constructed by TSMC 0.18-μm 1P6M process technology, the presented SAR ADC can achieve 105.86-fJ/conversion-step figure of merit (FOM) in the Nyquist bandwidth. In addition, applying the partial FCS scheme based differential SAR ADC can efficiently reduce 96.875% of Capacitor layout area compared to the conventional DAC approach. Constructed by TSMC 0.18-μm 1P6M process technology, the presented SAR ADC can achieve 29.47-fJ/conversion-step figure of merit (FOM).
42
Chuang, Siou-Ming, et 莊修銘. « Low Power Successive Approximation Analog-to-Digital Converter for Biomedical Signal Recording ». Thesis, 2011. http://ndltd.ncl.edu.tw/handle/06181142325661659785.
Texte intégralRésumé :
碩士國立交通大學
電控工程研究所
99
A low power Successive Approximation Analog-to-Digital Converter (SAR ADC) is presented. This thesis presents a new switching procedure which with low switching energy. The design is a 100KS/s、12 bit resolution and 10KS/s、8bit resolution analog-to-digital converter, using UMC 90nm CMOS Logic & Mixed-Mode 1P9M Low K Process. The simulation results show that the ADC, under 100KS/s and 12-bit mode, achieves an SNDR of 69.7dB,and the resultant ENOB is 11.28bits. Under 10KS/s and 8-bit mode, it achieves an SNDR of 48.4dB, and the resultant ENOB is 7.75 bits. The power consumption of the ADC converter in 12-bit and 8-bit mode is 5.42uW and 3.12uW, respectively. Finally, the chip area is 1145um*951um.
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Wu, I.-Ying, et 吳宜穎. « An Improved Successive-Approximation Analog-to-Digital Converter with Offset Calibration Technique ». Thesis, 2016. http://ndltd.ncl.edu.tw/handle/2vnafm.
Texte intégralRésumé :
碩士國立高雄應用科技大學
電子工程系碩士班
104
The thesis proposes the design of a 6-bit 100-MS/s improved successive-approximation analog-to-digital converter (ISA-ADC). In this thesis, the improved successive-approximation analog-to-digital converter uses R-2R ladder architecture and includes offset calibration technique that can reduce the offset voltage to improve circuit effectiveness in comparator.
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Chen, Chun-Fu, et 陳俊甫. « 1.2V 10-bits Low Power Successive Approximation Register Analog-to-Digital Converter ». Thesis, 2011. http://ndltd.ncl.edu.tw/handle/494753.
Texte intégralRésumé :
碩士國立虎尾科技大學
電機工程研究所
99
Recently, low power ADC has been developed for many energy-constrained applications, such as wireless sensor networks and bio-medical applications. Among many types of ADC, slope ADC, sigma-delta ADC, and successive approximation register ADC (SAR ADC) are good candidates for low power applications. SAR ADC has recently become very attractive due to their minimal active analog circuit requirements. SAR ADC consists of dual sampling capacitor, sample-and-hold circuit (S/H), digital-to-analog converter (DAC), comparator, and successive approximation register. Bootstrapped switch is applied to sample-and-hold circuit to achieve rail-to-rail signal swing at low-voltage power supply. DAC structure is based on binary-weighted capacitor array for MSB part and C-2C capacitor array for LSB part. Furthermore, dual sampling technique is also applied to DAC structure. This scheme provides low power consumption for the proposed SAR ADC. In this research, 10-bits 727kS/s SAR ADC under a single 1.2V power supply has been designed and simulated in TSMC 0.18μm CMOS 1P6M process. Simulation results show that SAR ADC can operate at an input frequency of 13.5kHz with SFDR of 57.5dB and SNDR of 56.3dB. The peak DNL is -0.7LSB ~ 0.95 LSB, the peak INL is -1.22LSB ~ 1.48LSB, and the power dissipation is about 21.9μW. Simulations have been performed to demonstrate the feasibility of this new technique.
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Gan, Jianhua Abraham Jacob A. Yan Shouli. « Non-binary capacitor array calibration for a high performance successive approximation analog-to-digital converter ». 2003. http://wwwlib.umi.com/cr/utexas/fullcit?p3119619.
Texte intégral
46
Gan, Jianhua. « Non-binary capacitor array calibration for a high performance successive approximation analog-to-digital converter ». Thesis, 2003. http://hdl.handle.net/2152/591.
Texte intégral
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Lin, Jing-Mao, et 林經貿. « Design of a 1-V 10-Bit Successive Approximation Analog-to-Digital Converter ». Thesis, 2007. http://ndltd.ncl.edu.tw/handle/14200763484023935656.
Texte intégralRésumé :
碩士國立中正大學
電機工程所
96
Following the process evolution, the technologies go into deep sub-micron eras. The supply voltage has to be scaled down and the demand for circuits under battery operated is increased, such as portable equipments, sensor devices, bio-medical applications. This thesis presented a 1v, 10bit successive approximation ADC(SA-ADC). In order to increase the resolution of the SA-ADC, the bootstrap technique is used on the sample and hold circuit. A pre-amplifier is used in the comparator circuit. The chip is implemented in TSMC 0.18μm 1P6M CMOS technology. Measurement results show that the SNDR and ENOB of the SA-ADC with an input frequency of 501kHz under sampling frequency of 1.04MHz are 47.29dB and 7.56bit, respectively. The DNL is about +1.22/-1.0 LSB, and INL is about +2.66/-2.44 LSB. The total power consumption is 86μW.
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Chang, Ting-Kai, et 張廷愷. « Design of High-Speed Energy-Efficient Successive-Approximation Register Analog-to-Digital Converters ». Thesis, 2014. http://ndltd.ncl.edu.tw/handle/39481166797197627137.
Texte intégralRésumé :
碩士國立臺灣大學
電子工程學研究所
102
This dissertation proposes two circuit design techniques for high-speed energy-efficient successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-and-concept prototypes, the proposed techniques are able ti improve the operating speed and decrease total circuit power consumption. The proposed techniques and chip measurement results are sketched as follows: The first technique is using charge-sharing method to achieve a Pipelined SAR ADC, this architecture using passive components capacitors for second stage sampling without using OP amplifiers, so the power consumption can be decreased greatly. A 9-bit 100MS/s SAR ADC with proposed method is implemented in TSMC 90nm 1P9M CMOS technology. As for measurement results, 1MHz input sinusoidal signal is fed into the ADC, when the operating frequency at 10MS/s, 20MS/s, 50MS/s and 100MS/s, the ENOB of ADC are 7.33 bits, 7.27 bits, 6.92 bits and 6.57 bits. The ADC consumes 2.2mW from a 1-V supply when the operating frequency at 100MS/s, the resulting figure of merit (FOM) is 231fJ/conversion-step. The second technique is adding a for reference to decrease the area of capacitor array, also we using the nature of capacitor that current will lagging the voltage, we make some change at switching, so we can achieve the target voltage without charge redistribution, we call this method “voltage-jumping” method. By using this method, we can not only decrease the capacitor array area by 50%, but also reduce the settling time of second bit. A 10-bit 100MS/s SAR ADC with proposed method is implemented in TSMC 90nm 1P9M CMOS technology. As for measurement results, 1MHz input sinusoidal signal is fed into the ADC, when the operating frequency at 10MS/s, 50MS/s and 100MS/s, the ENOB of ADC are 7.42 bits, 7.57 bits and 7.32 bits. The ADC consumes 1.6mW from a 1-V supply when the operating frequency at 100MS/s, the resulting figure of merit (FOM) is 100fJ/conversion-step.
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Wang, Wei-Sheng, et 王韋盛. « A 1.6μW Successive Approximation analog-to-digital Converter for Bio-medical Signal Application ». Thesis, 2012. http://ndltd.ncl.edu.tw/handle/52285246553940087883.
Texte intégralRésumé :
碩士國立清華大學
電機工程學系
100
This thesis proposes a novel 0.9V 10-bit Successive Approximation (SAR) analog-to-digital converter (ADC) based on half junction splitting (J.S.) and half binary weighted capacitor digital-to-analog converter (DAC) architecture. The kick-back noise of this structure due to comparator is larger than other DAC structures, thus a modified rail-to-rail comparator is used to reduce kick-back noise. This ADC is implemented in sub-threshold to reduce power consumption. In addition, dummy comparators are used in different sections of DAC to reduce the offset voltage caused by different gain errors of different DAC sections. The pre-simulation shows that the power dissipation is 1.27μW, SNDR is 61.7dB, ENOB is 9.96-bit, and figure-of-merit (FOM) is 12.8 fJ/conversion step. The chip has been fabricated with TMSC 0.18μm 1P6M CMOS process. The chip area is 893�e893μm2 with pads, and the core area is 440�e430μm2. The post-layout simulation shows that the power consumption is 1.72μW, the SNDR is 59.1dB, ENOB is 9.53-bit, and FOM is 23.2 fJ/conversion step. Under 0.9V supply voltage and 100KS/s sampling rate, the measurement result shows that the power dissipation was 1.59μW, SNDR was 46.47dB, ENOB was 7.43-bit, and FOM was 92.2 fJ/conversion step. This chip worked under 0.6 V supply voltage and consumed only 0.783μW. This low-power ADC is suitable for bio-medical signal acquisition. This low-power ADC is suitable for bio-medical signal acquisition.
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Huang, Hsin, et 黃昕. « Low-Power DAC and Successive Approximation Analog to Digital Converter for Biomedical Application ». Thesis, 2008. http://ndltd.ncl.edu.tw/handle/81107529896968436330.
Texte intégralRésumé :
碩士長庚大學
電子工程學研究所
96
In this thesis we discuss the design of the analog to digital converter (ADC) for biomedical signal applications. ADC servers as an important role to translate biomedical signals from analog to digital for back-end microprocessor to analyze and process. The required ADC suitable for this purpose must have low power and high resolution , which has a good tradeoff between power,area and speed. Analog circuits are the key point of the ADC design. Among them, DAC is of much importance . In this thesis we use both fixed reference voltage, and Complementary Signal Generator (CSG) for the design of the mixed charge serial DAC. It is effective to improve the DAC characteristic. The obtained DNL is +0.08 ~ -0.08LSB and INL0.043~ -0.065LSB,respectively .Besides, an offset cancellation and sleep control are designed for the comparator circuit to reduce mismatch error and save power.