Littérature scientifique sur le sujet « SUBMICRON TECHNOLOGIES »
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Articles de revues sur le sujet "SUBMICRON TECHNOLOGIES"
Claeys, Cor, Jan Vanhellemont et Eddy Simoen. « Defect Engineering in Submicron CMOS Technologies ». Solid State Phenomena 19-20 (janvier 1991) : 95–108. http://dx.doi.org/10.4028/www.scientific.net/ssp.19-20.95.
Texte intégralGal, Laszlo, C. Prunty et R. Kumar. « Comparative study of submicron BiCMOS technologies ». Microelectronics Journal 23, no 1 (mars 1992) : 59–74. http://dx.doi.org/10.1016/0026-2692(92)90097-k.
Texte intégralZhu, Tao, Hai Rong Li, Yan Dong Wan, Sha Chen et Hai Bing Liu. « Recognizability and Controlling Technology of Submicron Particles ». Applied Mechanics and Materials 182-183 (juin 2012) : 369–73. http://dx.doi.org/10.4028/www.scientific.net/amm.182-183.369.
Texte intégralLiu, Xiaoxiao, Guangsheng Ma, Jingbo Shao, Zhi Yang et Guanjun Wang. « Interconnect crosstalk noise evaluation in deep-submicron technologies ». Microelectronics Reliability 49, no 2 (février 2009) : 170–77. http://dx.doi.org/10.1016/j.microrel.2008.11.013.
Texte intégralJarron, P., G. Anelli, T. Calin, J. Cosculluela, M. Campbell, M. Delmastro, F. Faccio et al. « Deep submicron CMOS technologies for the LHC experiments ». Nuclear Physics B - Proceedings Supplements 78, no 1-3 (août 1999) : 625–34. http://dx.doi.org/10.1016/s0920-5632(99)00615-5.
Texte intégralChong, Y. F., K. L. Pey, A. T. S. Wee, A. See, Z. X. Shen, C. H. Tung, R. Gopalakrishnan et Y. F. Lu. « Laser-induced titanium disilicide formation for submicron technologies ». Journal of Electronic Materials 30, no 12 (décembre 2001) : 1549–53. http://dx.doi.org/10.1007/s11664-001-0172-2.
Texte intégralAchkasov, A., Maksim Solodilov, Nikolay Litvinov, Pavel Chubunov, V. Zolnikov, Dmitriy Shehovcov et Oleg Bordyuzha. « Features of the design of microcircuits made using deep-submicron technologies ». Modeling of systems and processes 15, no 4 (13 décembre 2022) : 7–17. http://dx.doi.org/10.12737/2219-0767-2022-15-4-7-17.
Texte intégralSchwalke, U., M. Kerber, K. Koller et H. J. Jacobs. « EXTIGATE : The ultimate process architecture for submicron CMOS technologies ». IEEE Transactions on Electron Devices 44, no 11 (1997) : 2070–77. http://dx.doi.org/10.1109/16.641386.
Texte intégralNikolaidis, T., et C. Papadas. « ESD production for deep submicron triple well CMOS technologies ». Electronics Letters 35, no 23 (1999) : 2025. http://dx.doi.org/10.1049/el:19991393.
Texte intégralЧубур, K. Chubur, Яньков, A. Yankov, Зольников, Konstantin Zolnikov, Ачкасов et A. Achkasov. « ALGORITHMIC BASIS OF MODELING FAILURES IN DEEP-SUBMICRON TECHNOLOGIES ». Modeling of systems and processes 8, no 1 (2 juillet 2015) : 15–17. http://dx.doi.org/10.12737/12014.
Texte intégralThèses sur le sujet "SUBMICRON TECHNOLOGIES"
Muñoz, Gamarra Jose Luis. « NEMS/MEMS integration in submicron CMOS Technologies ». Doctoral thesis, Universitat Autònoma de Barcelona, 2014. http://hdl.handle.net/10803/285060.
Texte intégralThe reduction of MEMS devices dimensions to the nano scale (NEMS) has allowed them to access a host of new physics and promise to revolutionize sensing applications. However this miniaturization has been obtained at an expense of dedicated, difficult and non reproducible fabrication processes. This thesis deals with the miniaturization of MEMS structures following a CMOS-MEMS approach. In order to it a small pitch CMOS technology (ST 65nm) is studied in depth, NEMS structures are defined using its available layers (width= 60 nm, thickness= 100nm in polysilicon and width= 90nm, thickness= 180nm in metal 1 based on copper) and a post-CMOS releasing process is developed in order to release them. Successful integration of NEMS devices is demostrated with the added value of a robust, reproducible fabrication and an easy integration with additional circuitry. However this aggressive scaling has a main drawback, small output signals. As an alternative to capacitive read-out, the implementation of a resonant gate transduction, based on the idea of modulate the charge of a transistor by the movement of a mechanical structure, is studied and implemented. The frequency response of a polysilicon resonator implemented in AMS 0.35um CMOS technology (24 MHz) has been successfully characterized and its operation as a low voltage switch (2.25 V pull-in) is demonstrated. In addition, we propose the use of mechanical switches not only as memory or logic devices (due to its energy efficiency), but also as the building blocks of a ring oscillator configuration composed exclusively by mechanical switches. This new approach extends their use to other application as mass sensing but with the added value of a digital output signal. In order to implement this new configuration a model to simulate its behavior is developed and mechanical switches are built using different CMOS technologies, trying always to reduce their dimensions. Low operating voltages (5 V, MIM approach), abrupt response (4.3 mV/decade, ST Metal 1) and good ION/IOFF ratio (1.104, MIM approach) are obtained.
Manhas, Sanjeev Kumar. « Hot carrier degradation in deep submicron n-MOS technologies ». Thesis, De Montfort University, 2003. http://hdl.handle.net/2086/10787.
Texte intégralBazarjani, Seyfollah Carleton University Dissertation Engineering Electronics. « Mixed analog-digital design considerations in deep submicron CMOS technologies ». Ottawa, 1996.
Trouver le texte intégralSilvestri, Marco. « AGEING AND IONIZING RADIATION SYNERGETIC EFFECTS IN DEEP-SUBMICRON CMOS TECHNOLOGIES ». Doctoral thesis, Università degli studi di Padova, 2010. http://hdl.handle.net/11577/3422233.
Texte intégralI processi termonucleari che si verificano all’interno del sole danno origine a radiazioni ionizzanti, tempeste elettromagnetiche ed emissioni di masse di plasma coronarico ionizzato che possono raggiungere l’atmosfera terrestre. Inoltre gli effetti indotti dai raggi cosmici, la presenza delle fasce di Van Allen, nonché gli ambienti radioattivi artificiali costruiti dall’uomo, espongono i circuiti microelettronici a condizioni di funzionamento estremo nello spazio e sulla terra. Al giorno d’oggi molte attività umane si basano su satelliti geostazionari che devono rimanere funzionanti ed affidabili per lungo tempo: sistemi GPS, comunicazioni audio e video, sistemi di sorveglianza, satelliti meteorologici, applicazioni per la difesa, etc. Inoltre il traffico aereo civile ad alta quota, anch’esso esposto a radiazioni, è sempre in maggiore espansione e naturalmente ogni passeggero si augura di atterrare sano e salvo ogni volta che necessiti di volare. Non da meno le centrali nucleari che forniscono il fabbisogno energetico alle nazioni più avanzate devono assolutamente operare in sicurezza evitando tremendi disastri naturali e sociali. Ognuna di queste applicazioni è tuttavia fortemente dipendente dall’elettronica che gestisce e controlla ogni attività in modo trasparente rispetto all’utente. La sfida principale per ingegneri e scienziati che lavorano in questo ambito, è quella di studiare e progettare microelettronica in grado di operare in ambienti ostili per lungo tempo e in modo affidabile. Il progresso tecnologico dei dispositivi CMOS verso dimensioni sub-micrometriche gioca un ruolo fondamentale in termini di affidabilità. Infatti, a prescindere dagli effetti delle radiazioni, la riduzione delle dimensioni dei dispositivi e l’implementazione di ossidi ultra sottili influiscono sull’affidabilità dei transistor MOS a causa dell’aumento intrinseco dei campi elettrici che accelerano i naturali processi di degradazione. Per esempio, l’iniezione di portatori caldi è una delle cause più importanti di degradazione in quanto l’energia che gli elettroni possono acquisire è correlata al campo elettrico accelerante. Questa tesi sviluppa questa problematica sia su transistor standard (Open Layout Transistor, OLT) che su transistor ad anello (Enclosed layout Transistor, ELT), questi ultimi progettati per essere immuni dagli effetti di dose totale (Total Ionizing Dose, TID). Sebbene i meccanismi e gli effetti legati ai portatori caldi siano ben documentati nella letteratura di settore, questa tesi è uno dei pochi lavori che si propone di investigare le sinergie con gli effetti indotti dai raggi X, introducendo nuovi e interessanti aspetti legati all’affidabilità. Inoltre la previsione del tempo di vita dell’ossido di gate è una delle informazioni più importanti da tenere in considerazione quando si intende pianificare una missione a lungo termine. Questa tesi dimostra che l’esposizione ai raggi X può alterare i successivi test di affidabilità a causa dell’interazione tra i difetti generati dalle radiazioni e dagli stress elettrici. Di conseguenza, un approccio nuovo va seguito quando si intende valutare l’adeguatezza dei dispositivi da implementare in applicazioni ove siano presenti radiazioni ionizzanti. Senza considerare questi aspetti le previsioni che emergono dai test sperimentali possono in alcuni casi fortunati essere conservative, in altri meno fortunati sottostimare i fenomeni portando a conclusioni fuorvianti e addirittura pericolose per il buon esito di una missione. Una nuova fonte di incertezza e di sinergia per le tecnologie CMOS avanzate esposte a raggi X riguarda il diverso assorbimento di dose totale indotto dalle interconnessioni metalliche. Infatti la necessità di integrazione sempre più spinta obbliga i progettisti ad incrementare il numero di strati di interconnessione nel back-end del dispositivo nonché la riduzione dello spessore dei dielettrici isolanti. Di conseguenza, a fronte di una esposizione ai raggi X, gli elettroni secondari generati dall’interazione con gli strati metallici possono raggiungere più facilmente l’area attiva del transistor degradandolo in modo non uniforme. In questa tesi questo effetto viene studiato grazie all’uso di strutture appositamente progettate, contribuendo cosi allo sviluppo di dispositivi il più possibile immuni da tale fenomeno. D’altro canto gli effetti indotti da particelle cariche (Single Event Effect, SEE) nelle moderne tecnologie stanno diventando la principale fonte di errore. L’elettronica implementata a bordo di navicelle spaziali, satelliti, aerei civili e militari, e perfino al livello del suolo terrestre è affetta da SEEs, a volte distruttivi, a volte no. In particolare questa tesi si focalizza sulla rottura istantanea e permanente dell’ossido di gate causata dal passaggio di uno ione pesante in presenza di alti campi elettrici (Single Event Gate Rupture, SEGR) che, a causa delle sue caratteristiche, lo pone tra gli eventi più rischiosi. In questa tesi vengono studiati diversi fattori: l’influenza del tipo di struttura di test, della polarizzazione mantenuta durante gli esperimenti e l’influenza dei raggi X. Anche in questo caso si dimostra l’esistenza di diverse forme di sinergia tra radiazioni e stress elettrico, fornendo indicazioni circa le metodologie di test e l’uso di strutture che possano fornire risultati realistici riguardo l’incidenza di questo fenomeno nei moderni transistor utilizzati per l’elettronica spaziale. In conclusione questa tesi vuole essere il primo forte contributo scientifico per lo studio degli effetti sinergici tra radiazione ionizzante e test di vita accelerati su dispositivi CMOS avanzati, da implementare in ambienti radioattivi quali lo spazio o gli esperimenti di fisica delle alte energie.
Finkelstein, Hod. « Shallow-trench-isolation bounded single-photon avalanche diodes in commercial deep submicron CMOS technologies ». Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2007. http://wwwlib.umi.com/cr/ucsd/fullcit?p3274523.
Texte intégralTitle from first page of PDF file (viewed October 3, 2007). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 256-271).
Havránek, Miroslav [Verfasser]. « Development of pixel front-end electronics using advanced deep submicron CMOS technologies / Miroslav Havránek ». Bonn : Universitäts- und Landesbibliothek Bonn, 2014. http://d-nb.info/1077288867/34.
Texte intégralKlein, Adam Sherman. « Design and Characterization of RFIC Voltage Controlled Oscillators in Silicon Germanium HBT and Submicron MOS Technologies ». Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/34435.
Texte intégralMaster of Science
Halek, Basel. « The analysis and optimisation of performance and reliability metrics of capacitive links in deep submicron semiconductor technologies ». Thesis, University of Newcastle Upon Tyne, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.514992.
Texte intégralBaptista, Acácio João Galhardo. « Novel techniques for the design and practical realization of switched-capacitor circuits in deep-submicron CMOS technologies ». Doctoral thesis, FCT - UNL, 2009. http://hdl.handle.net/10362/2619.
Texte intégralSwitches presenting high linearity are more and more required in switched-capacitor circuits,namely in 12 to 16 bits resolution analog-to-digital converters. The CMOS technology evolves continuously towards lower supply voltages and, simultaneously, new design techniques are necessary to fulfill the realization of switches exhibiting a high dynamic range and a distortion compatible with referred resolutions. Moreover, with the continuously downing of the sizes, the physic constraints of the technology must be considered to avoid the excessive stress of the devices when relatively high voltages are applied to the gates. New switch-linearization techniques, with high reliability, must be necessarily developed and demonstrated in CMOS integrated circuits. Also, the research of new structures of circuits with switched-capacitor is permanent. Simplified and efficient structures are mandatory, adequate to the new demands emerging from the proliferation of portable equipments, necessarily with low energy consumption while assuring high performance and multiple functions. The work reported in this Thesis comprises these two areas. The behavior of the switches under these new constraints is analyzed, being a new and original solution proposed, in order to maintain the performance. Also, proposals for the application of simpler clock and control schemes are presented, and for the use of open-loop structures and amplifiers with localfeedback. The results, obtained in laboratory or by simulation, assess the feasibility of the presented proposals.
ARUMUGAM, THIAGARAJAN. « A heuristic approach for Capacitive Crosstalk Avoidance during Post Global Routing Crosstalk Synthesis for Deep Submicron Technologies ». University of Cincinnati / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1204214738.
Texte intégralLivres sur le sujet "SUBMICRON TECHNOLOGIES"
Symposium N on Materials and Processes for Submicron Technologies (1998 Strasbourg, France). Materials and processes for submicron technologies : Proceedings of Symposium N on Materials and Processes for Submicron Technologies of the E-MRS Spring Conference, Strasbourg, France, 16-19 June 1998. Amsterdam : Elsevier, 1999.
Trouver le texte intégralLevy, R. A., J. M. Martinez-Duart et R. Madar. Materials and Processes for Submicron Technologies. Elsevier Science & Technology Books, 1999.
Trouver le texte intégralLeung, Wallace Woon-Fong. Nanofiber Filter Technologies for Filtration of Submicron Aerosols and Nanoaerosols. Elsevier, 2021.
Trouver le texte intégralNanofiber Filter Technologies for Filtration of Submicron Aerosols and Nanoaerosols. Elsevier, 2022. http://dx.doi.org/10.1016/c2020-0-01936-5.
Texte intégralLeung, Wallace Woon-Fong. Nanofiber Filter Technologies for Filtration of Submicron Aerosols and Nanoaerosols. Elsevier, 2021.
Trouver le texte intégralEl-Kareh, Badih. Silicon Devices and Process Integration : Deep Submicron and Nano-Scale Technologies. Springer, 2009.
Trouver le texte intégralEl-Kareh, Badih. Silicon Devices and Process Integration : Deep Submicron and Nano-Scale Technologies. Springer, 2010.
Trouver le texte intégralChapitres de livres sur le sujet "SUBMICRON TECHNOLOGIES"
Veendrick, H. J. M. « Special circuits, devices and technologies ». Dans Deep-Submicron CMOS ICs, 209–30. Boston, MA : Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4133-2_5.
Texte intégralSvensson, Christer. « Low Voltage Technologies ». Dans Low Power Design in Deep Submicron Electronics, 493–509. Boston, MA : Springer US, 1997. http://dx.doi.org/10.1007/978-1-4615-5685-5_17.
Texte intégralFredkin, Edward F., et Tommaso Toffoli. « Design Principles for Achieving High-Performance Submicron Digital Technologies ». Dans Collision-Based Computing, 27–46. London : Springer London, 2002. http://dx.doi.org/10.1007/978-1-4471-0129-1_2.
Texte intégralSchoenauer, Tim, Joerg Berthold et Christoph Heer. « Reduced Leverage of Dual Supply Voltages in Ultra Deep Submicron Technologies ». Dans Lecture Notes in Computer Science, 41–50. Berlin, Heidelberg : Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-39762-5_6.
Texte intégralJanssens, Johan, et Michiel Steyaert. « Design of Broadband Low-Noise Amplifiers in Deep-Submicron CMOS technologies ». Dans Analog Circuit Design, 317–35. Boston, MA : Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-2983-2_14.
Texte intégralSingh, Shivam, Prakash Kumar Ojha et Abhijit R. Asati. « Analysis of Logical Effort-Based Optimization in the Deep Submicron Technologies ». Dans Lecture Notes in Electrical Engineering, 23–37. Singapore : Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-6737-5_3.
Texte intégralCaputa, Peter, Henrik Fredriksson, Martin Hansson, Stefan Andersson, Atila Alvandpour et Christer Svensson. « An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies ». Dans Lecture Notes in Computer Science, 849–58. Berlin, Heidelberg : Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30205-6_87.
Texte intégralBaño Morales, Daysi, Nelly Rosas-Laverde et Cristian Santacruz. « Synthesis of Nanometric and Submicron Particles of Titanium Dioxide for the Formation of Nanostructured Films ». Dans Intelligent Technologies : Design and Applications for Society, 150–60. Cham : Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-24327-1_13.
Texte intégralKrivokapic, Z., et W. D. Heavlin. « Predicting Manufacturing Variabilities for Deep Submicron Technologies : Integration of Process, Device, and Statistical Simulations ». Dans Simulation of Semiconductor Devices and Processes, 229–32. Vienna : Springer Vienna, 1993. http://dx.doi.org/10.1007/978-3-7091-6657-4_56.
Texte intégral« Submicron Electronic Technologies ». Dans Multimedia Technology for Applications. IEEE, 2009. http://dx.doi.org/10.1109/9780470545348.part2.
Texte intégralActes de conférences sur le sujet "SUBMICRON TECHNOLOGIES"
Lowe, A. T. « Advances in submicron process technologies ». Dans AIP Conference Proceedings Volume 138. AIP, 1986. http://dx.doi.org/10.1063/1.35545.
Texte intégralDobre, Mihaela-Daniela, et Gheorghe Brezeanu. « PAD cells performances in submicron technologies ». Dans 2016 International Semiconductor Conference (CAS). IEEE, 2016. http://dx.doi.org/10.1109/smicnd.2016.7783087.
Texte intégralLong, J. « T1 Design of integrated RF front-ends in submicron and deep submicron CMOS technologies ». Dans 2007 7th International Conference on ASIC. IEEE, 2007. http://dx.doi.org/10.1109/icasic.2007.4415549.
Texte intégralDehaene, W., S. Cosemans, A. Vignon, F. Catthoor et P. Geens. « Embedded SRAM design in deep deep submicron technologies ». Dans ESSCIRC 2007. 33rd European Solid-State Circuits Conference. IEEE, 2007. http://dx.doi.org/10.1109/esscirc.2007.4430324.
Texte intégralSamy Hosny, M., et Yuejian Wu. « Low power clocking strategies in deep submicron technologies ». Dans Tutorial (ICICDT). IEEE, 2008. http://dx.doi.org/10.1109/icicdt.2008.4567265.
Texte intégralGupta, Shourya, Kirti Gupta et Neeta Pandey. « Performance evaluation of SRAM cells for deep submicron technologies ». Dans 2016 Second International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity (CIPECH). IEEE, 2016. http://dx.doi.org/10.1109/cipech.2016.7918785.
Texte intégralGarcia-Ortiz, A., L. Kabulepa, T. Murgan et M. Glesner. « Moment-based power estimation in very deep submicron technologies ». Dans ICCAD-2003. International Conference on Computer Aided Design. IEEE, 2003. http://dx.doi.org/10.1109/iccad.2003.159678.
Texte intégralAuer, S., J. Dietl, L. DoThanh, B. Ganter, K. H. Kusters, P. Kupper, L. Kusztelan, H. M. Muhlhoff, W. Muller et F. X. Stelz. « Limitations of Trench Cell Process Technologies for Submicron DRAMs ». Dans 1990 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1990. http://dx.doi.org/10.7567/ssdm.1990.c-9-6.
Texte intégralMavis, David G., Paul H. Eaton et M. D. Sibley. « SEE characterization and mitigation in ultra-deep submicron technologies ». Dans 2009 IEEE International Conference on IC Design and Technology (ICICDT). IEEE, 2009. http://dx.doi.org/10.1109/icicdt.2009.5166276.
Texte intégralPileggi, Lawrence. « Timing metrics for physical design of deep submicron technologies ». Dans the 1998 international symposium. New York, New York, USA : ACM Press, 1998. http://dx.doi.org/10.1145/274535.274539.
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