Littérature scientifique sur le sujet « RTL-to-TLM abstraction »

Simulating systems on a chip (SoC) even before starting its productivity makes it possible to validate the correct functioning of the systems, also avoiding the manufacture of defective chips. However, low-level design and system complexity makes verification and simulation more complicated and time consuming. The classification of the different levels of abstraction from lowest to highest generally depends on the estimation accuracy of the system performance and the speed of simulation. The RTL (Register Transfer Level) abstraction level allows efficient description at gate level with good precision. Therefore, RTL program are slowly simulated. Simulation speed usually depends on the size of the platform used, which is not the case for transaction level modeling (TLM) to achieve simulation speed based on the exchange of transactions between system modules. This work aims to give a detailed description of the different levels of abstraction with the main advantages, and disadvantages on the performances estimation side such as, energy consumption, precision, and speed. Furthermore, an overview of the most adequate memory architectures and interconnection networks, to aim the most suitable virtual platforms of simulation for SoC.

Il Transaction-level modeling (TLM) è attualmente uno stile di progettazione molto promettente per affrontare la crescente complessità dei sistemi embedded moderni. Un flusso di progettazione basato sul TLM prevede l’applicazione di diverse tecniche di verifica in base al sistema che si sta progettando e all’esaustività dei risultati che si intende raggiungere. Il flusso di progettazione generalmente richiede uno spostamento da o verso un livello di astrazione più basso, sia per scopi di progettazione che di verifica. Da un lato, il raffinamento da TLM a RTL viene effettuato per avvicinarsi alla realizzazione fisica del sistema che si sta progettando. Dall’altro lato, l’astrazione da RTL a TLM consente di riutilizzare componenti di terze parti o già sviluppate, e di integrarle all’interno di una descrizione a livello di sistema, ottenendo così una riduzione del tempo e dei costi di progettazione e un aumento della velocità di simulazione. Infine, un ulteriore passo di raffinamento consiste nella sintesi a livello gate, che avvicina ulteriormente il design alla sua realizzazione fisica. A questo livello la generazione del test è tipicamente un’attività lunga e dispendiosa, quindi si possono adottare tecniche volte a ridurre tali tempi di calcolo.
Transaction-level modeling (TLM) is nowadays a promising design style to deal with the increasing complexity of modern embedded systems. A TLM-based flow involves different verification techniques according to the system being designed and the exhaustiveness of the results to be achieved. The design flow may involve a transition from or to a lower abstraction level (RTL), both for design and verification purposes. Refinement from TLM to RTL is performed to move closer to the physical realization of the system being designed. On the other hand, abstraction from RTL to TLM allows to reuse third-party or already developed components and to integrate them into a system-level design, thus gaining a reduction of design time and costs and an increase in simulation speed. Finally, a further refinement step consists of gate-level synthesis, which brings the design even closer to its physical realization. At this level, test generation is typically a time-consuming activity, so techniques can be adopted to reduce such computation times.

Model based verification has been the bedrock of electronic design automation. Over the past several years, system modeling has evolved to keep up with improvements in process technology fueled by Moore’s law. Modeling has evolved to keep up with the complexity of applications resulting in various levels of abstractions. The design automation industry has evolved from transistor level modeling to gate level and eventually to register transfer level (RTL). These models have been used for simulation based verification, formal verification and semiformal verification. With the advent of multicore systems, RTL modeling and verification are no longer feasible. Furthermore, the software content in most modern designs is growing rapidly. The increasing software content, along with the size, complexity and heterogeneity of multicore systems, makes RTL simulation extremely slow for any reasonably sized system. This has made system verification the most serious obstacle to time to market. The root of the problem is the signal-based communication modeling in RTL. In any large design there are hundreds of signals that change their values frequently during the execution of the RTL model. Every signal toggle causes the simulator to stop and reevaluate the state of the system. Therefore, RTL simulation becomes painfully slow. To overcome this problem, designers are increasingly resorting to modeling such complex systems at higher levels of abstraction than RTL. Transaction level models (TLMs) have emerged as the next level of abstraction for system design. However, well defined TLM semantics are needed for design automation at the transaction level. In this chapter, we present transaction level model automation for multicore systems based on well defined TLM semantics. TLMs replace the traditional signal toggling model of system communication with function calls, thereby increasing simulation speed. TLMs are already being used for executable specification of multicore designs, for analysis, fast simulation, and debugging. They play an important role in early application development and debugging before the final prototype has been implemented. We discuss essential issues in TLM automation and also provide an understanding of the basic building blocks of TLMs.