Bibliographies thématiques / Progettistica hardware e software

Littérature scientifique sur le sujet « Progettistica hardware e software »

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Publié le 11 mars 2023

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Articles de revues sur le sujet "Progettistica hardware e software"

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Breazeale, Vicki. « Software/Hardware ». Journal of Nutrition Education 17, no 4 (octobre 1985) : 162. http://dx.doi.org/10.1016/s0022-3182(85)80086-8.

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Kellerhoff, Peter. « Software überflügelt Hardware ». VDI nachrichten 74, no 28-29 (2020) : 3. http://dx.doi.org/10.51202/0042-1758-2020-28-29-3.

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Gupta, P. « Hardware-software codesign ». IEEE Potentials 20, no 5 (2002) : 31–32. http://dx.doi.org/10.1109/45.983337.

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Jerraya, A. « Hardware-software codesign ». IEEE Design and Test of Computers 17, no 1 (janvier 2000) : 92–99. http://dx.doi.org/10.1109/mdt.2000.825680.

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Harris, I. G. « Hardware/software covalidation ». IEE Proceedings - Computers and Digital Techniques 152, no 3 (2005) : 380. http://dx.doi.org/10.1049/ip-cdt:20045095.

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Perel, Morton L. « Hardware, Software, Brainware ». Implant Dentistry 16, no 1 (2007) : 1. http://dx.doi.org/10.1097/id.0b013e3180327609.

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Randell, Brian. « Hardware/software tradeoffs ». ACM SIGARCH Computer Architecture News 13, no 2 (juin 1985) : 19–21. http://dx.doi.org/10.1145/1296935.1296938.

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Day, Charles. « Software Makes Hardware ». Computing in Science & ; Engineering 10, no 6 (novembre 2008) : 104. http://dx.doi.org/10.1109/mcse.2008.156.

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Gramm, Andreas. « Hardware & ; Software ». LOG IN 31, no 2-3 (janvier 2011) : 118–21. http://dx.doi.org/10.1007/bf03323739.

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Bray-Garretson, Helen, et Richard O'Connor. « Hardware, Software, Etc. » Contemporary Psychology : A Journal of Reviews 38, no 2 (février 1993) : 214–15. http://dx.doi.org/10.1037/033080.

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Thèses sur le sujet "Progettistica hardware e software"

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Taylor, Ramsay G. « Verification of hardware dependent software ». Thesis, University of Sheffield, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.575744.

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Many good processes exist for ensuring the integrity of software systems, Some are analysis processes that seek to confirm that cer- tain properties hold for the system, and these rely on the ability to infer a correct model of the behaviour of the software, To ensure that such inference is possible many high-integrity systems are writ- ten in "safe" language subsets that restrict the program to constructs whose behaviour is sufficiently abstract and well defined that it can be determined independent of the execution environment. This nec- essarily prevents any assumptions about the system hardware. but consequently makes it impossible to use these techniques on software that must interact with the hardware. such as device drivers. This thesis addresses this shortcoming by taking the opposite approach: if the analyst accepts absolute hardware dependence - that the analysis will only be valid for a particular target system: the hardware that the driver is intended to control -- then the specifica- tion of the system can be used to infer the behaviour of the software that interacts with it, An analysis process is developed that operates on disassembled executable files and formal system specifications to produce CSP-OZ formal models of the software's behaviour, This analysis process is implemented in a prototype called Spurinna. that is then used in conjunction with the verification tools Z2SAL, the SAL suite, and IsabelleHOL. to demonstrate the verification of prop- erties of the software.
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Hilton, Adrian J. « High integrity hardware-software codesign ». Thesis, Open University, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.402249.

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Edmison, Joshua Nathaniel. « Hardware Architectures for Software Security ». Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/29244.

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The need for hardware-based software protection stems primarily from the increasing value of software coupled with the inability to trust software that utilizes or manages shared resources. By correctly utilizing security functions in hardware, trust can be removed from software. Existing hardware-based software protection solutions generally suffer from utilization of trusted software, lack of implementation, and/or extreme measures such as processor redesign. In contrast, the research outlined in this document proposes that substantial, hardware-based software protection can be achieved, without trusting software or redesigning the processor, by augmenting existing processors with security management hardware placed outside of the processor boundary. Benefits of this approach include the ability to add security features to nearly any processor, update security features without redesigning the processor, and provide maximum transparency to the software development and distribution processes. The major contributions of this research include the the augmentation methodology, design principles, and a graph-based method for analyzing hardware-based security systems.
Ph. D.
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Blaha, Vít. « Hardware a software inteligentního spotřebiče ». Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221136.

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Nowadays, the interest in smart appliances, which enable consumption reduction or consumption shifting approach, grows up. Such appliances can react to actual situation in the distributional network. From the energy distributor point of view, the activity of these appliances brings improvement of stability in the distribution network, while for the end customer there is possibility of the saving money. This thesis describes a transformation of standard fridge to smart fridge controlled by microcomputer Raspberry Pi. The smart fridge can communicate with supervisor system and according to its instructions change its behavior (temperature set point). The appliance can be manually controlled by a group of buttons, while its state can be visualized on the alphanumeric display. Last but not least way to control the appliance is through a web interface. The thesis also describes design of printed circuit board (PCB), which is designed for connection of all necessary sensors and actuators to Raspberry Pi. Software equipment is designed in the C++ program language.
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Figueiredo, Boneti Carlos Santieri de. « Exploring coordinated software and hardware support for hardware resource allocation ». Doctoral thesis, Universitat Politècnica de Catalunya, 2009. http://hdl.handle.net/10803/6018.

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Multithreaded processors are now common in the industry as they offer high performance at a low cost. Traditionally, in such processors, the assignation of hardware resources between the multiple threads is done implicitly, by the hardware policies. However, a new class of multithreaded hardware allows the explicit allocation of resources to be controlled or biased by the software. Currently, there is little or no coordination between the allocation of resources done by the hardware and the prioritization of tasks done by the software.
This thesis targets to narrow the gap between the software and the hardware, with respect to the hardware resource allocation, by proposing a new explicit resource allocation hardware mechanism and novel schedulers that use the currently available hardware resource allocation mechanisms.
It approaches the problem in two different types of computing systems: on the high performance computing domain, we characterize the first processor to present a mechanism that allows the software to bias the allocation hardware resources, the IBM POWER5. In addition, we propose the use of hardware resource allocation as a way to balance high performance computing applications. Finally, we propose two new scheduling mechanisms that are able to transparently and successfully balance applications in real systems using the hardware resource allocation. On the soft real-time domain, we propose a hardware extension to the existing explicit resource allocation hardware and, in addition, two software schedulers that use the explicit allocation hardware to improve the schedulability of tasks in a soft real-time system.
In this thesis, we demonstrate that system performance improves by making the software aware of the mechanisms to control the amount of resources given to each running thread. In particular, for the high performance computing domain, we show that it is possible to decrease the execution time of MPI applications biasing the hardware resource assignation between threads. In addition, we show that it is possible to decrease the number of missed deadlines when scheduling tasks in a soft real-time SMT system.
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Nilsson, Per. « Hardware / Software co-design for JPEG2000 ». Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5796.

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For demanding applications, for example image or video processing, there may be computations that aren’t very suitable for digital signal processors. While a DSP processor is appropriate for some tasks, the instruction set could be extended in order to achieve higher performance for the tasks that such a processor normally isn’t actually design for. The platform used in this project is flexible in the sense that new hardware can be designed to speed up certain computations.

This thesis analyzes the computational complex parts of JPEG2000. In order to achieve sufficient performance for JPEG2000, there may be a need for hardware acceleration.

First, a JPEG2000 decoder was implemented for a DSP processor in assembler. When the firmware had been written, the cycle consumption of the parts was measured and estimated. From this analysis, the bottlenecks of the system were identified. Furthermore, new processor instructions are proposed that could be implemented for this system. Finally the performance improvements are estimated.

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Endresen, Vegard Haugen. « Hardware-software intercommunication in reconfigurable systems ». Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2010. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-10762.

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In this thesis hardware-software intercommunication in a reconfigurable system has been investigated based on a framework for run time reconfiguration. The goal has been to develop a fast and flexible link between applications running on an embedded processor and reconfigurable accelerator hardware in form of a Xilinx Virtex device. As a start the link was broken down into hardware and software components based on constraints from earlier work and a general literature search. A register architecture for reconfigurable modules, a reconfigurable interface and a backend bridge linking reconfigurable hardware with the system bus were identified as the main hardware components whereas device drivers and a hardware operating system were identified as software components. These components were developed in a bottom-up approach, then deployed, tested and evaluated. Synthesis and simulation results from this thesis suggest that a hybrid register architecture, a mix of shift based and addressable register architecture might be a good solution for a reconfigurable module. Such an architecture enables a reconfigurable interface with full duplex capability with an initially small area overhead compared to a full scale RAM implementation. Although the hybrid architecture might not be very suitable for all types of reconfigurable modules it can be a nice compromise when attempting to achieve a uniform reconfigurable interface. Backend bridge solutions were developed assuming the above hybrid reconfigurable interface. Three main types were researched: a software register backend, a data cache backend and an instruction and data cache backend. Performance evaluation shows that the instruction and data cache outperforms the other two with an average acceleration ratio of roughly 5-10. Surprisingly the data cache backend performs worst of all due to latency ratios and design choices. Aside from the BRAM component required for the cache backends, resource consumption was shown to be only marginally larger than a traditional software register solution. Caching using a controller in the backend-bridge can thus provide good speedup for little cost as far as BRAM resources are not scarce. A software-to-hardware interface has been created has been created through Linux character device driver and a hardware operating system daemon. While the device drivers provide a middleware layer for hardware access the HWOS separates applications from system management through a message queue interface. Performance testing shows a large increase in delay when involving the Linux device drivers and the HWOS as compared to calls directly from the kernel. Although this is natural, the software components are very important when providing a high performance platform. As additional work specialized cell handling for reconfigurable modules has been addressed in the context of a MPEG-4 decoder. Some light has also been shed on design of reconfigurable modules in Xilinx ISE which can radically improve development time and decrease complexity compared to a Xilinx Platform Studio flow. In the process of demonstrating run time reconfigurations it was discovered that a clock signal will resist being piped through bus macros. Also broken functionality has been shown when applying run time reconfiguration to synchronous designs using the framework for self reconfiguration.

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Lu, Yandong. « Hardware/Software Partitioning of Embedded Svstems ». Thesis, University of Manchester, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.520747.

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King, Myron Decker. « A methodology for hardware-software codesign ». Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84891.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 150-156).
Special purpose hardware is vital to embedded systems as it can simultaneously improve performance while reducing power consumption. The integration of special purpose hardware into applications running in software is difficult for a number of reasons. Some of the difficulty is due to the difference between the models used to program hardware and software, but great effort is also required to coordinate the simultaneous execution of the application running on the microprocessor with the accelerated kernel(s) running in hardware. To further compound the problem, current design methodologies for embedded applications require an early determination of the design partitioning which allows hardware and software to be developed simultaneously, each adhering to a rigid interface contract. This approach is problematic because often a good hardware-software decomposition is not known until deep into the design process. Fixed interfaces and the burden of reimplementation prevent the migration of functionality motivated by repartitioning. This thesis presents a two-part solution to the integration of special purpose hardware into applications running in software. The first part addresses the problem of generating infrastructure for hardware-accelerated applications. We present a methodology in which the application is represented as a dataflow graph and the computation at each node is specified for execution either in software or as specialized hardware using the programmer's language of choice. An interface compiler as been implemented which takes as input the FIFO edges of the graph and generates code to connect all the different parts of the program, including those which communicate across the hardware/software boundary. This methodology, which we demonstrate on an FPGA platform, enables programmers to effectively exploit hardware acceleration without ever leaving the application space. The second part of this thesis presents an implementation of the Bluespec Codesign Language (BCL) to address the difficulty of experimenting with hardware/software partitioning alternatives. Based on guarded atomic actions, BCL can be used to specify both hardware and low-level software. Based on Bluespec SystemVerilog (BSV) for which a hardware compiler by Bluespec Inc. is commercially available, BCL has been augmented with extensions to support more efficient software generation. In BCL, the programmer specifies the entire design, including the partitioning, allowing the compiler to synthesize efficient software and hardware, along with transactors for communication between the partitions. The benefit of using a single language to express the entire design is that a programmer can easily experiment with many different hardware/software decompositions without needing to re-write the application code. Used together, the BCL and interface compilers represent a comprehensive solution to the task of integrating specialized hardware into an application.
by Myron King.
Ph.D.
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Nagaonkar, Yajuvendra. « FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation ». Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1294.pdf.

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Livres sur le sujet "Progettistica hardware e software"

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Ecker, Wolfgang, Wolfgang Müller et Rainer Dömer, dir. Hardware-dependent Software. Dordrecht : Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-1-4020-9436-1.

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Engineers, Society of Automotive, et SAE World Congress (2005 : Detroit, Mich.), dir. Software/hardware systems. Warrendale, Pa : SAE International, 2005.

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Gorsline, G. W. Computer organization : Hardware/software. 2e éd. Englewood Cliffs, N.J : Prentice-Hall, 1986.

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Micheli, Giovanni, et Mariagiovanna Sami, dir. Hardware/Software Co-Design. Dordrecht : Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-0187-2.

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Teich, Jürgen. Digitale Hardware/Software-Systeme. Berlin, Heidelberg : Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/978-3-662-06740-6.

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Haubelt, Christian, et Jürgen Teich. Digitale Hardware/Software-Systeme. Berlin, Heidelberg : Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-05356-6.

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Cady, Fredrick M. Software and hardware engineering. New York : Oxford University Press, 1997.

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M, Sibigtroth James, dir. Software and hardware engineering. New York : Oxford University Press, 2000.

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Gorsline, George W. Computer organization : Hardware/software. 2e éd. London : Prentice-Hall, 1986.

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Benjamin, Zee, dir. Computer hardware/software architecture. Englewood Cliffs, N.J : Prentice-Hall, 1986.

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Chapitres de livres sur le sujet "Progettistica hardware e software"

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Zemanek, Heinz. « Hardware — Software ». Dans Foundations of Computer Science, 9–19. Berlin, Heidelberg : Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/bfb0052073.

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Murata, Satoshi, et Haruhisa Kurokawa. « Hardware and Software ». Dans Springer Tracts in Advanced Robotics, 211–33. Tokyo : Springer Tokyo, 2012. http://dx.doi.org/10.1007/978-4-431-54055-7_9.

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Maul, Harald, et Georg Ziemes. « Software-Hardware-Schnittstellen ». Dans PLOTGRAF, 277–91. Wiesbaden : Vieweg+Teubner Verlag, 1987. http://dx.doi.org/10.1007/978-3-322-86095-8_5.

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Sucaet, Yves, et Wim Waelput. « Hardware and Software ». Dans Digital Pathology, 15–29. Cham : Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-08780-1_2.

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Bähring, Helmut. « Hardware/Software-Schnittstelle ». Dans Springer-Lehrbuch, 141–215. Berlin, Heidelberg : Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/978-3-662-12500-7_3.

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Bund, Elmar. « Hardware und Software ». Dans Einführung in die Rechtsinformatik, 13–18. Berlin, Heidelberg : Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-642-76103-4_3.

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Eles, Petru, Krzysztof Kuchcinski et Zebo Peng. « Hardware/Software Partitioning ». Dans System Synthesis with VHDL, 275–99. Boston, MA : Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2789-0_8.

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Niemann, Ralf. « Hardware/Software Partitioning ». Dans Hardware/Software Co-Design for Data Flow Dominated Embedded Systems, 47–131. Boston, MA : Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2803-3_4.

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Di Cataldo, Giuseppe. « Hardware and Software ». Dans Stack Frames, 1–19. Berkeley, CA : Apress, 2016. http://dx.doi.org/10.1007/978-1-4842-2181-5_1.

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Schaumont, Patrick R. « Hardware/Software Interfaces ». Dans A Practical Introduction to Hardware/Software Codesign, 259–301. Boston, MA : Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6000-9_9.

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Actes de conférences sur le sujet "Progettistica hardware e software"

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Lee, Robert P., Konstantinos Markantonakis et Raja Naeem Akram. « Provisioning Software with Hardware-Software Binding ». Dans ARES '17 : International Conference on Availability, Reliability and Security. New York, NY, USA : ACM, 2017. http://dx.doi.org/10.1145/3098954.3103158.

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Stitt, Greg, Frank Vahid, Gordon McGregor et Brian Einloth. « Hardware/software partitioning of software binaries ». Dans the 3rd IEEE/ACM/IFIP international conference. New York, New York, USA : ACM Press, 2005. http://dx.doi.org/10.1145/1084834.1084905.

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Stitt, Greg, et Frank Vahid. « Hardware/software partitioning of software binaries ». Dans the 2002 IEEE/ACM international conference. New York, New York, USA : ACM Press, 2002. http://dx.doi.org/10.1145/774572.774596.

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Reddi, Vijay Janapa, Meeta S. Gupta, Michael D. Smith, Gu-yeon Wei, David Brooks et Simone Campanoni. « Software-assisted hardware reliability ». Dans the 46th Annual Design Automation Conference. New York, New York, USA : ACM Press, 2009. http://dx.doi.org/10.1145/1629911.1630114.

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Keutzer, Kurt. « Hardware/software co-simulation ». Dans the 31st annual conference. New York, New York, USA : ACM Press, 1994. http://dx.doi.org/10.1145/196244.196458.

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Mills, Mike, et Greg Peterson. « Hardware/software co-design ». Dans the 1998 annual ACM SIGAda international conference. New York, New York, USA : ACM Press, 1998. http://dx.doi.org/10.1145/289524.289528.

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Dalpasso, Marcello, Alessandro Bogliolo et Luca Benini. « Hardware/software IP protection ». Dans the 37th conference. New York, New York, USA : ACM Press, 2000. http://dx.doi.org/10.1145/337292.337588.

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Scheeline, Alexander. « Hardware, software, brainware, noware ». Dans Photonics West '95, sous la direction de Gerald E. Cohn, Jeremy M. Lerner, Kevin J. Liddane, Alexander Scheeline et Steven A. Soper. SPIE, 1995. http://dx.doi.org/10.1117/12.206025.

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Stitt, Greg, Roman Lysecky et Frank Vahid. « Dynamic hardware/software partitioning ». Dans the 40th conference. New York, New York, USA : ACM Press, 2003. http://dx.doi.org/10.1145/775832.775896.

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Hummer, James, et Loïc Briand. « When hardware becomes software ». Dans the conference. New York, New York, USA : ACM Press, 1992. http://dx.doi.org/10.1145/143557.144016.

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Rapports d'organisations sur le sujet "Progettistica hardware e software"

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Leson, Joel L. Microcomputer Hardware and Software Management Program. Fort Belvoir, VA : Defense Technical Information Center, février 2001. http://dx.doi.org/10.21236/ada402387.

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Sprinkle, Jonathan, et Brandon Eames. Multicore Hardware Experiments in Software Producibility. Fort Belvoir, VA : Defense Technical Information Center, juin 2009. http://dx.doi.org/10.21236/ada502782.

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Aggarwal, Aneesh. Low Overhead Software/Hardware Mechanisms for Software Assurance and Producibility. Fort Belvoir, VA : Defense Technical Information Center, février 2007. http://dx.doi.org/10.21236/ada464355.

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Lei, Li. Hardware/Software Interface Assurance with Conformance Checking. Portland State University Library, janvier 2000. http://dx.doi.org/10.15760/etd.2320.

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Hopper, G. Future possibilities : Data, hardware, software and people. Office of Scientific and Technical Information (OSTI), janvier 1985. http://dx.doi.org/10.2172/6566336.

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Koch, Ed, Francis Rubinstein et Kiliccote Sila. Hardware/Software Solution Unifying DALI, IBECS, and BACnet. Office of Scientific and Technical Information (OSTI), décembre 2004. http://dx.doi.org/10.2172/878328.

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Friedman, M. A., P. Y. Tran et P. L. Goddard. Reliability Techniques for Combined Hardware and Software Systems. Fort Belvoir, VA : Defense Technical Information Center, février 1992. http://dx.doi.org/10.21236/ada256347.

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Minker. Parallellogic Programming and Parallel System Software and Hardware. Fort Belvoir, VA : Defense Technical Information Center, décembre 1990. http://dx.doi.org/10.21236/ada239228.

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Li, Juncao. An Automata-Theoretic Approach to Hardware/Software Co-verification. Portland State University Library, janvier 2000. http://dx.doi.org/10.15760/etd.12.

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Klymenko, Mykola V., et Andrii M. Striuk. Development of software and hardware complex of GPS-tracking. CEUR Workshop Proceedings, mars 2021. http://dx.doi.org/10.31812/123456789/4430.

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The paper considers the typical technical features of GPS-tracking systems and their development, as well as an analysis of existing solutions to the problem. Mathematical models for the operation of hardware and software of this complex have been created. An adaptive user interface has been developed that allows you to use this complex from a smartphone or personal computer. Methods for displaying the distance traveled by a moving object on an electronic map have been developed. Atmega162-16PU microcontroller software for GSM module and GPS receiver control has been developed. A method of data transfer from a GPS tracker to a web server has been developed. Two valid experimental samples of GPS-trackers were made and tested in uncertain conditions. The GPS-tracking software and hardware can be used to monitor the movement of moving objects that are within the coverage of GSM cellular networks.
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