Thèses sur le sujet « Polycrystalline Oxides »

Transparent conductive oxides (TCOs) and polycrystalline silicon (poly-Si) thin-films are very promising for application in photovoltaics. It is extremely challenging to develop cheap TCOs and poly-Si films to make photovoltaic devices. The aim of this thesis is to study sputtered aluminum-doped ZnO TCO and poly-Si films by solid-phase crystallization (SPC) for application in low-cost photovoltaics. The investigated aspects have been (i) to develop and characterize sputtered aluminum-doped ZnO (ZnO:Al) films that can be used as a TCO material on crystalline silicon solar cells, (ii) to explore the potential of the developed ZnO:Al films for application in ZnO:Al/c-Si heterojunction solar cells, (iii) to make and characterize poly-Si thin-films on different kinds of glass substrates by SPC using electron-beam evaporated amorphous silicon (a-Si) [referred to as EVA poly-Si material (SPC of evaporated a-Si)], and (iv) to fabricate EVA poly-Si thin-film solar cells on glass and improve the energy conversion efficiency of these cells by post-crystallization treatments. The ZnO:Al work in this thesis is focused on the correlation between film characteristics and deposition parameters, such as rf sputter power (Prf), working gas pressure (Pw), and substrate temperature (Tsub), to get a clear picture of film properties in the optimized conditions for application in photovoltaic devices. Especially the laterally non-uniform film properties resulting from the laterally inhomogeneous erosion of the target material are investigated in detail. The influence of Prf, Pw and Tsub on the structural, electrical, optical and surface morphology properties of ZnO:Al films is discussed. It is found that the lateral variations of the parameters of ZnO:Al films prepared by rf magnetron sputtering can be reduced to acceptable levels by optimising the deposition parameters. ZnO:Al/c-Si heterojunction solar cells are fabricated and characterized to demonstrate the feasibility of the fabricated ZnO:Al films for application in heterojunction solar cells. In this application, expensive indium-tin oxide (ITO) is usually used. Under the standard AM1.5G spectrum (100 mW/cm2, 25 ??C), the best fabricated cell shows an open-circuit voltage of 411 mV, a short-circuit current density of 30.0 mA/cm2, a fill factor of 66.7 %, and a conversion efficiency of 8.2 %. This is believed to be the highest stable efficiency ever reported for this type of cell. By means of dark forward current density-voltage-temperature (J-V-T) measurements, it is shown that the dominant current transport mechanism in the ZnO:Al/c-Si solar cells, in the intermediate forward bias voltage region, is trap-assisted multistep tunneling. EVA poly-Si thin-films are prepared on four types of glass substrates (planar and textured glass, both either bare or SiN-coated) based on evaporated Si, which is a cheaper Si deposition method than the existing technologies. The textured glass is realized by the UNSW-developed AIT process (AIT = aluminium-induced texture). The investigation is concentrated on finding optimized process parameters and evaluating film crystallization quality. It is found that EVA poly-Si films have a grain size in the range 0.8-1.5 ??m, and a preferential (111) orientation. UV reflectance and Raman spectroscopy measurements reveal a high crystalline material quality, both at the air-side surface and in the bulk. EVA cells are fabricated in both substrate and superstrate configuration. Special attention is paid to improving the Voc of the solar cells. For this purpose, after the SPC process, the samples receive the two post-crystallization treatments: (i) a rapid thermal anneal (RTA), and (ii) a plasma hydrogenation. It is found that two post-crystallization treatments more than double the 1-Sun Voc of the substrate-type cells. It is demonstrated that RTA improves the structural material quality of the cells. Furthermore, a hydrogenation step is shown to significantly improve the electronic material quality of the cells. Based on the RTA???d and hydrogenated EVA poly-Si material, the first mesa-type EVA cells are fabricated in substrate configuration, by using sputtered Al-doped ZnO as the transparent front contact. The investigation is focused on addressing the correlation between the type of the substrate and cell performance. Optical, electrical and photovoltaic properties of the devices are characterized. It is found that the performance of EVA cells depends on the glass substrate topography. For cells on textured glass, the AIT texture is shown to have a beneficial effect on the optical absorption of EVA films. It is demonstrated that a SiN barrier layer on the AIT-textured glass improves significantly both the crystalline quality of the poly-Si films and the energy conversion efficiency of the resulting solar cells. For cells on planar glass, a SiN film between the planar glass and the poly-Si film has no obvious effect on the cell properties. The investigations in this thesis clearly show that EVA poly-Si films are very promising for poly-Si thin-film solar cells on glass.

The structural changes in polycrystalline indium oxide were studied before and after irradiation of samples, Xe+ ions with energy 140 and 300 keV, X-ray methods. Discovery, that irradiation leads to a change in the chemical composition of the oxide, accompanied by phase transformations. The main structure of the cubic oxide after irradiation contain macro and micro stresses, which depend on the energy irradiation. The increase in the relative integral intensity of radiation reflected from the planes of the cell on depth was observed. The maximum value observed at a depth of 1.5 m from the plane (510). The analyses of reflected the radiation found that the flux of photons remains constant - the atomic nuclei of oxide not change, increases the frequency, decreases the wavelength depend from the energy irradiation. In some directions in reflecting from the planes, the atoms are formed with different electron density, that connect whit presence of defects, which leads to appear of the forced oscillation, which increases the relative integral intensity of the reflected radiation. These processes are damped with increasing depth of the sample. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/35411

In the process of studying the mechanisms of influence of structural defects on properties in scandium oxide, the thermal and electrical effects in the temperature range 25 – 1800 C in a vacuum, in the struc-ture was of detected a gradual phase transition of the ordered cubic type C in a disordered type C1 in the temperature range of 400 – 1000 C. Phase transformation is accompanied by the difference of the conduc-tivity type of the charge carriers. Anion conductivity of charges in the structure of scandium oxide exist there is to 400 С, with the energy of conductivity charges 2.46 eV. In scandium oxide in the interval tem-peratures 400 – 1000 C in case there is a mixture of two types of conductivity anion and electronic. In the interval of temperatures 1600 – 1800 C in case there is a change of the chemical composition of the oxide on the content of oxygen. With the help of the mathematical model of calculation of the elements of the structure of the change in the size of the radii of oxygen and anionic vacancies, which coincides with the change of parameters of elementary cells in the transition of the structure of C in C1. When you are citing the document, use the following link http://essuir.sumdu.edu.ua/handle/123456789/35390

博士
國立中山大學
電機工程學系研究所
96
The purpose of this study is using titanium dioxide (TiO2) as gate oxide on thin film transistor (TFT) and discussed with their physical, chemical and electrical properties. Amorphous silicon (a-Si) and polycrystalline silicon (poly-Si) are used as substrates. The metal-organic chemical vapor deposition (MOCVD) and the liquid phase deposition (LPD) are used as the TiO2 growth methods. About the LPD growth method, ammonium hexafluoro-titanate ((NH4)2TiF6) and hexafluorotitanic acid (H2TiF6) are used as Ti sources. We are interested in two parts: (1) the growth mechanisms, physics properties, chemical properties and electrical properties of MOS structure; (2) the fabrication processes and electrical properties of devices. In the first part, we discuss the thin films characteristics on a-Si and poly-Si substrates. For the MOCVD growth method, the MOCVD-TiO2 film tends to form the poly structure. Poly structure has a higher dielectric constant, however, higher traps and dangling bonds also exist at the grain boundaries. Thus, poly structure of TiO2 film has a higher leakage current. For the LPD growth method, the film tends to form the amorphous structure. Amorphous structure has lower leakage current but also has lower dielectric constant. The film that grown from the (NH)2TiF6 source is called LPD-TiO2 film. The film that grown from the (NH)2TiF6 source is called LPD-TixSi(1-x)Oy film. Both films are incorporated with OH and F ions during the growth, the OH and F ions can be outgassed during the low temperature annealing process. In addition, appropriate F ions in the film can passivate the traps and dangling bonds. The low temperature treatments in N2 or O2 ambient and post-metallization annealing (PMA) are adopted to improve the film characteristics. On the other hand, the substrate is not a prefect structure (not a single structure). Thus the film may be influenced by substrate during the annealing treatment. In the second part, the electrical properties of TFT devices were discussed under the coplanar structure. There are several differences of the operation principle in TFT and MOSFET. A-Si and poly-Si are the un-doped substrates with many traps in the bulk. The channel should be occurred through the full depletion mode. The full depletion region is the substrate that under the gate electrode. Thus, the key point is kept the suitable thickness. Too thick, the channel can not appear. Too thin, the substrate may be over-etched. For ion implantation, due to the thinner active layer, the ion implantation energy should be lowed. In addition, the activation temperature and activation time should be adjusted suitable. We have fabricated the TFT devices with the MOCVD-TiO2 as gate oxide on poly-Si substrate. From the I-V characteristics, the Kink effect can be observed. However, the Ion/Ioff ratio is still low. We must further study how to increase the Ion/Ioff ratio.

A kinetic study on polycrystalline platinum (Pt) in sulphuric acid is presented. An electrochemical kinetic mechanism of Pt oxide reduction and surface oxide structures are proposed. The reduction reaction was studied by cyclic voltammetry (CV) and various potential programs that combine sweep and hold periods by an assembled analog instrumentation. The reduction peak was studied under three surface conditions: same oxide coverage θ and same potential E, different θ and same E, and same θ but different E, to determine the influence of θ and E on the peak potential and peak shape. The double-layer charge measured previously by dynamic electrochemical impedance spectroscopy (dEIS) was used to correct the CV baseline. Differential-equation-based models as a function of θ and E were investigated to simulate the oxide reduction and oxidation, and estimate kinetic parameters. A simple mechanism combining desorption and multi-layer growth mechanisms showed good fit with both the spread-out oxidation peak and the sharp reduction peak. A microscopic surface oxide growth model was proposed to explain the surface oxides reduction mechanism.
Graduate

We present results of measurements designed to study superconducting I-V scaling in samples of bulk $\rm YBa\sb2Cu\sb3O\sb{7-\delta}$ with varying morphologies, 1$\mu$m $\rm\leq\langle d\sb{g}\rangle\leq20\mu m$ and at selected magnetic fields, $0.5{\rm G}\leq H\leq10\ {\rm T}.$ I-V isotherm measurements performed near the superconducting transition on the samples are consistent with recent predictions of I-V scaling, with critical exponents $\nu\sim1.1-1.75$ and $\rm z\sim2.3-4.3.$ The values for $\nu$ are comparable to those previously reported. The values for z are consistent with those reported by Tieman and Hallock but are somewhat lower than what is predicted by the glassy models. The static exponent does not seem to display any morphology or magnetic field dependence. The dynamic exponent, however, does display some morphology dependance with z higher for the small grain size samples. Furthermore, the data shows some evidence for a crossover between low and high z values in increasing magnetic fields.

This thesis examines the excimer-laser-induced melting of ELA-prepared silicon films using in situ transient reflectance and transmission analysis. The results clearly show that these polycrystalline films, which consist of columnar grains in contact with SiO₂, can melt in a largely and remarkably 2-D manner. Based on the presently and previously obtained experimental results, as well as considering the thermal, thermodynamic, and kinetic aspects of the melting-transition-relevant details, we suggest a model that consists of grain-boundary-initiated melting, followed by lateral melting proceeding into the transiently superheated interior of the grains. Additional experiments are performed which demonstrate how this 2-D melting behavior at least stems intrinsically from the presence in the material of melt-prone grain boundaries and superheating-permitting Si/SiO₂ interfaces. Next, the phase and temperature evolutions of the irradiated films are investigated using a numerical simulation program, which incorporates key material, thermodynamic, and kinetic parameters. We find that the center portion of the grains during (partial) melting (1) corresponds to, especially at the SiO₂-passivated surface, the hottest regions of the films during rapid heating, and (2) remains entirely solid throughout the thickness of the film, as the maximum temperature sustained in these unmelted solids remains well below the superheating limit of silicon at the Si/SiO₂ interface. Lastly, we discuss, and substantiate with results obtained from numerical simulations, the role that the manifested dimensionality of melting plays in dictating the efficiency with which the ELA crystallization technique can generate microstructurally uniform polycrystalline materials. The current discovery regarding the 2-D nature of melting should be recognized and appreciated as a critical process-enabling element for ELA, as the scenario permits microstructure evolution of the grains to take place in an effective manner.

碩士
國立中山大學
電機工程學系研究所
94
When the size of display panel increased, the RC delay of TFTs became serious. High dielectric (high-k) materials used as the gate oxide can increase the gate oxide capacitance Co, which can induce a higher drain current, and higher aperture ratio. Therefore, low-k materials are used for inter-metal dielectrics. Thus, it can improve the RC delay. LPD-TiO2 film on a-Si and poly-Si technology and characterization of films were described in detail in this thesis. The highest dielectric constant of 11.76 and 29.54, and lowest leakage current density of 5.45×10-7A/cm2 at -0.45 MV/cm and 3.11×10-1 A/cm2 at 0.45 MV/cm for the O2-annealed of LPD-TiO2film on a-Si and poly-Si can be obtained.

碩士
長庚大學
電子工程學系
98
In this thesis, we used the Er2O3 high-k materials combined with fluorine implantation to improve gate insulator integrity for TFT application. At first, the Er2O3 high-k dielectrics were deposited by RF sputtering on polycrystalline silicon combined with fluorine implantation and post-RTA treatment to improve the electrical characteristics of the polysilicon high-k dielectrics. Using high-k material as gate dielectrics can effectively decrease the leakage current, since that can preserve the equivalent oxide thickness (EOT) and reduce the direct tunneling current. But there are existed in some problems about the high-k material such as high trap defects and reliability concern. Therefore, before the deposition of the Er2O3 high-k dielectric, the fluorine ion pre-treatment such as fluorine implantation and CF4 plasma were applied on polysilicon interface to passivate the trap defects and interface states between the high-k dielectric and polysilicon. Since the fluorine ion can passivate the dangling and weak Si-H bonds, furthermore, that can also pile up distributed at the poly-Si interface to form strong Si-F bonds after adequate rapid thermal annealing (8000C) leading to superior characteristics. According to the results, the optimum fluorine ions pre-treatment (1x1015cm-2) can effectively reduce the leakage current, enhance the breakdown electric field, and decrease charge trapping rate to obtain a better charge-to-breakdown for reliability improvement. But when the ion dosages increase more than 5 x1015 cm−2, the electrical characteristics were degraded due to the increase of trap states caused by the fluorine diffusion and segregation in the polysilicon.

博士
國立中山大學
電機工程學系研究所
96
This thesis is mainly proposed and discussed the characteristics of polycrystalline silicon thin film transistor putting forward and probing into four kinds of novel buried-oxide structures. Because of the shortcoming of the traditional polycrystalline silicon thin film transistor, like leakage current (On/Off state current), subthreshold swing, floating body effect (kink effect), self-heating effect, and short channel effect etc.. Thus, we propose and fabricate four kinds of novel structural polycrystalline silicon thin film transistors that are involved in the following, indicating to improve the critical issues of polycrystalline silicon thin film transistor mentioned above. 1. We propose and fabricate the multiple/dual trenched-body polycrystalline silicon thin film transistor. This proposed structure is demonstrated to obviously suppress the off-state leakage up to 70% reduction, comparing with the conventional device. Also, we survey the reliability of this proposed device included temperature and DC hot-carrier stress effects. We found that the trenched-body TFTs perform more rapid degradation than the conventional TFT does after the temperature and stress durations, but their electrical characteristics are still superior to the conventional counterparts. Importantly, we demonstrate that this proposed device have a dramatic potential to be a novel capacitorless 1T-DRAM, because of its large floating-body-charge storages. As the experiment, the large threshold voltage shift is examined apparently after a certain write and erase operations, leading to a manifest programming window. 2. We propose and fabricate the block-oxide polycrystalline silicon thin film transistor. This proposed structure can not only improve the leakage issue of conventional device seriously, but also avoid fluctuating threshold voltage attributed from the ultra-thin film effect. 3. We propose and fabricate the floating-body contact polycrystalline silicon thin film transistor. This structure is modified by the conventional contact window in order to effectively improve the kink effect, utilizing the bottom gate polycrystalline silicon thin film transistor. 4. Finally, we propose and simulate the non-continuous buried layer polycrystalline silicon thin film transistor. This structure built upon the field oxidation layer can effectively improve the self-heating effect and kink effect. Furthermore, this structure is simple to fabricate, practical, and completely compatible on CMOS technology.

碩士
國立中山大學
電機工程學系研究所
107
The main research goal of this paper is to use different deposition methods to prepare the gate oxide layer of polycrystalline silicon thin-film transistor (Poly-Si TFT), and study the effect of devices with different gate oxide deposition methods for Poly-Si TFTs. In this paper, the electron beam evaporation system (E-gun) of physical vapor deposition and the plasma enhanced chemical vapor deposition (PECVD) of chemical vapor deposition are used to prepare the gate oxide layers. This thesis discusses N-type polycrystalline-silicon thin-film transistor, P-type polycrystalline silicon thin-film transistor, and N-type metal oxide semiconductor field effect transistor (MOSFETs). Through the analysis of electrical diagrams, sub-threshold swing (SS), carrier mobility, interface trap state concentration (Nit), and current switching ratio (Ion/Ioff) are compared. The polycrystalline-silicon thin film transistor and metal oxide semiconductor field effect transistor are used to compare between single crystalline-silicon and polycrystalline silicon for two different gate oxide deposition methods. In this experiment, it was found that using different deposition methods has a large impact on the TFT electrical analysis of polycrystalline silicon. On the other hand, there is not so much difference in the electrical analysis of single-crystalline silicon MOSFETs. The main reason is probably related to the interface quality between the channel and the gate oxide. In this experiment, it was found that using E-gun is more effective than using PECVD to deposit the gate oxide layer on n-type transistor. It is inferred that E-gun can control the film thickness of the coating and the quality of the interface more effectively to reduce the electrical performance of the defect on the transistor.

博士
國立清華大學
材料科學工程學系
97
The photoanode of dye-sensitized solar cell is composed of polycrystalline n-type oxide semiconductors, including nanostructured TiO2 or ZnO and transparent F-doped SnO2 electrode. The functions of nanostructured layers are to adsorb dye and to transport injected photo electrons. The analysis on electron transport in photoanode according to the energetic perspective illustrates that the interfacial Schottky barrier and grain boundary back-to-back Schottky barrier which restrict electron transport theoretically exist in the photoanodic materials. The former results from the difference of band structure between the nanostructured layer and the transparent electrode, and the latter is attributed to the nature of polycrystalline oxide semiconductor in the nanostructured layer. In order to promote the electron collection efficiency in photoanode, it is necessary to suppress the influence of the energetic barriers on electron transport. Introducing transparent Al-doped ZnO electrode into photoanode could eliminate the interfacial Schottky barrier. By using sol-gel method with the three-steps annealing procedure, it succeeded in preparing the Al-doped ZnO film with high transmittance and low resistivity. The origin of electric conduction of sol-gel derived AZO films is verified as the combining effect of the high temperature annealing to enhance crystal quality that provides higher mobility of electrons and the reduction annealing to release the localized electrons caused by oxygen absorption. According to the deductions from near infrared transmittance spectra based on Drude model, an effective method to improve electronic conduction is obtained. By modifying the preheating procedure, the grains of Al-doped ZnO films become smaller and more defected, resulting in better electrical conductivity. The results of impedance analysis demonstrated that the function of hydrogen annealing is to destroy the energetic barriers at grain boundaries and releases free electrons which are evidenced by the presence of parallel resistor-capacitor circuit, constant phase element and short Warburg element in equivalent circuits. It manifests that the energetic barrier which restrict electron transport is able to be destroyed. The existence of grain boundary barriers in the polycrystalline oxide semiconductors applied to photoanodic nanostructured layer (mesoporous TiO2, mesoporous ZnO, and nanowired ZnO) is verified by preparing samples with adequate structures and employing precise impedance analysis. The formation of the grain boundary barriers is dominated by material structural characteristics, such as density of lattice defects, crystalline orientation, and grain sizes. Three types of grain boundary barriers are observed in this study. The analysis for the samples with different sintering temperature showed that the characterization of grain boundary barrier is governed by the depth of depletion region determined by the grain size and defect density at grain boundary. Furthermore, it is also manifested that hydrogen annealing could destroy the grain boundary barriers which restrict injected photoelectron transport in the photoanodic nanostructured layer via impedance spectroscopy. The destruction of barriers seems to increase the short current of dye-sensitized solar cell.

博士
國立陽明大學
臨床醫學研究所
88
Current efforts of new stent technology have been aimed largely at the improvement of intravascular stent biocompatibility. Among the chemical characteristics of metallic stents, surface oxide corrosion properties are paramount. Using our unique technique, the currently marketed 316 L stainless steel and nitinol stent wires covered with polycrystalline oxide were chemically etched and then passivated to form amorphous oxide. Excellent metallic stent corrosion resistance with an amorphous oxide surface was demonstrated in our previous in vitro study. For in vivo validation, we compared the corrosion behavior of different oxide surfaces on various forms of test wires in the abdominal aorta of mongrel dogs using open-circuit potential and cyclic anodic polarization measurements. After conduction, the retrieved test wires were observed under scanning electron microscope (SEM). No passivity breakdown was found for wires covered with amorphous oxide, while wires with polycrystalline oxide showed breakdown at potentials between +0.2 to + 0.6 V. SEM showed that severe pitting or crevice corrosion occurred on the surface of polycrystalline oxide, while the surface of amorphous oxide was free of degradations in our experiment. We have demonstrated that this amorphous oxide coating on metallic material provides better corrosion resistance, but whether the corrosion products released from the wires with polycrystalline oxide are harmful to the surrounding tissue or not? This issue needs further be clarified. Although both 316 L stainless steel and nitinol are most popular materials of intravascular stents, there are still few confirmative biocompatibility data available, especially in vascular smooth muscle cells. The released nickel ions have been proven to be toxic to cultured fibroblasts but the potential cytotoxicity of stent corrosion products on vascular smooth muscle cells has still not been highlighted. In this doctoral thesis research, the 316 L stainless steel and nitinol wires were corroded in Dulbecco''s modified Eagle''s medium applied with constant electrochemical breakdown voltage, and the supernatant and precipitates of corrosion products were prepared as culture media. The dose and time effects of different concentrations of corrosion products on the growth and morphology of smooth muscle cells were evaluated with [3H]-thymidine uptake ratio and cell cycle sorter. Both the supernatant and precipitates of the corrosion products were toxic to the primary cultured rat aortic smooth muscle cells. The growth inhibition was correlated well with the increased concentrations of the corrosion products. For nitinol wire, small growth stimulation was found with released nickel concentration of 0.95±0.23 ppm, but this stimulation effect was not observed for 316 L stainless steel wires with mild leaching. The growth inhibition became significant when the nickel concentration was above 9 ppm for nitinol wires and above 11.7 ppm for 316 L stainless steel wires. The corrosion products also altered cell morphology, induced cell necrosis and decreased cell numbers. The cell growth inhibition occurred at the G0/G1 to S transition phase. This was the first study to demonstrate the cytotoxicity of corrosion products of current nitinol and 316 L stainless steel stent wires on smooth muscle cells, which might affect the post- stenting neointimal hyperplasia and the patency rate of cardiovascular stents. In conclusion, this thesis study demonstrated that in comparison with polycrystalline oxide, amorphous oxide coating on metallic material provides better corrosion resistance, not only in vitro but also in vivo, and it is superior not only in strength safety but also in medical device biocompatibility.

碩士
國立中央大學
機械工程學系在職專班
102
There are some conclusions gotten from the experiment. The surface roughness and average friction coefficient are 0.092μm and 0.33μ by traditional mechanical grinding process; the surface roughness and average friction coefficient are 0.051μm and 0.10μ by adding 0.5% graphene into solution. The latter surface roughness and friction coefficient is 1.8 times and 3.3 times compared to the former. The research shows that the tribological properties of graphene reduce the friction coefficient of solution and improve the surface roughness on workpiece. The research can be applied to grinding process of silicon wafer. The method can not only simplify the experiment steps but also enhance the process efficiency. The research is expected to be an application reference for industry and academic area.

碩士
國立臺灣師範大學
機電工程學系
104
In this work, the low-temperature plasma treatment was employed to modify the polarity of tin-oxide (SnO) semiconductor and investigated the potential applications of SnO thin-film transistors. The intrinsic p-type SnO TFT showed a low threshold voltage of -0.81 V, a field-effect mobility of 5.4 cm2 V −1 s −1 , and on/off current ratio of 2.28×103. To further improve the performance of intrinsic TFT devices, the low-temperature fluorine plasma treatment was conducted on p-type SnO channel. Under a variety of experimental comparison, the p-type SnO TFT with fluorine plasma treatment showed the significant improvement on current ratio by at least one order of magnitude (7.7x105), which could be attributed to the passivation effect of fluorine atoms on SnO channel. We also investigate the oxygen plasma effect on intrinsic p-type SnO channel. After an appropriate oxygen plasma treatment, the p-type SnO channel transferred to be n-type one due to the increase of oxygen concentration. The optimal n-type SnO TFT exhibited a threshold voltage of -1.49 V, a high field-effect mobility of 30 cm2 V −1 s −1, and on/off current ratio of 7.8x103. Therefore, the channel modification engineering by simple plasma treatment could be useful for the fabrication of low-temperature electronics. Besides, the illumination test of visible light was also performed to evaluate the carrier response between n- and p-type tin-oxide channels. The current response of transistor dependent to bandgap of SnO channel (n- or p-type) and light wavelength showed the potential application of Photodetector.

博士
國立中山大學
物理學系研究所
100
In order to meet the requests of the application as pixel switch and current driver in next generation active-matrix liquid crystal displays (AMLCD) and active-matrix organic light-emitting diodes (AMOLED). The materials of low temperature poly-silicon (LTPS) and metal-oxide are supposed to be the most potential material for active layer of thin-film transistors (TFTs) due to their high mobility compared to the traditional amorphous silicon TFTs. Therefore, in order to make the LTPS TFTs and metal-oxide TFTs affordable for the practical applications, the understanding of instability and reliability is critically important. In the first part, we studied the nonvolatile memory characteristics of polycrystalline-silicon thin-film-transistors (poly-Si TFTs) with a silicon-oxide-nitride-oxide-silicon (SONOS) structure. As the device was programmed, significant gate induced drain leakage current was observed due to the extra programmed electrons trapped in the nitride layer which. In order to suppress the leakage current and thereby avoid signal misidentification, we utilized band-to-band hot hole injection method to counteract programmed electrons and this method can exhibit good sustainability because the injected hot holes can remain in the nitride layer after repeated operations. On the other hand, we also investigated the degradation behavior of SONOS-TFT under off-state stress. After the electrical stress, the significant on-state degradation indicates that the interface states accompanied with hot-hole injection. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Furthermore, we also performed the identical off-state stress for the device with different memory states. The different degradation behavior under different memory states is attributed to the different overlap region of injected holes and trap states. In the second part, the degradation mechanism of indium-gallium-zinc oxide (IGZO) thin film transistors (TFTs) caused by gate-bias stress performed in the dark and light illumination was investigated. The parallel threshold voltage indicates that charge trapping model dominates the degradation behavior under positive gate-bias stress. However, the degradation of negative gate bias stress is much slighter than the positive gate bias stress since the IGZO material is hard to induced hole inversion layer. In addition, the hole mobility is much lower than electron resulting in ignorable hole trapping effect. On the other hand, the identical positive and negative gate bias stress performed under light illumination exhibit opposite degradation behavior compared with dark stress. This degradation variation under dark and light illumination can be attributed to the effectively energy barrier variation of electron and hole trapping. Furthermore, to further investigate the light induced instability for IGZO TFTs, the device with and without a SiOx passivation were investigated under light illumination. The experiment results indicate that oxygen adsorption and desorption dominate the light induced instability for unpassivated device and the trap states caused during the passivation layer deposition process will induce apparent subthreshold photo-leakage current under light illumination. In the third part, we investigated the degradation mechanism of IGZO TFTs under hot-carrier and self-heating stress. Under hot-carrier stress, except the electron trapping induced positive Vt shift, an apparent on-current degradation behavior indicates that trap states creation. On the other hand, the identical hot-carrier stress performed in the asymmetric source/drain structure exhibits different degradation behavior compared with symmetric source/drain structure. For asymmetric structure, the strong electrical field in the I-shaped drain electrode will induce channel hot electron injection near the drain side and cause asymmetric threshold voltage degradation. In this part we also investigated the degradation behavior under self-heating stress. The apparent positive threshold voltage (Vt) shift and on-current degradation indicate that the combination of trap states generation and electron trapping effect occur during stress. The trap states generation is caused by the combination of Joule heating and the large vertical field. Moreover, the Joule heating generated by self-heating operation can enhance electron trapping effect and cause larger Vt shift in comparison with the gate-bias stress. Finally, the electrical properties and photo sensitivity of dual gate IGZO TFTs were investigated. The asymmetric electrical properties and photo sensitivity under top gate and bottom gate operation is attributed to the variation of gate control region. Furthermore, the obvious asymmetric photo sensitivity can be utilized to the In-cell touch panel technology and lower the process cost compared with the traditional a-Si TFTs due to the elimination of black matrix.

博士
國立交通大學
電子工程系所
92
In this dissertation, for the sake of system-on-a-chip (SOC), silicon-on-insulator (SOI) and Bipolar-CMOS-DMOS (BCD) technology have been studied because of its superior isolation characteristics and mixture of the analog functions of bipolar, digital design of CMOS and high-voltage elements of DMOS on the same chip. In order to improve breakdown voltage from less reduced-surface-field (RESURF) effect of SOI devices, the step doping profile are investigated instead of complicated linearly graded doping profile by the distinct doping region along lateral direction. In order to stride forward the future integrations on any substrates, the LTPS LDMOS using excimer laser crystallization has been demonstrated by combination of the thin film technology and power device architecture. The LTPS LDMOS at 400 C substrate heating during excimer laser annealing will be used to expect to be a future driver device in system-on-a-panel (SOP) and three-dimensional (3-D) circuit integrations. Additionally, in order to comprehend heat dissipation in 3-D integration circuits, analyses of thermal problems in 3-D circuits are necessary. First, traditional Bipolar-CMOS-DMOS (BCD) technology, which is designed for only lateral bipolar (Bipolar, 12 V BVCEO and 25 V BVCBO), complementary metal oxide semiconductor (CMOS, 1.2 V threshold voltage) and double diffused metal oxide semiconductor (DMOS, 40 V breakdown voltage) transistors on the bulk silicon wafer, has been successfully utilized directly to fabricate silicon-on-insulator lateral-double -diffused-metal-oxide-semiconductor (SOI LDMOS) for the first time without changing any trial parameters. To simultaneously display the characteristics of high-power, high-speed and high-frequency, the results of output characteristics, switch and microwave performance must be moderate instead of individual optimum. Finally, according to the experimental results, it is proved that Bulk-BCD technology simultaneously enables high speed, high frequency and high blocking voltage applications�osuch as those in high-voltage integrated circuit switches (ns-range) and RF power amplifiers (MHz range to GHz range)�ousing a SOI wafer. In the study of step doping profile, a partition method is proposed to analyze the high-voltage step-doping silicon on insulator lateral insulated gate bipolar transistor (Step-Doping SOI-LIGBT) structure. The on-state characteristics will be present with the similar forward voltage drop (Vce) value between the step doping and linearly graded doping devices. The breakdown voltage can be deduced by the partition mid-point method and the corresponding breakdown electric field will also be fingered out in the step drift region. Furthermore, in order to reduce the undesirable additional masks, the degraded factor (D) is developed to evaluate the minimum number of frames with the better performance. Eventually, a 660 V step analytical results will be exemplified to compare with a 606.6 V MEDICI simulation, which shows very good agreement by this proposed method. In the study of future SOP and 3-D integrations, a new low-temperature polycrystalline silicon high-voltage LDMOS (LTPS HVLDMOS) using excimer laser crystallization has been proposed for the first time. However, in order to enhance LTPS HVLDMOS characteristics, there are two starting points: 1) integrate the thin film technology with the power device, 2) clarify the requirement of excimer laser treatment for low temperature power devices. As a result, the ON/OFF current ratio after laser treatment is improved over 106 times than that before laser treatment at Ldrift=15-�慆 and Vds=25 V. The LTPS HVLDMOS after laser treatment also demonstrates the better trade-off between the specific on resistance and breakdown voltage against the previous HVTFTs by solid phase crystallization�osuch as semi-insulating (SI), metal-field-plated (MFP), and offset-drain (OD) HVTFTs. In order to further improve the quality of crystallized poly-Si thin films and the performance of LTPS LDMOS, low-temperature poly-Si lateral double diffused metal oxide semiconductor (LTPS LDMOS) with high voltage and very low on-resistance has been achieved using excimer laser crystallization at 400 �aC substrate heating for the first time. The ON/OFF current ratios were exhibited with 2.96 × 10^5 and 6.72 × 10^6 while operating at Vds=0.1 V and 10 V, respectively. The maximum current limit was up to 10 mA and maximum power limit could be enhanced over 1 Watt at Vds=90 V and Vgs=20 V. The Ron,sp with dimensions of W/Lch=600-um/12-um could be significantly decreased 6.67 × 102 times in the magnitude as compared with the traditional offset drain (OD) TFTs. At last part of this thesis, the issue of heat dissipation will be discussed because many potential applications require operation at elevated temperatures. The effects of a high temperature ambient are exacerbated by power dissipation which causes additional temperature rise within the device. Power devices are often expected to run hotter than other component, but the excessive temperature rise of an inherently problem device will often lead to catastrophic failure. Failure of a single power device can shut down a computer, bring to halt a motor-driven system, or stop a vehicle dead in its tracks. This problem is anticipated to be exacerbated in 3-D circuit integration because the same power generated in a 2-D chip will now be generated in a smaller 3-D chip size resulting in a sharp increase in the power density. Therefore, accurate characterization of the thermal properties of power transistors is critical to the reliability of the systems using these devices. In order to understand this problem, the different electrical characteristics between crystalline and polycrystalline high voltage devices will be studied and the thermal stability of the LTPS LDMOS between the room temperature and 400 C irradiation will also be discussed over the ambient temperatures of 300 K�{400 K. The results of ambient temperature variation in LTPS LDMOS at 400 C irradiation are demonstrated the less sensitivity than the LTPS LDMOS before laser irradiation and at room temperature irradiation. Hence, the LTPS LDMOS at 400 C irradiation is very suitable for future system-on-a-panel (SOP) applications with higher temperature reliability.