Bibliographies thématiques / NOVEL CURRENT COMPARATOR

Littérature scientifique sur le sujet « NOVEL CURRENT COMPARATOR »

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Publié le 16 janvier 2024

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Articles de revues sur le sujet "NOVEL CURRENT COMPARATOR"

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Arunabala, Dr C., P. V. Sai Ranjitha, Bomminayuni Likhitha Gunturu Sravya, Bonagiri Navyasree et Arumalla Mounika. « Design of Diversified Low Power and High-Speed Comparators using 45nm Cmos Technology ». International Journal of Innovative Technology and Exploring Engineering 11, no 5 (30 avril 2022) : 27–31. http://dx.doi.org/10.35940/ijitee.e9849.0411522.

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At Present, portable battery-operated devices are enhancing due to low power consumption and high-speed applications, The designed circuit with feedback are used to design novel circuits. If the comparator having feedback are without clock signal. The comparators are mainly designed to minimize the power consumption and with good accuracy because of clock signal, if the clock signal is there, it is used to drive the circuit with low current. But in the existed design the circuit is with high power and current. These drawbacks are overcome by using the projected designed comparator. The Projected comparator design is with reduced power consumption, propagation delay, currents and with a smaller number of transistors. The comparators are useful in analog to digital converters. And this is simulated by using 45 nm CMOS technology Cadence Virtuoso tool.
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Chavoshisani, Reza, Mohammad Hossein Moaiyeri et Omid Hashemipour. « A high-performance low-voltage current-mode min/max circuit ». COMPEL : The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 34, no 4 (6 juillet 2015) : 1172–83. http://dx.doi.org/10.1108/compel-10-2014-0245.

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Purpose – Current-mode approach promises faster and more precise comparators that lead to high-performance and accurate winner-take-all circuits. The purpose of this paper is to present a new high-performance, high-accuracy current-mode min/max circuit for low-voltage applications. In addition, the proposed circuit is designed based on a new efficient high-resolution current conveyor-based fully differential current comparator. Design/methodology/approach – The proposed design detects the min and max values of two analog current signals by means of a current comparator and a logic module. The comparator compares the values of the input current signals accurately and generates two digital control signals and the logic module determines the min and max values based on the controls signals. In addition, an accurate current copy module is utilized to copy the input current signals and convey them to the comparator and the logic module. Findings – The results of the comprehensive simulations, conducted using HSPICE with the TSMC 90 nm CMOS technology, demonstrate the high-performance and robust operation of the proposed design even in the presence of process, temperature, input current and supply voltage variations. For a case in point, for 5 μA differential input current the average propagation delay and power consumption of the proposed circuit are attained as 150 ps and 150 µW, respectively, which leads to more than 64 percent improvement in terms of power-delay product as compared with the most efficient design, previously presented in the literature. Originality/value – A new efficient structure for current-mode min-max circuit is proposed based on a novel current comparator design which is accurate, high-performance and robust to process, voltage and temperature variations.
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TANG, XIAN, et KONG PANG PUN. « A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC ». Journal of Circuits, Systems and Computers 20, no 01 (février 2011) : 15–27. http://dx.doi.org/10.1142/s0218126611007049.

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A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-μm CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73.19 μW under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.
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Fathi, Amir, Abdollah Khoei et Khayrollah Hadidi. « High Speed Min/Max Architecture Based on a Novel Comparator in 0.18-μm CMOS Process ». Journal of Circuits, Systems and Computers 24, no 04 (4 mars 2015) : 1550048. http://dx.doi.org/10.1142/s0218126615500486.

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This paper describes the design of a high speed min/max architecture based on a new current comparator. The main advantage of the proposed circuit which employs a novel preamplifier-latch comparator is the higher operating frequency feature in comparison with previous works. Because the comparator can work in voltage mode, the min/max structure can be redesigned either in voltage or current mode. The designed comparator is refreshed without any external clock. Therefore, it does not degrade the speed performance of proposed min/max structure. These features along with low power consumption qualify the proposed architecture to be widely used in high speed fuzzy logic controllers (FLCs). Post-layout simulation results confirm 3.4 GS/s comparison rate with 9-bit resolution for a 0.9 V peak-to-peak input signal range for the comparator and 800 MHz operating frequency for min/max circuit. The power consumption of whole structure is 912 μW from a 1.8 V power supply using TSMC 0.18-μm CMOS technology.
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Monika et Poornima Mittal. « A novel modified current comparator based on extremely low voltage high compliance current mirror ». International Journal of Information Technology 14, no 1 (28 octobre 2021) : 323–31. http://dx.doi.org/10.1007/s41870-021-00823-7.

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Ouremchi, Mounir, Karim El Khadiri, Ahmed Tahiri et Hassan Qjidaa. « Design of a Novel Current Mode Charge Pump for Very-Low-Voltage Applications in 130 nm SOI-BCD Technology ». International Journal of Circuits, Systems and Signal Processing 15 (18 mai 2021) : 461–69. http://dx.doi.org/10.46300/9106.2021.15.50.

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A novel charge pump with current mode control suitable to work under a very-low-voltage supply is proposed in this paper. The proposed charge pump consists of two sections. The first section is a power switches stage which consists of seven cascaded DEPMOS power switches. The second section is a low voltage stage which consists of a Low Voltage Level Shifter, Current Mode control, Follower Amplifier, Error Amplifier, Soft Start Comparator, and Skip mode & Over Voltage Comparator. The charge pump has been designed, simulated, and layout in Cadence using TSMC 130 nm SOI technology with LDMOS transistors, which have very low on-resistance. The input range of the charge pump is 2.7– 4.4 V, and it can supply up to 100 mA load current. The maximum efficiency is 90%, and the chip area is only 0.597 mm².
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Wang, Cheng, Zhanpeng Yang, Xinpeng Xing, Quanzhen Duan, Xinfa Zheng et Georges Gielen. « A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing ». Electronics 12, no 19 (27 septembre 2023) : 4062. http://dx.doi.org/10.3390/electronics12194062.

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This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works.
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He, Lin, Gang Li et Meng Tang. « Relaxation Oscillator Exploiting PTAT Hysteresis of Differential Schmitt Trigger ». Journal of Circuits, Systems and Computers 24, no 10 (25 octobre 2015) : 1550147. http://dx.doi.org/10.1142/s0218126615501479.

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In this paper, we proposed a novel relaxation oscillator to address the frequency variation caused by the comparator delay. The conventional operational transconductance amplifiers (OTAs)-comparator is replaced with a Schmitt trigger to significantly reduce the delay. This Schmitt trigger is implemented by a differential structure operating in the subthreshold region to generate a proportional to absolute temperature (PTAT) hysteresis. Both the voltage reference and the current source are made PTAT as well. The proposed oscillator can be made ultra-low power and have excellent frequency stability over process, voltage and temperature (PVT) variation.
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Bhatia, Veepsa, Neeta Pandey et Asok Bhattacharyya. « High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology ». International Journal of Electrical and Computer Engineering (IJECE) 6, no 1 (1 février 2016) : 90. http://dx.doi.org/10.11591/ijece.v6i1.8693.

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A novel power-speed efficient current comparator is proposed in this paper. It comprises of only CMOS inverters in its structure, employing a simple biasing method. The structure offers simplicity of design. It posesses the very desirable features of high speed and low power dissipation, making this structure a highly desirable one for various current mode applications. The simulations have been performed using UMC 90 nm CMOS technology and the results demonstrate the propagation delay of about 3.1 ns and the average power consumption of 24.3 µW for 300 nA input current at supply voltage of 1V.
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Bhatia, Veepsa, Neeta Pandey et Asok Bhattacharyya. « High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology ». International Journal of Electrical and Computer Engineering (IJECE) 6, no 1 (1 février 2016) : 90. http://dx.doi.org/10.11591/ijece.v6i1.pp90-98.

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A novel power-speed efficient current comparator is proposed in this paper. It comprises of only CMOS inverters in its structure, employing a simple biasing method. The structure offers simplicity of design. It posesses the very desirable features of high speed and low power dissipation, making this structure a highly desirable one for various current mode applications. The simulations have been performed using UMC 90 nm CMOS technology and the results demonstrate the propagation delay of about 3.1 ns and the average power consumption of 24.3 µW for 300 nA input current at supply voltage of 1V.
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Thèses sur le sujet "NOVEL CURRENT COMPARATOR"

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MONIKA. « DESIGN AND PERFORMANCE ANALYSIS OF NOVEL CURRENT COMPARATOR BASED ON EXTREMELY LOW VOLTAGE HIGH COMPLIANCE CURRENT MIRROR ». Thesis, 2021. http://dspace.dtu.ac.in:8080/jspui/handle/repository/20444.

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This thesis presents the novel structure of the current comparator which embraces the Extremely Low-Voltage High-Compliance Current Mirror (ELVHC CM) as the current differencing stage. The current comparator is a elementary unit of current mode applications. Their performance is found better than the voltage comparator in the literature. In the literature, the very first current comparator shows the 10 ns delay with higher resolution. Later many designs were proposed with specific advantages per application. In the current comparator, the current mirror (CM) plays a crucial role. CM provides the current differences that have to be measured. In this thesis, six types of CM have been discussed, analyzed, and simulated. Name of all these CMs are Simple current mirror, Wilson current mirror, Improved Wilson current mirror, Cascode current mirror, ELVHC CM, and BDQFG FVF CM. The first four CMs are the basic types of CM structures and the remaining two CMs are the advanced topology of CM. The significant parameters of CM which describe the overall performance of CM are Current transfer characteristics, PER, Compliance voltage, Bandwidth and input/output resistance. For basic CM structures i.e. Simple current mirror, Wilson current mirror, Improved Wilson current mirror, and Cascode current mirror, Current transfer characteristics, PER, Compliance voltage, and output resistance. All these basic four current mirror structures have been simulated on various technology nodes such as CMOS 180 nm, 90 nm, 45 nm, and FinFET 18 nm on the Cadence Virtuoso simulator and then compared based on technology node and the topology. If a comparison of basic four CM has seen technology-wise then 180 nm shown better performance among all technology nodes. Whereas, Simple CM shows 11.25% of PER for 180 nm technology node while 74.62% of PER is observed for 90 nm technology node, 12.58% for 45 nm, and 13.17% for FinFET 18 nm. Similarly, 0.1 V output compliance voltage is observed for all technology node of Simple CM and 45 nm technology node Simple CM depicted 199 MΩ output resistance which is greatest among all technology node pf Simple CM. Talking about Wilson CM 180 nm technology node shown best performance among all technology nodes as -16.17% of PER is spotted. Furthermore, minimum compliance voltage 0.2 V is seen for 90 nm technology node, and 168 MΩ of highest resistance is noticed for FinFET 18 nm technology node of Wilson CM. Improved Wilson CM experience similar v resistance as Wilson CM for all technology nodes. While mirroring accuracy is found quite similar of Improved Wilson CM and Cascode CM. But for Cascode CM 180 nm technology node shown lower output resistance and higher compliance voltage which is not good in practice, although FinFET Cascode CM depicted 293 MΩ of output resistance. Afterward, two advanced current mirrors named ELVHC CM and BDQFG FVF CM are discussed, analyzed, and simulated on Cadence Virtuoso Simulator. Their small signal analysis has been done with mathematical equations and Monte Carlo analysis is also carried out. Transfer characteristics, PER, and Output compliance voltage are calculated for these two CMs. Moreover in BDQFG FVF CM, bulk driven quasi floating gate and flipped voltage follower techniques and their working as been discussed. Based on the comparison of both CM it is concluded the ELVHC CM is better than BDQFG FVF CM. Also, it is observed that at 200 μA input current ELVHC CM depicted 0.03% of PER. Moreover, BDQFG FVF CM shown 0.12 V of minimum output compliance voltage while ELVHC CM presents 0.091 V. In conclusion, it is noticed that ELVHC CM’s performance is better than BDQFG FVF CM. Based on this statement a novel design of the current comparator has been proposed which comprises ELVHC CM as a current differencing stage. To find out the workability of the proposed design, a new proposed comparator is analyzed and simulated on a 180 nm technology node and compared with BDQFG FVF CM based current comparator. Where, majorly three parameters are calculated such as propagation delay, power, and PDP. It is noticed that both comparators have a resolution of 5 nA. Further, the proposed design depicts 74.2% and 30.2% propagation delay and power dissipation respectively less than BDQFG FVF CM based comparator. All these analyses show that the current comparator based on ELVHC CM’s performance is superior.
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Chapitres de livres sur le sujet "NOVEL CURRENT COMPARATOR"

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Bhatia, Veepsa, et Neeta Pandey. « A Novel Ultra Low Power Current Comparator ». Dans Communications in Computer and Information Science, 423–32. Singapore : Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-5427-3_45.

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Actes de conférences sur le sujet "NOVEL CURRENT COMPARATOR"

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Paglinawan, Arnold C., Charmaine C. Paglinawan, Shao-Chun Cheng et Wen-Yaw Chung. « A novel dual-modulation design low input impedance current comparator ». Dans TENCON 2012 - 2012 IEEE Region 10 Conference. IEEE, 2012. http://dx.doi.org/10.1109/tencon.2012.6412233.

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Ren, Shiyan, Yumeng Zhang et Donghui Cai. « A novel high-precision current adder based on dc comparator ». Dans 2012 Conference on Precision Electromagnetic Measurements (CPEM 2012). IEEE, 2012. http://dx.doi.org/10.1109/cpem.2012.6250932.

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Lin, Feipeng, Bo Liang, Haiming Shao et Hao Wang. « A Novel Method for Calibrating Automatic Direct Current Comparator Resistance Bridges ». Dans 2018 Conference on Precision Electromagnetic Measurements (CPEM 2018). IEEE, 2018. http://dx.doi.org/10.1109/cpem.2018.8500990.

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Bhatia, Veepsa, Mohini Madan, Baljeet Kaur, Neeta Pandey et Asok Bhattacharyya. « A novel CC-II based current comparator and its application as current mode flash ADC ». Dans 2013 International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT). IEEE, 2013. http://dx.doi.org/10.1109/mspct.2013.6782122.

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Khater, Faeka M. H., Mohamed I. Abu-Elsebah et Farouk I. Ahmed. « Novel Speed and Position Estimation in Field-Oriented Control of Induction Machine Drive System ». Dans ASME 1997 Design Engineering Technical Conferences. American Society of Mechanical Engineers, 1997. http://dx.doi.org/10.1115/detc97/vib-4501.

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Abstract This paper describes a novel technique which has been proposed to simplify field orientation control system. This technique depends on zero crossing detection of different waveform of stator fluxes using the comparator reference signal which control the inverter transistors. By using this technique it is available to update the position θ and current components in the rotational reference frame up to twelve times per cycle. As a result, the transformation from two phase stationary reference frame (SRF) to two phase rotating synchronously reference frame (RRF), has been canceled which leads to less consumption time in software. Thus control algorithm requires less time to be implemented via software for position detection and speed estimation.
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Scherer, Hansjörg. « Ultrastable Low-Noise Current Amplifier : A New Tool for Small Current Metrology ». Dans NCSL International Workshop & Symposium. NCSL International, 2017. http://dx.doi.org/10.51843/wsproceedings.2017.08.

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The Ultra stable Low-noise Current Amplifier (ULCA) is a user-friendly and superior alternative to existing instruments for small direct currents in the range between about 1 fA and 5 μA. The principle of the portable laboratory table-top device, operated at room temperature, is based on a novel dual-stage transimpedance amplifier concept. The total transimpedance of 1 GO is calibrated with a cryogenic current comparator with an uncertainty < 0.1 μO/O traceable to the quantum Hall resistance. The output voltage is measured with a voltmeter calibrated traced to the Josephson voltage standard. In addition to its electrometer function, in combination with a voltage source the ULCA also can be used as a current generator. Therefore, it represents a new tool for ultra-accurate small-current measurement and generation traceable to quantum electrical standards. It outperforms commercial devices and calibration setups used in metrology institutes by up to two orders of magnitude in accuracy. The unique features of the ULCA are the excellent stability of its transimpedance (drift less than 5 μO/O per year, short-term fluctuations over one week< 0.1 μO/O), its small temperature coefficient (typically about 0.2 μO/O per Kelvin), fast settling(difference to final value < 0.1 μA/A after 3 s), and the low input current noise of 2.4 fA/vHz. This enables measuring a direct current of 100 pA with a total relative uncertainty of 0.1 μA/A in about 10 h. Besides being excellently suited for R&D in small-current metrology (e.g. for research on single-electron pumps) the ULCA is also widely applicable for calibrations, for instance for electrometers, small-current sources, or high-value resistors. Corresponding fields (and specific examples) are electronic industry (ICs), medicine and biotechnology (dosimetry, radiation protection, DNA sequencers) as well as environmental monitoring (concentration measurements of small particles in air or aerosols), and lighting industry (photo current measurement). Framed by two patent applications, the technology was transferred from the Physikalisch-Technische Bundesanstalt (PTB) to a German company (Magnicon GmbH, Hamburg), which manufactures and markets the ULCA since 2016 licensed by PTB.
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Chao, Tien-Hsin. « Optical correlator using a LCTV CGH filter and a thresholding photodetector array chip ». Dans OSA Annual Meeting. Washington, D.C. : Optica Publishing Group, 1991. http://dx.doi.org/10.1364/oam.1991.thl2.

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An optical correlator using a CGH filter encoded in a liquid crystal television spatial light modulator (LCTV SLM) and a custom designed VLSI photodetector array chip is reported. A Burckhardt-type CGH filter was written in a commercially available thin film transistor-type LCTV SLM that contains 320 × 220 pixels and has a contrast ratio of ~100:1. Both gray scale and binary holographic images are reconstructed from the LCTV CGH. This CGH filter is successfully used in an optical correlator for pattern recognition experiments. To further enhance the system speed and discrimination capability, a novel CMOS 32 × 32 postprocessing photodetector array chip is designed and fabricated for the correlator peak detection. The two main novel features of this detector array are its thresholding capability and high speed. The thresholding capacity is achieved by building a comparator and logic circuits around each pixel of the detector array. Parallel detection across the entire output plane is done in each clock cycle. Digitized addresses of locations of all the correlation peaks that exceed the thresholding level are present in the output port. The speed of the detector is ~1-10 msec, depending upon the level of the thresholding current.
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