Bibliographies thématiques / Network-on-chip, Dataflow Computing, Performance, Framework

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Littérature scientifique sur le sujet « Network-on-chip, Dataflow Computing, Performance, Framework »

Auteur : Grafiati

Publié le 14 mars 2023

Mis à jour le 31 juillet 2025

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Articles de revues sur le sujet "Network-on-chip, Dataflow Computing, Performance, Framework"

Alam, Shahanur, Chris Yakopcic, Qing Wu, Mark Barnell, Simon Khan, and Tarek M. Taha. "Survey of Deep Learning Accelerators for Edge and Emerging Computing." Electronics 13, no. 15 (2024): 2988. http://dx.doi.org/10.3390/electronics13152988.

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The unprecedented progress in artificial intelligence (AI), particularly in deep learning algorithms with ubiquitous internet connected smart devices, has created a high demand for AI computing on the edge devices. This review studied commercially available edge processors, and the processors that are still in industrial research stages. We categorized state-of-the-art edge processors based on the underlying architecture, such as dataflow, neuromorphic, and processing in-memory (PIM) architecture. The processors are analyzed based on their performance, chip area, energy efficiency, and applica

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Fang, Juan, Sitong Liu, Shijian Liu, Yanjin Cheng, and Lu Yu. "Hybrid Network-on-Chip: An Application-Aware Framework for Big Data." Complexity 2018 (July 30, 2018): 1–11. http://dx.doi.org/10.1155/2018/1040869.

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Burst growing IoT and cloud computing demand exascale computing systems with high performance and low power consumption to process massive amounts of data. Modern system platforms based on fundamental requirements encounter a performance gap in chasing exponential growth in data speed and amount. To narrow the gap, a heterogamous design gives us a hint. A network-on-chip (NoC) introduces a packet-switched fabric for on-chip communication and becomes the de facto many-core interconnection mechanism; it refers to a vital shared resource for multifarious applications which will notably affect sys

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Muhsen, Yousif, Nor Azura Husin, Maslina Binti Zolkepli, Noridayu Manshor, Ahmed Abbas Jasim Al-Hchaimi, and A. S. Albahri. "Routing Techniques in Network-On-Chip Based Multiprocessor-System-on-Chip for IOT: A Systematic Review." Iraqi Journal For Computer Science and Mathematics 5, no. 1 (2024): 181–204. http://dx.doi.org/10.52866/ijcsm.2024.05.01.014.

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Routing techniques (RTs) play a critical role in modern computing systems that use network-on-chip (NoC) communication infrastructure within multiprocessor system-on-chip (MPSoC) platforms. RTs contribute greatly to the successful performance of NoC-based MPSoCs due to traffic congestion avoidance, quality-of-service assurance, fault handling and optimisation of power usage. This paper outlines our efforts to catalogue RTs, limitations, recommendations and key challenges associated with these RTs used in NoC-based MPSoC systems for the IoT domain. We utilized the PRISMA method to collect data

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Lin, Yanru, Yanjun Zhang, and Xu Yang. "A Low Memory Requirement MobileNets Accelerator Based on FPGA for Auxiliary Medical Tasks." Bioengineering 10, no. 1 (2022): 28. http://dx.doi.org/10.3390/bioengineering10010028.

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Convolutional neural networks (CNNs) have been widely applied in the fields of medical tasks because they can achieve high accuracy in many fields using a large number of parameters and operations. However, many applications designed for auxiliary checks or help need to be deployed into portable devices, where the huge number of operations and parameters of a standard CNN can become an obstruction. MobileNet adopts a depthwise separable convolution to replace the standard convolution, which can greatly reduce the number of operations and parameters while maintaining a relatively high accuracy.

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Sowmya B J and Dr Jamuna S. "Design of Area Efficient Network-On-Chip Router: A Comprehensive Review." International Research Journal on Advanced Engineering Hub (IRJAEH) 2, no. 07 (2024): 1895–908. http://dx.doi.org/10.47392/irjaeh.2024.0260.

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The number of uses for cutting-edge technologies has led to a further growth in a single chip's computational capacity. In this case, several applications want to build on a single chip for computing resources. As a result, connecting the IP cores becomes yet another difficult chore. The many-core System-On-Chips (SoCs) are being replaced by Network-On-Chip (NoC) as an on-chip connectivity option. As a result, the Network on Chip was created as a cutting-edge framework for those networks inside the System on Chip. Modern multiprocessor architectures would benefit more from a NoC architecture a

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Qi, Shengrong, Zekang Fan, Zhongzhen Sun, and Kefeng Ji. "Ship Target Detection in SAR Images Based on Improved YOLOv5 and Edge Deployment on Huawei Ascend." Journal of Physics: Conference Series 3055, no. 1 (2025): 012048. https://doi.org/10.1088/1742-6596/3055/1/012048.

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Abstract Aiming at the challenges faced in ship target detection in complex large scenes of spaceborne SAR images, such as difficulties in detecting small targets, severe target occlusion, large amounts of SAR data, and limited computing power of airborne/spaceborne computing units, this paper proposes a lightweight ship detection model based on the improved YOLOv5 and realizes the edge deployment of the algorithm in combination with the Huawei Ascend hardware platform. The main contributions include: 1) Rotating target detection framework: By introducing an angle classification head, the prob

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Sabah, Yousri. "Quantum-Inspired Temporal Synchronization in Dynamic Mesh Networks: A Non-Local Approach to Latency Optimization." Wasit Journal for Pure sciences 4, no. 1 (2025): 86–93. https://doi.org/10.31185/wjps.710.

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This paper presents a novel method for achieving temporal synchronization in Network-on-Chip (NoC) architectures, using optimization techniques derived from quantum mechanics. We provide a non-local temporal coordination framework to optimize network latency in dynamic mesh networks using quantum principles such as entanglement and superposition. A specialized router design using quantum-inspired control units incorporates the Quantum-Inspired Temporal Coordination Algorithm (QTCA) and Non-Local State Synchronization Protocol (NSSP), which are essential components of the proposed architecture.

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Sheng, Huayi, and Muhammad Shemyal Nisar. "Simulating an Integrated Photonic Image Classifier for Diffractive Neural Networks." Micromachines 15, no. 1 (2023): 50. http://dx.doi.org/10.3390/mi15010050.

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The slowdown of Moore’s law and the existence of the “von Neumann bottleneck” has led to electronic-based computing systems under von Neumann’s architecture being unable to meet the fast-growing demand for artificial intelligence computing. However, all-optical diffractive neural networks provide a possible solution to this challenge. They can outperform conventional silicon-based electronic neural networks due to the significantly higher speed of the propagation of optical signals (≈108 m.s−1) compared to electrical signals (≈105 m.s−1), their parallelism in nature, and their low power consum

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Apoorva, Reddy Proddutoori. "Optimistic Workload Configuration of Parallel Matrices On CPU." European Journal of Advances in Engineering and Technology 8, no. 8 (2021): 66–70. https://doi.org/10.5281/zenodo.12770771.

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This study compares and uses different feature parallelization techniques Fast Fourier Transform (FFT) and Discrete Wavelet Transform (DWT) for classification of matrices. Convolutional Neural Network (CNN) is used to determine the classifications. In the classification, CNN is a unique technique that can be effectively used as a classifier. This study helps to extract features in the most efficient way with less computing time in real life. The framework provides comprehensive and flexible APIs that enable efficient implementation of multi-threaded applications. To meet the real-time performa

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Sui, Xuefu, Qunbo Lv, Liangjie Zhi, et al. "A Hardware-Friendly High-Precision CNN Pruning Method and Its FPGA Implementation." Sensors 23, no. 2 (2023): 824. http://dx.doi.org/10.3390/s23020824.

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To address the problems of large storage requirements, computational pressure, untimely data supply of off-chip memory, and low computational efficiency during hardware deployment due to the large number of convolutional neural network (CNN) parameters, we developed an innovative hardware-friendly CNN pruning method called KRP, which prunes the convolutional kernel on a row scale. A new retraining method based on LR tracking was used to obtain a CNN model with both a high pruning rate and accuracy. Furthermore, we designed a high-performance convolutional computation module on the FPGA platfor

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Thèses sur le sujet "Network-on-chip, Dataflow Computing, Performance, Framework"

MAZUMDAR, SOMNATH. "An Efficient NoC-based Framework To Improve Dataflow Thread Management At Runtime." Doctoral thesis, Università di Siena, 2017. http://hdl.handle.net/11365/1011261.

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This doctoral thesis focuses on how the application threads that are based on dataflow execution model can be managed at Network-on-Chip (NoC) level. The roots of the dataflow execution model date back to the early 1970’s. Applications adhering to such program execution model follow a simple producer-consumer communication scheme for synchronising parallel thread related activities. In dataflow execution environment, a thread can run if and only if all its required inputs are available. Applications running on a large and complex computing environment can significantly benefit from the

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Chapitres de livres sur le sujet "Network-on-chip, Dataflow Computing, Performance, Framework"

Jegadeesan, R., and A. Devi. "Parallel Processing Frameworks on FPGA for High Throughput Neural Network Inference." In Smart Microcontrollers and FPGA Based Architectures for Advanced Computing and Signal Processing, 2025th ed. RADemics Research Institute, 2025. https://doi.org/10.71443/9789349552425-10.

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The increasing demand for real-time, energy-efficient, and high-throughput inference of deep neural networks has positioned FPGAs as a compelling hardware platform due to their inherent parallelism, reconfigurability, and customizability. This book chapter investigates advanced parallel processing frameworks on FPGAs tailored for neural network acceleration, emphasizing architectural strategies that balance throughput, latency, and resource constraints. A comprehensive analysis of data-level, task-level, pipeline, spatial, and hybrid parallelism is presented, with a focus on their synergistic

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Actes de conférences sur le sujet "Network-on-chip, Dataflow Computing, Performance, Framework"

Kim, Hanjoon, Seulki Heo, Junghoon Lee, Jaehyuk Huh, and John Kim. "On-Chip Network Evaluation Framework." In 2010 SC - International Conference for High Performance Computing, Networking, Storage and Analysis. IEEE, 2010. http://dx.doi.org/10.1109/sc.2010.35.

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Li, Yixiao, Yutaka Matsubara, Daniel Olbrys, Kazuhiro Kajio, Takashi Inada, and Hiroaki Takada. "Agile Software Design Verification and Validation (V&V) for Automated Driving." In FISITA World Congress 2021. FISITA, 2021. http://dx.doi.org/10.46720/f2020-ves-017.

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Automated Driving System (ADS) generally consists of 3 functions 1) Recognition, 2) Planning, 3) Control. Precise vehicle localization and accurate recognition of objects (vehicle, pedestrian, lane, traffic sign, etc.) are typically based on high-definition dynamic maps and data from multiple sensors (e.g. Camera, LiDAR, Radar). Planners, especially those for optimal path and trajectory, tend to be computationally intensive. Many applications in ADS use machine learning techniques such as DNN (Deep Neural Network), which further increase the demand for computing power. To parallelly process ma

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