Thèses sur le sujet « Low Thermal Budget »

Higher conversion efficiencies while reducing costs at the same time is the ultimate goal driving the development of solar cells. Multi-crystalline silicon has attracted considerable attention because of its high stability against light soaking. In case of solar grade multi-crystalline silicon the rigorous control of metal impurities is desirable for solar cell fabrication. It is the aim of this thesis to develop a new manufacturing process optimized for solar-grade multi-crystalline silicon solar cells. In this work the goal is to form solar cell emitters in silicon substrates by plasma immersion ion implantation of phosphine and posterior millisecond-range flash lamp annealing. These techniques were chosen as a new approach in order to decrease the production cost by reducing the amount of energy needed during fabrication. Therefore, this approach is called “Low Thermal Budget” process. After ion implantation the silicon surface is strongly disordered or amorphous up to the depth of the projected ion range. Therefore, subsequent annealing is required to remove the implantation damage and activate the doping element. Flash lamp annealing in the millisecond-range is demonstrated here as a very promising technique for the emitter formation at an overall low thermal budget. During flash lamp annealing, only the wafer surface is heated homogeneously to high temperatures at a time scales of ms. Thereby, implantation damages are annealed and phosphorous is electrically activated. The variation of pulse time allows to modify the degree of annealing of the bulk region to some extent as well. This can have an influence on the gettering behavior of metallic impurities. Ion implantation doping got in distinct consideration for doping of single-crystalline solar cells very recently. The efficient doping of multi-crystalline silicon remains the main challenge to reduce costs. The influence of different annealing techniques on the optical and electrical properties of multi-crystalline silicon solar cells was investigated. The Raman spectroscopy showed that the silicon surface is amorphous after ion implantation. It could be demonstrated that flash lamp annealing at 1000 °C for 3 ms even without preheating is sufficient to recrystallize implanted silicon. The sheet resistance of flash lamp annealed samples is in the range of about 60 Ω/□. Without surface passivation the minority carrier diffusion length in the flash lamp annealed samples is in the range of 85 µm. This is up to one order of magnitude higher than that observed for rapid thermal or furnace annealed samples. The highest carrier concentration and efficiency as well as the lowest resistivity were obtained after annealing at 1200 °C for 20 ms for both, single- and multi-crystalline silicon wafers. Photoluminescence results point towards phosphorous cluster formation at high annealing temperatures which affects metal impurity gettering within the emitter. Additionally, in silicon based solar cells, hydrogen plays a fundamental role due to its excellent passivation properties. The optical and electrical properties of the fabricated emitters were studied with particular interest in their dependence on the hydrogen content present in the samples. The influence of different flash lamp annealing parameters and a comparison with traditional thermal treatments such as rapid thermal and furnace annealing are presented. The samples treated by flash lamp annealing at 1200 °C for 20 ms in forming gas show sheet resistance values in the order of 60 Ω/□, and minority carrier diffusion lengths in the range of ~200 µm without the use of a capping layer for surface passivation. These results are significantly better than those obtained from rapid thermal or furnace annealed samples. The simultaneous implantation of hydrogen during the doping process, combined with optimal flash lamp annealing parameters, gave promising results for the application of this technology in replacing the conventional phosphoroxychlorid deposition and diffusion.

Afin de poursuivre la miniaturisation des dispositifs CMOS, l'empilement HfO2/Métal a remplacé l'empilement SiO2/polySi. Cependant, la diffusion incontrôlée des espèces chimiques dans ces nouveaux empilements fabriqués avec un fort budget thermique compromet l'obtention des travaux de sortie (EWF) et des épaisseurs d'oxyde équivalent (EOT) définis par l'ITRS. Une solution consiste à utiliser une intégration à plus bas budget thermique. Avec cette nouvelle approche, l'objectif de ce travail de thèse était de comprendre les paramètres physiques permettant d'obtenir une EOT<1nm et des EWF permettant une co-intégration nMOS et pMOS pour des nœuds futurs CMOS 20-14 nm. En nous appuyant sur différents méthodes d'analyse physico-chimique (STEM EDX, TOF-SIMS et XPS), la distribution spatiale des éléments et leurs liaisons chimiques au sein d'empilements de taille nanométrique ont été discutées et, sur la base de considérations thermodynamiques, corrélées aux valeurs mesurées de l'EOT et EWF. Nous avons démontré pour la première fois un écart de ~0. 8eV entre une électrode TiAlNx déficitaire et riche en azote, déposée sur HfO2. Ces résultats ont été obtenus après avoir identifié les mécanismes qui contrôlent l'EWF et l'EOT dans des empilements plus simples TiN/Ti, Al et TiAl. Les grilles HfO2/TiAlNx ne sont cependant pas stables thermiquement. Nous avons alors proposé deux systèmes métalliques plus simples et plus stables utilisant des alliages TaNix et NiTix obtenus par interdiffusion dans les empilements HfO2/Ta/Ni et de HfO2/Ni/Ti. Ces structures de grilles à base de Ni apparaissent prometteuses pour une co-intégration CMOS à bas budget thermique
To continue CMOS scaling, the HfO2/metal gate stack replaced the historical SiO2/PolySi gate stack. But the uncontrolled interdiffusion and reactivities of the new gate materials integrated with the classical high thermal budget approach appear to be a roadblock to reach the effective work function (EWF) and equivalent oxide thickness (EOT) ITRS targets. One solution consisted in implementing an approach with a lower thermal budget. Using this new approach, the aim of this thesis work was to understand the physical mechanisms, which enable to reach an EOT<1nm and an EWF relevant for nMOS and pMOS co-integration as required for the next 20-14nm CMOS nodes. Using spatially resolved TEM/EDX analyses and macroscopic TOF-SIMS and XPS techniques, elemental distributions and chemical bonds across nanometric-sized stacks were discussed and, based on thermodynamic considerations, correlated with the measured EWF and EOT. We showed for the first time that the modulation of nitrogen during TiAlN deposition on HfO2 results in a ~0. 8eV EWF shift between the N-poor and N-rich HfO2/TiAlNx electrodes. The TiAlN complex system was understood after the identification of the EWF and EOT modulation mechanisms in the simple gate stacks TiN/Ti, Al or TiAl. Although TiAlNx electrodes define the best compromise for a variable EWF with a sub-nm EOT, it exhibits a low thermal stability. Therefore, we investigated two simpler metallic and stable systems using TaNix and NiTix alloys resulting from thermally assisted Ni-Ta and Ni-Ti interdiffusion in HfO2/Ta/Ni and HfO2/Ni/Ti stacks, respectively. These Ni-based electrodes are shown to be promising for a low thermal budget CMOS co-integration

The integration of III-V devices on Si substrates would allow the fabrication of specialized devices for optoelectronics and photonics directly on the highly refined silicon infrastructure, based on CMOS technology. In this work of thesis, Droplet Epitaxy technique is used for the low thermal budget fabrication of GaAs quantum nanostructures on silicon substrates through a Ge layer and for the fabrication of GaAs local artificial substrates directly on Si substrate. Quantum nanostructures grown on Si substrate through a Ge layer showed an intense photoluminescence emission, detectable up to room temperature and with a ratio between number of photon emitted and photogenerated carriers similar to the one obtained for GaAs quantum nanostructures grown by droplet epitaxy on GaAs substrate. GaAs local artificial substrates fabricated on Si showed high tunability in size and density, a size dispersion below 10%, a good crystalline quality and well defined shapes with a high aspect ratio.

碩士
國立交通大學
電子研究所
83
In this thesis,we successfully utilize the rapid thermal O2, N2, and N2O annealing technology to improve the quality of the ultra-low temperature (-20?C) electron cyclotron resonance (ECR) thin oxide. Among the three kinds of annealing technology, the N2O annealed oxide is found to have the better electrical characteristics due to the Si-N bonds in place of the weaker bonds at the Si/SiO2 interface. The breakdwon field( over 12.5 MV/cm), Dit (1.95e10cm-2eV-1) and leakage current are comparable to the furnace oxide. The material analyses, including the Fourier transform infrared spectrum analysis (FTIR), etch rate test, assure that the low thermal budget annealing indeed greatly improves the oxide quality. The relationship between the oxide thickness and growth time is well described by the Deal-Grove model. By way of the rapid thermal 40~O oxide, the characteristics of the ultra-thin oxide, such as the stress induced leakage current (SILC), quasi- breakdown phenomenon, the polarity dependence of the Qbd have been studied.

碩士
國立臺灣科技大學
電子工程系
87
The scaling of CMOS devices to satisfy deep submicrometer technology requirements involves several process adjustments . One of the main challenges is the formation of shallow junction . Low-energy ion implantation , in tandem with low-thermal budget annealing processes , allows us to form shallower junctions . To adopt a low thermal budget scheme , we employed long-time low-temperature furnace annealing and rapid thermal annealing（RTA）as an approach of activating the implanted dopants without significant diffusion and eliminating the implanted-induced defects . Moreover , various low thermal budget schemes have been performed to form shallow junctions . The first scheme is the low temperature furnace annealing . The second scheme is the low temperature furnace annealing followed by RTA . The third scheme is the RTA followed by low temperature furnace annealing . The fourth scheme is the low temperature furnace annealing followed by high temperature furnace annealing . In this thesis , the dopant activation and the electrical characteristics of junctions have also been investigated .

Higher conversion efficiencies while reducing costs at the same time is the ultimate goal driving the development of solar cells. Multi-crystalline silicon has attracted considerable attention because of its high stability against light soaking. In case of solar grade multi-crystalline silicon the rigorous control of metal impurities is desirable for solar cell fabrication. It is the aim of this thesis to develop a new manufacturing process optimized for solar-grade multi-crystalline silicon solar cells. In this work the goal is to form solar cell emitters in silicon substrates by plasma immersion ion implantation of phosphine and posterior millisecond-range flash lamp annealing. These techniques were chosen as a new approach in order to decrease the production cost by reducing the amount of energy needed during fabrication. Therefore, this approach is called “Low Thermal Budget” process. After ion implantation the silicon surface is strongly disordered or amorphous up to the depth of the projected ion range. Therefore, subsequent annealing is required to remove the implantation damage and activate the doping element. Flash lamp annealing in the millisecond-range is demonstrated here as a very promising technique for the emitter formation at an overall low thermal budget. During flash lamp annealing, only the wafer surface is heated homogeneously to high temperatures at a time scales of ms. Thereby, implantation damages are annealed and phosphorous is electrically activated. The variation of pulse time allows to modify the degree of annealing of the bulk region to some extent as well. This can have an influence on the gettering behavior of metallic impurities. Ion implantation doping got in distinct consideration for doping of single-crystalline solar cells very recently. The efficient doping of multi-crystalline silicon remains the main challenge to reduce costs. The influence of different annealing techniques on the optical and electrical properties of multi-crystalline silicon solar cells was investigated. The Raman spectroscopy showed that the silicon surface is amorphous after ion implantation. It could be demonstrated that flash lamp annealing at 1000 °C for 3 ms even without preheating is sufficient to recrystallize implanted silicon. The sheet resistance of flash lamp annealed samples is in the range of about 60 Ω/□. Without surface passivation the minority carrier diffusion length in the flash lamp annealed samples is in the range of 85 µm. This is up to one order of magnitude higher than that observed for rapid thermal or furnace annealed samples. The highest carrier concentration and efficiency as well as the lowest resistivity were obtained after annealing at 1200 °C for 20 ms for both, single- and multi-crystalline silicon wafers. Photoluminescence results point towards phosphorous cluster formation at high annealing temperatures which affects metal impurity gettering within the emitter. Additionally, in silicon based solar cells, hydrogen plays a fundamental role due to its excellent passivation properties. The optical and electrical properties of the fabricated emitters were studied with particular interest in their dependence on the hydrogen content present in the samples. The influence of different flash lamp annealing parameters and a comparison with traditional thermal treatments such as rapid thermal and furnace annealing are presented. The samples treated by flash lamp annealing at 1200 °C for 20 ms in forming gas show sheet resistance values in the order of 60 Ω/□, and minority carrier diffusion lengths in the range of ~200 µm without the use of a capping layer for surface passivation. These results are significantly better than those obtained from rapid thermal or furnace annealed samples. The simultaneous implantation of hydrogen during the doping process, combined with optimal flash lamp annealing parameters, gave promising results for the application of this technology in replacing the conventional phosphoroxychlorid deposition and diffusion.:1 Motivation and objectives 1 2 Progress and prospects of silicon solar cells 5 3 Basics of a silicon solar cell 8 3.1 Specific characteristic of a standard silicon solar cell 12 3.2 Fundamental efficiency limits of standard silicon solar cells 14 4 Industrial process featuring low thermal budget process 17 4.1 Cleaning and etching steps 19 4.2 Emitter formation in p-type silicon 20 4.2.1 Thermal diffusion of phosphorous (industrial) 22 4.2.2 Ion beam implantation 24 4.2.3 Plasma immersion ion implantation as potential tool for the LTB process 26 4.2.4 Thermal processing of ion implanted solar cells - FLA as a novel method 28 4.3 Contact formation 30 4.3.1 Screen printing and sintering (industrial) 30 4.3.2 Gettering and BSF formation by aluminum diffusion (industrial) 32 4.3.3 Sputtering (LTB) 33 4.4 Surface passivation 33 5 Fabrication and characterization 35 5.1 Fabrication 35 5.2 Characterization of the p-n junction by ion implantation and FLA 39 5.2.1 Four-Point-Probe measurement (4-PPM) 39 5.2.2 Raman Spectroscopy (RS) 40 5.2.3 Photoluminescence Spectroscopy (PL) 41 5.2.4 Surface Photo-Voltage (SPV) 41 5.3 Analysis of hydrogen and metal impurities 46 5.3.1 Secondary Ion Mass Spectrometry (SIMS) 46 5.3.2 Elastic Recoil Detection Analyses (ERDA) and 47 Rutherford Backscattering Spectrometry (RBS) 47 5.4 Solar cell characterization 49 5.4.1 Transmission Electron Microscopy (TEM) 49 5.4.2 Auger Electron Spectroscopy (AES) 50 5.4.3 Light Beam Induced Current (LBIC) 51 5.4.4 Sun Simulator 52 6 Solar cell performance 53 6.1 Processing of the p-n junction by IBI and FLA 54 6.1.1 Variation FLA parameters 54 6.1.2 Influence of the grain size on the LD 71 6.2 Influence of the hydrogen introduced by PIII 76 6.2.1 Hydrogen profile by SIMS 76 6.2.2 H content as function of the thermal treatments 78 6.2.3 Optical properties of the silicon substrate 80 6.3 Influence of PIII and FLA on implanted iron 82 6.4 Contact formation 88 6.4.1 Antireflection layer 89 6.4.2 Back surface formation 90 6.4.3 Electrical and optical characterization 93 7 Overview of the achieved results 98 I References VIII II Publications XVII III Symbols index XVIII IV Acronyms XXI

博士
國立交通大學
光電工程研究所
101
Recently, transparent metal oxide semiconductor attracts great attention due to the characteristics of high mobility, high transparency, room temperature deposited, and high process compatibility with present solid-state semiconductor technologies. Among several novel oxide semiconductors, amorphous InGaZnO (a-IGZO) thin film received considerable attention for their use in next-generation active matrix liquid crystal display (AMLCD) and active-matrix organic light-emitting diode display (AMOLED) technologies. The sputter-deposited a-IGZO active layer typically requires thermal annealing at around 300℃ for 30 min or longer to achieve a satisfactory device performance and stability. In this study, we presents a novel microwave annealing process for a-IGZO TFT fabrication with low thermal budget process. Microwave heating process can transfer the energy directly to the target materials by absorption of microwave energy throughout the volume of the material. Among its advantages include low thermal budget, rapid heating process, thermal uniformity, suppression of unexpected species diffusion, and selective heating of materials, which is impossible with the typical furnace annealing process, microwave annealing is highly promising for a-IGZO TFT manufacturing. The performance of a-IGZO TFTs with microwave annealing are well competitive with its counterpart with furnace annealing at 450℃ for 1 hour with a carrier mobility of 13.5 cm2/Vs, threshold voltage of 3.28 V, and subthreshold swing of 0.43 V/decade. Although a-IGZO TFTs performed good electrical performance, containing the rare-dispersive elements will increase the cost and be a critical issue for the long-term applications. Therefore, rare elements-free transparent metal oxide semiconductors are considered to be the promising candidates for the next generation display technologies. In this work, we developed a novel rare elements-free oxide semiconductor, amorphous AlZnSnO (a-AZTO), TFT technologies. The band-gap of a-AZTO is larger than 3.6 eV, therefore it shows high transparency in visible light region. We have investigated the effects of SnO2 content on performance of a-AZTO TFTs. Moreover, we employed the plasma treatment to enhance the electrical reliability of a-AZTO TFTs. The experiment results showed that the O2 and N2O plasma could effectively oxidize Sn in back channel of a-AZTO thin film and improve the reliability and stability of a-AZTO TFTs. Furthermore, we decreased the fabrication temperature from 450°C to 350°C by H2 plasma process and remained great performance of a-AZTO TFTs. In the end of this study, a supercritical fluid (SCF) technology is proposed at 150°C to enhance the electrical performance and reliability of a-AZTO TFTs. The SCF provides good liquid-like solvency and high gas-like diffusivity, giving it excellent transport capacity to take the H2O molecules into metal oxide films and terminate the traps in metal oxide films by the oxidization reaction.

博士
國立中央大學
機械工程學系
103
Wafer bonding is the core technology for semiconductor industry and related micro/nano devices. It has made significant innovation in recent years for its widely applications, such as silicon on insulator、high performance microelectronics、micro-electromechanical systems、3D IC and optoelectronics, etc. Today, as energy saving and carbon reduction is continuing to evolve, wafer bonding technology is needed to innovate for the green earth. Different bonding materials do not present difficulty for wafer bonding, but thermal mismatch imposes a severe limitation on the annealing temperature. The innovation needs of wafer bonding are high bonding strength、cost effective and energy saving. The aim of this study is to design a systematic evaluation index for wafer bonding technology based on thermal budget theory, and develop low temperature & high strength wafer bonding technology. The evaluation index include thermal budget ratio, energy efficiency and eco efficiency. The study also proposed an innovative wafer bonding technology, it was named “Green Wafer Bonding”, by hybrid HF-Dip and Nitrogen Plasma Activation methods. By the experiments, it can be proved green wafer bonding can provide high strength bonding in low temperature: Si/Si (2500mJ/cm2, 75oC) and Si3N4/Si3N4 (2500mJ/cm2, 200oC). By the evaluation, it showed Si/Si (RCA-HF-N2 Plasma) has the lowest thermal budget and energy efficiency is 51.6% and Si3N4/Si3N4 (RCA-HF-N2 Plasma) needs double thermal budget and energy efficiency is 28.6%. GWB technology has the best bonding quality and the highest enegy saving performace than the conventional bondig technologies. By the patent analysis, it showed the main application of wafer bonding are including MEMS, SOI and optoelectronics, etc. The study also applied GWB (Green Wafer Bonding) technology in smart-cut process and produced a nano-scaled Si film successfully. Green Wafer Bonding has many advantages, such as high bonding strength, low temperature, saving time and cost. The research can be applied for developing the energy saving semiconductor industry and new technologies, such as thermal-electricity converter, hydrogen storage and thin film solar cell, etc.

碩士
國立交通大學
光電工程研究所
103
In this thesis, the amorphous SiGe thin film is deposited by ICPCVD at low temperature of 450oC, the SiGe thin film is then crystallized by visible laser crystallization (λ=532 nm). The grain size of as-crystallized poly-SiGe thin films range from 500 nm to 600 nm. It is found that germanium segregation is observed after laser crystallization. It causes germanium-rich region on surface of the thin film. Thus, Chemical Mechanical Polishing (CMP) is used to polish high germanium concentration region and smoothen the surface to obtain thin and flat ploy SiGe film with uniform germanium concentration distribution. Moreover, far infrared ray laser annealing (FIR-LA) can decrease sheet resistance. Laser energy is absorbed in implantation induced defect region and transfer to phonon vibration, which is equal to thermal activation effectively. . In this study, the sheet resistance of polycrystalline SiGe film can be decreased to 290 Ohm/sq. (P-type) and 350 Ohm/sq. (N-type) by far infrared ray laser annealing with less dopants diffusion due to the short time dwell time. Therefore, FIR-LA is also suitable for realizing nano-scaled devices. The combination of visible laser crystallized SiGe film and far-infrared ray laser activation demonstrated the high performance of poly SiGe metal-oxide-silicon field effect transistor (MOSFET), which exhibited high on current of 51.3 uA/um, low subthreshold swing (S.S.) of 181 mV/dec. and threshold voltage (Vth) of -1.05 V in P-type FET. The N-type device exhibited Ion of 20.1 uA/um, S.S. of 240 mV/dec, and Vth of 0.95 V. The process and related performance is of great potential for nano-scaled TFTs and monolithic 3DICs applications.

博士
國立交通大學
材料科學與工程學系所
104
The demand for system on panel (SoP) and monolithic 3D integration is increasing for realizing devices with high density and operation speed and low power consumption to fabricate future chip integration. However, the conventional high thermal processes constrain this realization; thus developing low thermal budget processes is essential. In this thesis, we investigated the material characteristics of low thermal budget amorphous Si (a-Si) thin-film for fabrication of low thermal budget photovoltaics and field effect transistors. Furthermore, we developed and integrated low thermal budget processes, such as light-trapping structures, plasma-deposited thin film, laser crystallization, and laser activation, to fabricate hydrogenated a-Si (a-Si:H) thin-film solar cells, poly-Si field-effect transistors (FETs), and charge-trap non-volatile memories (CTNVMs). For low thermal budget thin-film solar cells, highly efficient n-i-p and p-i-n a-Si:H thin-film solar cells were fabricated through inductively coupled plasma chemical vapor deposition at 140-200oC. The light-trapping capability of the n-i-p solar cells increased in the ultraviolet (UV)-visible region and a conversion efficiency of 8.5% was achieved, when the cells were incorporated with sub-micron (0.4 μm in diameter) self-assembly loosely-packed silica spheres (LPSS) monolayers (65% fill density). The LPSS monolayer behaves like a nearly omnidirectional antireflector and increases the solar efficiency at high incident angle of illumination. Incorporating the FTO/Au-NPs/AZO electrode in p-i-n thin-film solar cells imparted the light-trapping capability in the green-red band because of the plasmonic effect and resistance to photodegradation in the UV-blue band, which was due to the low defect of the p-/i-layer interface and intrinsic layer. This phenomenon substantially increased the conversion efficiency to 10.1% and reduced the photodegradation to 7%. For low thermal budget field effect transistor and non-volatile memories, green nanosecond laser spike annealing was used to transform a-Si to poly-Si, the thickness of which was reduced to 14 nm. Low temperature n- and p-FETs were fabricated by integrating a thin poly-Si channel, high-κ/metal gate (Al2O3/TiN) and far-infrared laser activation to obtain a high on-current (121 and 62 A/m, respectively), low subthreshold swing (88 and 121 mV/dec., respectively), and low threshold voltage (0.7 and 0.3 V, respectively). In addition, a metal/SiO2/Si-rich SiNx/AlOxNy/SiO2/Si CTNVM with a low thermal budget was implemented by combining low thermal budget field effect transistor with nano-scale to obtain a low operation voltage, low charge loss, and reliable endurance. These low thermal budget materials, processes and devices can be widely used in SoP, 3D integration, and Internet of Things.

碩士
國立交通大學
電子研究所
100
Silicon carbide (SiC) is suitable for fabricating high power semiconductor devices because of its wide band-gap and high thermal conductivity. Unfortunately, low channel mobility occurs on the 4H-SiC MOSFETs due to the high SiO2/SiC interface state density. How to reduce interface state density is an important issue. In this thesis, several low thermal budget processes to reduce interface state density are evaluated. Electrical parameters including interface state density and breakdown field distribution are analyzed. The effect of process conditions on interface state density is also discussed. The low temperature (1050 ℃) wet oxidation sample set provides the higher bound reference of the interface state density (Dit) in this thesis. It is expected that the shorter oxidation time would result in lower interface state density. However, it is observed that lots of carbon clusters saturate on the 0.5 hr wet oxidation sample. It is suspected that the oxidation temperature is not high enough for the diffusion of CO. The interface state density of the wet oxidation sample set is around 5x1011 cm-2eV-1 at Ec-E = 0.4 eV. High temperature (1300 ℃) N2O oxidation sample sets the lower bound reference of Dit. The Dit value of this sample is 4.67x1010 cm-2eV-1 and is 10 times lower than that of the wet oxidation samples. Low temperature (1100 ℃) post-oxidation annealing, with the N2O annealing or NH3 annealing, can improve the interface quality separately. The N2O annealing and NH3 annealing have superimposed effect the Dit can be improved to 2.92 x1011 cm-2eV-1 at Ec-E = 0.4 eV. N2O annealing can improve breakdown field but the breakdown field variation is still large. These results indicate that N2O annealing can improved oxide quality but the early breakdown due to the rough SiC surface cannot be changed. Samples with Si3N4 capping have tight breakdown field distribution because weak spots in the wet oxide do not coincide with the weak spot in the nitride layer so that early breakdown could be suppressed because current path is hard to form. NH3 plasma treatment can improve Dit effectively but a 0.5~1 V positive shift of flat-band voltage compared to wet oxidation sample is observed on all of the plasma treated samples. The trends of interface improvement by plasma treatment at 150 W and 200 W are similar. The interface state density decreases as the plasma treatment time increases from 2 minutes to 5 minutes and gradually saturates as the plasma treatment time increases to 10 minutes. At the same plasma treatment time, 200 W results in slightly higher interface state density than 150 W. It is suspected that higher plasma energy produces additional interface defects due to the stronger radiation. The 100 W 15 min sample has higher Dit than 150 W 10 min. It is thus concluded that 150 W 10 minutes is the optimized condition. Lower energy cannot passivate interface states effectively even if 15 min treatment. Dielectric stacks sample has the lowest thermal budget. However, it has the highest interface state density among all samples. Post-deposition annealing is required. Dielectric stacks sample exhibits wide breakdown field variation. It is suspected that the quality of the bottom PECVD oxide is too poor. Finally, to extract deep level interface states, high temperature measurement would be required. It is observed that the Dit improvement occurs only in the range of Ec-E = 0.2-0.8 eV. As Ec-E > 1 eV, there is no Dit improvement on all the samples. Secondary ion mass spectroscopic analysis shows nitrogen pile-up at the SiO2/SiC interface on the sample HT. This phenomenon is not observed on the other samples. It is suspected that the diffusion of nitrogen radicals in SiO2 is slow. If nitrogen incorporation is processed after SiO2 growth, there are not sufficient nitrogen radicals can reach the interface at low thermal budget processes. Although suitable NH3 plasma treatment achieves the lowest interface state density among these low thermal budget samples, Dit = 1.37x1011 cm-2eV-1, this value is still 3 times higher than the lowest bound reference. Furthermore, the thermal budget of the plasma treatment is too low. Only hydrogen can passivate the interface states. It is suspected that hydrogen can only passivate shallow level interface states and does not affect the interface states deeper than 0.5 eV. To achieve very low interface state density, novel low thermal budget processes must be developed. Otherwise high thermal budget process is still unavoidable.

碩士
國立交通大學
電子工程系
91
Since high temperature post-annealing for ferroelectric materials was usually required to get the fine crystallinity and ferroelectric characteristics. But many trouble issues was induced by the high thermal budget, such as the inter-diffusion of ferroelectric and substrate, and the deformation of junction profile etc. Therefore it is essential for the reduction of post-annealing temperature in order to make the ferroelectric material compatible the Si-base fabrication process. In this these, low temperature and low thermal budget for fabrication and post-annealing methods are introduced in this thesis. The (Pb,Sr)TiO3 (PST) ferroelectric material with low crystallization temperature was deposited onto the Pt/Ti/Ox/Si substrate for the research of capacitor type 1T-FeRAM. The PST thin film was fabricated by pulse-laser-deposition (PLD) method at low substrate temperature 200oC. At first, the results of conventional post annealing methods (Rapid Thermal Annealing (RTA), Furnace Annealing (FA) were acquired, witch surface cracks and interface lift were found by lager thermal stress. Therefore, novel post-treatment for Excimer Laser Annealing (ELA) method was introduced to suppress the above troubles. The PST thin films were irradiated with conditions of different laser energy density and shot number at low substrate temperature 300oC. The improvement of ferroelectric characteristic was apparently observed from electrical measurement and physical analysis, and it is further inferred that the crystallization phenomenon was occurred only on the surface region. The better improvement for crystallinity was found by appropriate control of laser energy density and shot number. Besides the larger improvement on crystallinity and characteristic of whole thin film were obtained with the combination of ELA and RTA post-treatment. The fine reliability properties for PST thin film with treatment of combination of ELA and RTA method were acquired after Fatigue, Imprint, and TDDB tests. Finally, the better crystallization and ferroelectric characteristic of the whole PST thin film treatments had been successfully achieved under low temperature post-treatment, and it is excellent for the most promising candidate in capacitor type 1T-FeRAM applications.

碩士
國立清華大學
電子工程研究所
104
In this thesis, we propose low thermal budget laser technologies to fabricate high-performance 3D stackable poly-Si FET, including green nanosecond laser used to produce high-quality poly-Si channel, far infrared ray laser used to anneal source / drain regions after ion implantation and form the metal silicide layer on the source / drain, thereby improves the device performance. Green nanosecond laser is employed to transform the channel layer of the device from a-Si to poly-Si thin film. After chemical mechanical polishing (CMP) process, the average grain size is larger than 700nm, and the mean surface roughness can be lowered efficiently; moreover, the nc-Si on the surface can be polished. Far infrared ray (FIR) laser is utilized to anneal the source / drain regions. Silicon films with various doping species are activated by FIR laser after the substrate temperature is raised to 400oC, and the sheet resistances of sub-100Ω/□ for both B/P-doped Si and 100~200Ω/□ for As-doped Si can be realized. It significantly outperforms rapid thermal anneal (RTA) process and obsesses lower thermal budget. In addition, the dopant profiles of boron and phosphorus observed by SIMS analysis are less diffused than the data prepared by RTA process. Finally, we produce NiSi layer by two-step annealing processes, involving RTA (250oC, 30s) for the first step and FIR laser at low temperature for the second step. After that, NiSi layer which has low resistivity is formed on the surface and is used to lower the contact resistance. Silicide made from these ways has lower thermal budget and it can obtain equivalent resistance in comparison with two-step RTA processes. We integrate the technologies mentioned above to the poly-Si FET, and the highest drive current can be reached to 285A/m for n-type and 111A/m for p-type respectively. The effect of different device sizes on the electrical characteristics will also be discussed in this thesis. The poly-Si FET fabricated from these methods not only has better electrical properties but also has lower thermal budget, thus it is beneficial to develop 3D sequential layered devices.

博士
國立交通大學
電子研究所
107
Hybrid bonding technology is one of the key technologies of 3D integrated circuits (3D IC). It has high material selectivity and high semiconductor process compatibility, enabling heterogeneous integration and achieving of lower power, smaller size and more functional products. Therefore, this technology is highly valued in both industry and academia, and is currently moving toward low thermal budget and fine pitch requirements. In hybrid bonding techniques, the polymer and metal need to be bonded during the bonding process, respectively. Conventional polyimides are less used in bonding technology due to their high curing temperature and high thermal budget. This thesis proposes a low curing temperature polyimide that can be combined with Cu/Sn eutectic bonding to achieve asymmetric wafer-level hybrid bonding at 250°C. The asymmetric structure can not only effectively optimize the processing of metals and polymers, but also achieve ultra-thin film bonding. In addition, the ratio of polymer-to-solder thickness was designed to study the applicability of the process. At different thickness ratios, the specific contact resistance value maintained at 10-7~10-8 Ω-cm2, and the thermal cycling tests and humidity reliability tests showed good electrical performance. Therefore, this asymmetric hybrid bonding structure has great potential for future 3D integration technologies. In addition to the hybrid bonding structure and its electrical properties, the compatibility of polyimide materials with semiconductor fabrication process and the adhesion strength of between the materials were investigated. Since the polyimide layer is deposited on the passivation layer in the redistribution layer (RDL), the adhesion strength and thermal reliability between the polyimide layer and the passivation layer are very important. Moreover, the Ti/Cu metal wires were deposited on the polyimide layer. Therefore, the adhesion strength between polyimide layer and Ti/Cu layer after certain electroplating process were also evaluated by the four-point bending system. By using scanning electron microscope and X-ray photoelectron spectroscopy, the bonding mechanism and behavior were observed and analyzed.