Bibliographies thématiques / LOW POWER PERFORMANCE

Littérature scientifique sur le sujet « LOW POWER PERFORMANCE »

Auteur : Grafiati
Publié le 11 septembre 2023

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Articles de revues sur le sujet "LOW POWER PERFORMANCE"

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Cao, Qiang, Jiang Jiang, Chang Wang et Yongxin Zhu. « FPGA Implementation of High Performance and Low Power VOD Server ». International Journal of Future Computer and Communication 3, no 3 (2014) : 148–52. http://dx.doi.org/10.7763/ijfcc.2014.v3.286.

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Wu, A., et C. K. Ng. « High performance low power low voltage adder ». Electronics Letters 33, no 8 (1997) : 681. http://dx.doi.org/10.1049/el:19970464.

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Han, Wei, Ahmet T. Erdogan, Tughrul Arslan et Mohd Hasan Hasan. « High-Performance Low-Power FFT Cores ». ETRI Journal 30, no 3 (9 juin 2008) : 451–60. http://dx.doi.org/10.4218/etrij.08.0107.0189.

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Deininger, W. D., G. Cruciani et M. J. Glogowski. « Performance comparisons of low-power arcjets ». Journal of Propulsion and Power 11, no 6 (novembre 1995) : 1368–71. http://dx.doi.org/10.2514/3.23982.

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Xu, Ning, Zhoughua Jiang et Feng Huang. « Performance and Low Power Driven Floorplanning ». Journal of Algorithms & ; Computational Technology 1, no 2 (juin 2007) : 161–69. http://dx.doi.org/10.1260/174830107781389058.

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Yoshikawa, Masaya, et Hidekazu Terai. « Performance Driven Placement Procedure for Low Power ». IEEJ Transactions on Electronics, Information and Systems 124, no 1 (2004) : 18–25. http://dx.doi.org/10.1541/ieejeiss.124.18.

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Andrew, R., et K. Venos. « Multiphase synchronous circuits for low power performance ». Microelectronics Journal 29, no 3 (mars 1998) : 105–11. http://dx.doi.org/10.1016/s0026-2692(97)00034-7.

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Yoshikawa, Masaya, et Hidekazu Terai. « Performance-driven placement procedure for low power ». Electrical Engineering in Japan 151, no 1 (2005) : 56–65. http://dx.doi.org/10.1002/eej.20057.

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Vallem, Dr Sharmila, G. Tejaswi, Hrithik Sidharth et Shilpa Reddy. « High Performance, Low Power Wallace Tree Multiplier ». International Journal of Recent Technology and Engineering (IJRTE) 12, no 2 (30 juillet 2023) : 20–25. http://dx.doi.org/10.35940/ijrte.b7685.0712223.

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An area-efficient high Wallace tree multiplier using adders is presented in this paper. The proposed Wallace tree multiplier is designed using logic gates and adders. The design is implemented in Cadence Virtuoso using a 45-nm technology library. The proposed design offers reduced delay and higher performance than conventional multipliers using carry-save adders with majority-based gate adder logic. The design also offers a reduced transistor count of 12, which is minimal compared to that of the conventional design. One of the fundamental building blocks of many VLSI applications is multipliers. To enhance the performance of circuits and systems, the design of multipliers is very important. The key feature of a high-performance Wallace tree multiplier lies in its efficient reduction of partial product additions. By utilising a combination of carry-save and carry-propagate adders, it minimises the critical path delay and maximises the speed of multiplication. Additionally, advanced optimisation techniques such as parallel prefix adders and parallel carry-save adders can be employed to further improve performance.
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Asna, M., H. Shareef, S. N. Khalid, A. O. Idris, A. N. Aldarmaki et Basil Hamed. « Universal power converter for low power applications ». International Journal of Power Electronics and Drive Systems (IJPEDS) 10, no 4 (1 décembre 2019) : 2165. http://dx.doi.org/10.11591/ijpeds.v10.i4.pp2165-2172.

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A novel power converter that can perform both voltage and frequency conversion was proposed. Inappropriate power supply can damage sensitive sub-components and render the connected device inoperable. Henceforth, the proposed voltage–frequency converter acts as an interface to plug any electrical device directly into an electrical socket and provide the voltage and frequency required. The converter used a synchronous reference frame proportional–integral (SRFPI) controller to regulate the instantaneous output voltage and to improve steady state performance. Because the PI controller works together with the synchronous reference frame controller, it is difficult to tune the PI control parameters. To overcome this issue, a new meta heuristic optimization technique called lightening search algorithm (LSA) optimization was used to identify the optimum PI parameter values. A detailed description of the system operation and control strategy was presented. Finally, the performance of the converter was analyzed and verified by simulation and experimental results. The experimental result has shown that the proposed system has satisfactory output voltage and frequency under different input voltages.
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Thèses sur le sujet "LOW POWER PERFORMANCE"

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Zhu, Haikun. « High-performance low-power VLSI design ». Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2007. http://wwwlib.umi.com/cr/ucsd/fullcit?p3250072.

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Thesis (Ph. D.)--University of California, San Diego, 2007.
Title from first page of PDF file (viewed April 4, 2007). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 97-101).
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Lee, Sunghyuk. « Techniques for low-power high-performance ADCs ». Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/87928.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 127-133).
Analog-to-digital converters (ADCs) are essential building blocks in many electronic systems which require digital signal processing and storage of analog signals. Traditionally, ADCs are considered a power hungry circuit. This thesis investigates ADC design techniques to achieve high-performance with low power consumption. Two designs are demonstrated. The first design is a voltage scalable zero-crossing based pipelined ADC. The zero-crossing based circuit technique is modified and optimized to improve the limited ADC resolution in nano-scaled CMOS technology. The proposed unidirectional charge transfer scheme allows faster and more energy efficient operation by eliminating unnecessary charging and discharging of the capacitors. Furthermore, the reduced transient disturbance at the beginning of the fine charge transfer phase improves the accuracy of operation. Power supply scaling enhances power efficiency at low sampling rates much like in digital circuits and widens the conversion frequency range where the ADC operates with highest efficiency. The second design is a high speed time-interleaved (TI) SAR ADC with background timing-skew calibration. A time-interleaved structure is employed to improve the effective sampling rate without sacrificing energy efficiency. SAR ADCs are used for each channel to make good use of device scaling. The proposed ADC architecture incorporates a flash ADC operating at the full sampling rate of the TI ADC. The flash ADC output is multiplexed to resolve MSBs of the SAR channels. Because the full-speed flash ADC does not suffer from timing-skew errors, the flash ADC output is also used as the timing reference to estimate the timing-skew of the SAR ADCs.
by Sunghyuk Lee.
Ph. D.
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Bystrøm, Vebjørn. « Low power/high performance dynamic reconfigurable filter-design ». Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2008. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8899.

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The main idea behind this thesis was to optimize the multipliers in a finite impulse response (FIR) filter. The project was chosen because digital filters are very common in digital signal processing and is an exciting area to work with. The first part of the text describes some theory behind the digital filter and how to optimize the multipliers that are a part of digital filters. The substantial thing to emphasize here is the use of Canonical Signed Digits (CSD) encoding. CSD representation for FIR filters can reduce the delay and complexity of the hardware implementation. CSD-encoding reduces the amount of non-zero digits and will by this reduce the multiplication process to a few additions/subtractions and shifts. In this thesis it was designed 4 versions of the same filter, that was implemented on an FPGA, where the substantial and most interesting results were the differences between coefficients that was CSD-encoded and coefficients that was represented with 2's complement. It was shown that the filter version that had CSD-encoded coefficients used almost 20% less area then the filter version with 2's complement coefficients. The CSD-encoded filter could run on a maximum frequency of 504,032 MHz compared the other filter that could run on a maximum frequency of 249,123 MHz. One of the filters that was designed was designed using the * operator in VHDL, that proved to be the most efficient when it came to the use of number of slices and speed. The reason for this was because an FPGA has built-in multipliers, so if one has the opportunity to use the multiplier they will give the best result instead of using logic blocks on the FPGA It was also discussed a filter that has the ability to change the coefficients at run-time without starting the design from the beginning. This is an advantage because a constant coefficient multiplier requires the FPGA to be reconfigured and the whole design cycle to be re-implemented. The drawback with the dynamic multiplier is that is uses more hardware resources.

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Ma, Albert. « Circuits for high-performance low-power VLSI logic ». Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37906.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
Includes bibliographical references (p. 85-88).
The demands of future computing, as well as the challenges of nanometer-era VLSI design, require new digital logic techniques and styles that are simultaneously high performance, energy efficient, and robust to noise and variation. We propose a new family of logic styles called Preset Skewed Static Logic (PSSL). PSSL bridges the gap between the two main logic styles, static CMOS logic and domino logic, occupying an intermediate region in the energy-delay-robustness space between the two. PSSL is better than domino in terms of energy and robustness, and is better than static CMOS in terms of delay. PSSL works by partially overlapping the execution of consecutive iterations through speculative evaluation. This is accomplished by presetting nodes at register boundaries before input arrival.
by Albert Ma.
Ph.D.
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Zhang, Ling. « Low power high performance interconnect design and optimization ». Diss., [La Jolla] : University of California, San Diego, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p3368979.

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Thesis (Ph. D.)--University of California, San Diego, 2009.
Title from first page of PDF file (viewed September 17, 2009). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 113-118).
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NEUPANE, USHA. « PERFORMANCE ANALYSIS OF LOW-POWER, SHORT-RANGE WIRELESS TRANSCEIVERS ». Master's thesis, University of Central Florida, 2004. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4169.

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To address the various emerging standards like BluetoothTM, Home RF, Wi-fiTM (IEEE 802.11), ZigBeeTM etc., in the field of wireless communications, different transceivers have been designed to operate at various frequencies such as 450 MHz, 902-920 MHz, 2.4 GHz, all part of designated ISM band. Though, the wireless systems have become more reliable, compact and easy to develop than before, a detailed performance analysis and characterization of the devices should be done. This report details the performance analysis and characterization of a popular binary FSK transceiver TRF6901 from Texas Instruments. The performance analysis of the device is done with respect to the TRF/MSP430 demonstration and development kit.
M.S.E.E.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
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Yazdani, Aminabadi Reza. « Ultra low-power, high-performance accelerator for speech recognition ». Doctoral thesis, Universitat Politècnica de Catalunya, 2019. http://hdl.handle.net/10803/667429.

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Automatic Speech Recognition (ASR) is undoubtedly one of the most important and interesting applications in the cutting-edge era of Deep-learning deployment, especially in the mobile segment. Fast and accurate ASR comes at a high energy cost, requiring huge memory storage and computational power, which is not affordable for the tiny power budget of mobile devices. Hardware acceleration can reduce power consumption of ASR systems as well as reducing its memory pressure, while delivering high-performance. In this thesis, we present a customized accelerator for large-vocabulary, speaker-independent, continuous speech recognition. A state-of-the-art ASR system consists of two major components: acoustic-scoring using DNN and speech-graph decoding using Viterbi search. As the first step, we focus on the Viterbi search algorithm, that represents the main bottleneck in the ASR system. The accelerator includes some innovative techniques to improve the memory subsystem, which is the main bottleneck for performance and power, such as a prefetching scheme and a novel bandwidth saving technique tailored to the needs of ASR. Furthermore, as the speech graph is vast taking more than 1-Gigabyte memory space, we propose to change its representation by partitioning it into several sub-graphs and perform an on-the-fly composition during the Viterbi run-time. This approach together with some simple yet efficient compression techniques result in 31x memory footprint reduction, providing 155x real-time speedup and orders of magnitude power and energy saving compared to CPUs and GPUs. In the next step, we propose a novel hardware-based ASR system that effectively integrates a DNN accelerator for the pruned/quantized models with the Viterbi accelerator. We show that, when either pruning or quantizing the DNN model used for acoustic scoring, ASR accuracy is maintained but the execution time of the ASR system is increased by 33%. Although pruning and quantization improves the efficiency of the DNN, they result in a huge increase of activity in the Viterbi search since the output scores of the pruned model are less reliable. In order to avoid the aforementioned increase in Viterbi search workload, our system loosely selects the N-best hypotheses at every time step, exploring only the N most likely paths. Our final solution manages to efficiently combine both DNN and Viterbi accelerators using all their optimizations, delivering 222x real-time ASR with a small power budget of 1.26 Watt, small memory footprint of 41 MB, and a peak memory bandwidth of 381 MB/s, being amenable for low-power mobile platforms.
Los sistemas de reconocimiento automático del habla (ASR por sus siglas en inglés, Automatic Speech Recognition) son sin lugar a dudas una de las aplicaciones más relevantes en el área emergente de aprendizaje profundo (Deep Learning), specialmente en el segmento de los dispositivos móviles. Realizar el reconocimiento del habla de forma rápida y precisa tiene un elevado coste en energía, requiere de gran capacidad de memoria y de cómputo, lo cual no es deseable en sistemas móviles que tienen severas restricciones de consumo energético y disipación de potencia. El uso de arquitecturas específicas en forma de aceleradores hardware permite reducir el consumo energético de los sistemas de reconocimiento del habla, al tiempo que mejora el rendimiento y reduce la presión en el sistema de memoria. En esta tesis presentamos un acelerador específicamente diseñado para sistemas de reconocimiento del habla de gran vocabulario, independientes del orador y que funcionan en tiempo real. Un sistema de reconocimiento del habla estado del arte consiste principalmente en dos componentes: el modelo acústico basado en una red neuronal profunda (DNN, Deep Neural Network) y la búsqueda de Viterbi basada en un grafo que representa el lenguaje. Como primer objetivo nos centramos en la búsqueda de Viterbi, ya que representa el principal cuello de botella en los sistemas ASR. El acelerador para el algoritmo de Viterbi incluye técnicas innovadoras para mejorar el sistema de memoria, que es el mayor cuello de botella en rendimiento y energía, incluyendo técnicas de pre-búsqueda y una nueva técnica de ahorro de ancho de banda a memoria principal específicamente diseñada para sistemas ASR. Además, como el grafo que representa el lenguaje requiere de gran capacidad de almacenamiento en memoria (más de 1 GB), proponemos cambiar su representación y dividirlo en distintos grafos que se componen en tiempo de ejecución durante la búsqueda de Viterbi. De esta forma conseguimos reducir el almacenamiento en memoria principal en un factor de 31x, alcanzar un rendimiento 155 veces superior a tiempo real y reducir el consumo energético y la disipación de potencia en varios órdenes de magnitud comparado con las CPUs y las GPUs. En el siguiente paso, proponemos un novedoso sistema hardware para reconocimiento del habla que integra de forma efectiva un acelerador para DNNs podadas y cuantizadas con el acelerador de Viterbi. Nuestros resultados muestran que podar y/o cuantizar el DNN para el modelo acústico permite mantener la precisión pero causa un incremento en el tiempo de ejecución del sistema completo de hasta el 33%. Aunque podar/cuantizar mejora la eficiencia del DNN, éstas técnicas producen un gran incremento en la carga de trabajo de la búsqueda de Viterbi ya que las probabilidades calculadas por el DNN son menos fiables, es decir, se reduce la confianza en las predicciones del modelo acústico. Con el fin de evitar un incremento inaceptable en la carga de trabajo de la búsqueda de Viterbi, nuestro sistema restringe la búsqueda a las N hipótesis más probables en cada paso de la búsqueda. Nuestra solución permite combinar de forma efectiva un acelerador de DNNs con un acelerador de Viterbi incluyendo todas las optimizaciones de poda/cuantización. Nuestro resultados experimentales muestran que dicho sistema alcanza un rendimiento 222 veces superior a tiempo real con una disipación de potencia de 1.26 vatios, unos requisitos de memoria modestos de 41 MB y un uso de ancho de banda a memoria principal de, como máximo, 381 MB/s, ofreciendo una solución adecuada para dispositivos móviles.
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Oskuii, Saeeid Tahmasbi. « Comparative study on low-power high-performance flip-flops ». Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2077.

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This thesis explores the energy-delay space of eight widely referred flip-flops in a 0.13µm CMOS technology. The main goal has been to find the smallest set of flip-flop topologies to be included in a “high performance” flip-flop cell library covering a wide range of power-performance targets. Based on the comparison results, transmission gate-based flip-flops show the best powerperformance trade-offs with a total delay (clock-to-output + setup time) down to 105ps. For higher performance, the pulse-triggered flip-flops are the fastest (80ps) alternatives suitable to be included in a flip-flop cell library. However, pulse-triggered flip-flops consume significantly larger power (about 2.5x) compared to other fast but fully dynamic flip-flops such as TSPC and dynamic TG-based flip-flops.

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Mohan, Nitin. « Low-Power High-Performance Ternary Content Addressable Memory Circuits ». Thesis, University of Waterloo, 2006. http://hdl.handle.net/10012/2873.

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Ternary content addressable memories (TCAMs) are hardware-based parallel lookup tables with bit-level masking capability. They are attractive for applications such as packet forwarding and classification in network routers. Despite the attractive features of TCAMs, high power consumption is one of the most critical challenges faced by TCAM designers. This work proposes circuit techniques for reducing TCAM power consumption. The main contribution of this work is divided in two parts: (i) reduction in match line (ML) sensing energy, and (ii) static-power reduction techniques. The ML sensing energy is reduced by employing (i) positive-feedback ML sense amplifiers (MLSAs), (ii) low-capacitance comparison logic, and (iii) low-power ML-segmentation techniques. The positive-feedback MLSAs include both resistive and active feedback to reduce the ML sensing energy. A body-bias technique can further improve the feedback action at the expense of additional area and ML capacitance. The measurement results of the active-feedback MLSA show 50-56% reduction in ML sensing energy. The measurement results of the proposed low-capacitance comparison logic show 25% and 42% reductions in ML sensing energy and time, respectively, which can further be improved by careful layout. The low-power ML-segmentation techniques include dual ML TCAM and charge-shared ML. Simulation results of the dual ML TCAM that connects two sides of the comparison logic to two ML segments for sequential sensing show 43% power savings for a small (4%) trade-off in the search speed. The charge-shared ML scheme achieves power savings by partial recycling of the charge stored in the first ML segment. Chip measurement results show that the charge-shared ML scheme results in 11% and 9% reductions in ML sensing time and energy, respectively, which can be improved to 19-25% by using a digitally controlled charge sharing time-window and a slightly modified MLSA. The static power reduction is achieved by a dual-VDD technique and low-leakage TCAM cells. The dual-VDD technique trades-off the excess noise margin of MLSA for smaller cell leakage by applying a smaller VDD to TCAM cells and a larger VDD to the peripheral circuits. The low-leakage TCAM cells trade off the speed of READ and WRITE operations for smaller cell area and leakage. Finally, design and testing of a complete TCAM chip are presented, and compared with other published designs.
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Duewer, Bruce Eliot. « A Low-Power, High Performance MEMS-based Switch Fabric ». NCSU, 2001. http://www.lib.ncsu.edu/theses/available/etd-20011015-145122.

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DUEWER, BRUCE ELIOT. A Low-Power, High Performance MEMS-based Switch Fabric. (Under the direction of Paul D. Franzon.)An approach with the potential for building large low power high performance crossbar networks is presented. Thin film polysilicon MEMS devices are developed to provide crosspoints. These devices are vertically moving plates that serve as variable capacitors. Addressing of large arrays using 2n rather than n-squared lines despite no active circuitry on the MEMS chips is facilitated by bistable device operation. Derivations of equations for bistable device operation are presented. Low power operation is possible as the devices are electrostatically controlled and are stationary except during reconfiguration. Early devices are fabricated using the MUMPS process. The bistability and array addressability properties are demonstrated. The substrate effect on device operation is measured and modeled; methods for utilizing the substrate effect to tune device operation are presented. Later devices are fabricated using the SUMMiT process. Changes in the SUMMiT design rules to increase allowable vertical motion range are proposed and designs using them fabricated. S-parameter characteristics of devices in both `on' and `off' states are measured. Addition of metallization after chip fabrication and release is necessary to lower the resistance of interconnect. A self masking method for applying this metallization allowing for decreased resistance at line crossings is proposed. This method is tested using each of sputtering and evaporation as the deposition technique for a gold and adhesion layer stack. Effectiveness of the method with each technique is evaluated. Chips suitable for providing high voltage control for large MEMS arrays are fabricated in a 2um feature size CMOS process. Architectures suitable for building large crossbars employing variable capacitor arrays are discussed. Optimization of hybrid CMOS/MEMS Clos arrays on the basis of criteria other than minimization of crosspoints is discussed. Array sizings to provide 192*192 and 256*256 crossbars are presented, and software examples for sizing and controlling Clos networks are provided. Evaluation of the suitability of the MEMS devices developed for use as digital or broadband crosspoints is evaluated, and potential future directions are proposed.

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Livres sur le sujet "LOW POWER PERFORMANCE"

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J, Sarmiento Charles, et United States. National Aeronautics and Space Administration., dir. Low power arcjet performance. [Washington, DC] : National Aeronautics and Space Administration, 1990.

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Yoo, Hoi-Jun. Low-power NoC for high-performance SoC design. Boca Raton, Fl : Taylor & Francis, 2008.

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Korec, Jacek. Low voltage power MOSFETs : Design, performance and applications. New York : Springer, 2011.

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Yoo, Hoi-Jun. Low-Power NoC for High-Performance SoC Design. London : Taylor and Francis, 2008.

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G, Oklobdzija Vojin, dir. Digital system clocking : High-performance and low-power aspects. New York : IEEE, 2003.

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H, Berns Darren, et United States. National Aeronautics and Space Administration., dir. Performance of a low-power subsonic-arc-attachment arcjet thruster. [Washington, D.C.] : NASA, 1993.

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H, Berns Darren, et United States. National Aeronautics and Space Administration., dir. Performance of a low-power subsonic-arc-attachment arcjet thruster. [Washington, D.C.] : NASA, 1993.

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H, Berns Darren, et United States. National Aeronautics and Space Administration., dir. Performance of a low-power subsonic-arc-attachment arcjet thruster. [Washington, D.C.] : NASA, 1993.

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Lim, Sung Kyu. Design for High Performance, Low Power, and Reliable 3D Integrated Circuits. New York, NY : Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4419-9542-1.

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Ho, Ron, et Robert Drost, dir. Coupled Data Communication Techniques for High-Performance and Low-Power Computing. Boston, MA : Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6588-2.

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Chapitres de livres sur le sujet "LOW POWER PERFORMANCE"

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Elrabaa, Muhammad S., Issam S. Abu-Khater et Mohamed I. Elmasry. « Low-Power High-Performance Adders ». Dans Advanced Low-Power Digital Circuit Techniques, 7–29. Boston, MA : Springer US, 1997. http://dx.doi.org/10.1007/978-1-4419-8546-0_2.

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Elrabaa, Muhammad S., Issam S. Abu-Khater et Mohamed I. Elmasry. « Low-Power High-Performance Multipliers ». Dans Advanced Low-Power Digital Circuit Techniques, 31–81. Boston, MA : Springer US, 1997. http://dx.doi.org/10.1007/978-1-4419-8546-0_3.

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Verma, Aishita, Anum Khan et Subodh Wairya. « Low-Power High-Performance Hybrid Scalable ». Dans Proceedings of First International Conference on Computational Electronics for Wireless Communications, 161–72. Singapore : Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-6246-1_14.

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Steyaert, M., J. Crols et G. Plas. « A High Performance RDS-detector for Low Voltage Applications ». Dans Low-Voltage Low-Power Analog Integrated Circuits, 7–19. Boston, MA : Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2283-6_2.

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Nawathe, Umesh Gajanan. « Design of High Performance Low Power Microprocessors ». Dans CMOS Processors and Memories, 3–27. Dordrecht : Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9216-8_1.

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Nikshepa, Vasudeva Pai et Udaya Kumar K. Shenoy. « 6LowPan—Performance Analysis on Low Power Networks ». Dans International Conference on Computer Networks and Communication Technologies, 145–56. Singapore : Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8681-6_15.

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Lakshmi Priya, G., M. Venkatesh, S. Preethi, T. Venish Kumar et N. B. Balamurugan. « Performance Analysis of Emerging Low-Power Junctionless Tunnel FETs ». Dans Emerging Low-Power Semiconductor Devices, 107–25. Boca Raton : CRC Press, 2022. http://dx.doi.org/10.1201/9781003240778-6.

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Devi, Padma, Gurinder pal Singh et Balwinder singh. « Low Power Optimized Array Multiplier with Reduced Area ». Dans High Performance Architecture and Grid Computing, 224–32. Berlin, Heidelberg : Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-22577-2_30.

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Baskiyar, Sanjeev, et Kiran Kumar Palli. « Low Power Scheduling of DAGs to Minimize Finish Times ». Dans High Performance Computing - HiPC 2006, 353–62. Berlin, Heidelberg : Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11945918_36.

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Li, Yong, Zhiying Wang, Jian Ruan et Kui Dai. « A Low-Power Globally Synchronous Locally Asynchronous FFT Processor ». Dans High Performance Computing and Communications, 168–79. Berlin, Heidelberg : Springer Berlin Heidelberg, 2007. http://dx.doi.org/10.1007/978-3-540-75444-2_21.

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Actes de conférences sur le sujet "LOW POWER PERFORMANCE"

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CURRAN, FRANCIS, et CHARLES SARMIENTO. « Low power arcjet performance ». Dans 21st International Electric Propulsion Conference. Reston, Virigina : American Institute of Aeronautics and Astronautics, 1990. http://dx.doi.org/10.2514/6.1990-2578.

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Albera, G., et R. I. Bahar. « Power/performance advantages of victim buffer in high-performance processors ». Dans Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design. IEEE, 1999. http://dx.doi.org/10.1109/lpd.1999.750402.

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« W2B : High Performance Low Power Circuits ». Dans 2018 31st IEEE International System-on-Chip Conference (SOCC). IEEE, 2018. http://dx.doi.org/10.1109/socc.2018.8618573.

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Guthaus, Matthew R., et Baris Taskin. « High-performance, low-power resonant clocking ». Dans the International Conference. New York, New York, USA : ACM Press, 2012. http://dx.doi.org/10.1145/2429384.2429545.

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Belikov, M., O. Gorshkov, V. Muravlev, R. Rizakhanov, A. Shagayda et A. Snnirev. « High-performance low power Hall thruster ». Dans 37th Joint Propulsion Conference and Exhibit. Reston, Virigina : American Institute of Aeronautics and Astronautics, 2001. http://dx.doi.org/10.2514/6.2001-3780.

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Xiong, Wade, et Vyshnavi Suntharalingam. « High Performance and Low Power Devices ». Dans 2006 IEEE international SOI. IEEE, 2006. http://dx.doi.org/10.1109/soi.2006.284407.

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« High Performance and Low Power Devices ». Dans 2006 IEEE international SOI Conferencee Proceedings. IEEE, 2006. http://dx.doi.org/10.1109/soi.2006.284408.

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Senejani, M. Nadi, M. Hosseinghadiry et M. Miryahyaei. « Low Dynamic Power High Performance Adder ». Dans 2009 International Conference on Future Computer and Communication (ICFCC). IEEE, 2009. http://dx.doi.org/10.1109/icfcc.2009.99.

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Veera Boopathy E, Raghul G. et Karthick K. « Low power and high performance MOSFET ». Dans 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA). IEEE, 2015. http://dx.doi.org/10.1109/vlsi-sata.2015.7050455.

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Prouty, M., et R. Johnson. « Small, Low Power, High Performance Magnetometers ». Dans EGM 2010 International Workshop. European Association of Geoscientists & Engineers, 2010. http://dx.doi.org/10.3997/2214-4609-pdb.165.a_op_11.

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Rapports d'organisations sur le sujet "LOW POWER PERFORMANCE"

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Rajive Ganguli et Sukumar Bandopadhyay. Low-Rank Coal Grinding Performance Versus Power Plant Performance. Office of Scientific and Technical Information (OSTI), décembre 2008. http://dx.doi.org/10.2172/963349.

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Nelson, Brian A. ICC Experiment Performance Improvement through Advanced Feedback Controllers for High-Power Low-Cost Switching Power Amplifiers. US : Nelson Scientific Explorations L.L.C., Mountlake Terrace WA, octobre 2006. http://dx.doi.org/10.2172/893760.

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Tripathi, J., et J. de Oliveira, dir. Performance Evaluation of the Routing Protocol for Low-Power and Lossy Networks (RPL). RFC Editor, octobre 2012. http://dx.doi.org/10.17487/rfc6687.

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ROZANOVA, N. CONTENT OF THE REPUTATION OF A REGIONAL POWER IN THE CONTEXT OF A NORMATIVE ASSESSMENT OF ITS PERFORMANCE. Science and Innovation Center Publishing House, 2021. http://dx.doi.org/10.12731/2070-7568-2021-10-5-1-39-48.

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The article reflects the results of the research of the information component of the concept “the reputation of the regional (executive) power” on the basis of the normative approach. The interrelation between the evaluation indicators of the regional executive power activity efficiency and the power reputation content is shown, based on the mass questionnaire survey of the population of 6 regions of the Central Federal District (sample of 1,500 people). The conclusion about rather low potential of influence of existing at the moment normative system of evaluation of efficiency of regional executive authorities on the process of formation of its reputation among the population is made.
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Hacke, P., K. Terwilliger et S. Kurtz. In-Situ Measurement of Crystalline Silicon Modules Undergoing Potential-Induced Degradation in Damp Heat Stress Testing for Estimation of Low-Light Power Performance. Office of Scientific and Technical Information (OSTI), août 2013. http://dx.doi.org/10.2172/1090973.

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Nuttall, Albert H. Performance of Power-Law Processor with Normalization for Random Signals of Unknown Structure. Fort Belvoir, VA : Defense Technical Information Center, mai 1997. http://dx.doi.org/10.21236/ada327076.

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Oduncu, Arif. Country Diagnostic Study – The Kyrgyz Republic. Islamic Development Bank Institute, décembre 2021. http://dx.doi.org/10.55780/rp21001.

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The Country Diagnostic Study (CDS) for the Kyrgyz Republic uses the Hausmann-Rodrik-Velasco growth diagnostics model to identify the binding constraints being faced in its quest for higher and more sustained economic growth and make recommendations to relax these constraints. Hence, the findings of the CDS can help the Islamic Development Bank in identifying areas where it can have a greater impact and provide an evidence-basis to support the development of the Member Country Partnership Strategy (MCPS). During the last two decades, the Kyrgyz Republic has recorded low performance in economic development. The country recorded only 3.0 percent of average annual Purchasing Power Parity (PPP)-adjusted Gross Domestic Product (GDP) per capita growth from 2000 to 2019. The Kyrgyz Republic is facing several economic and social problems that are challenging its economic development model. This CDS report shows that the most binding constraints to inclusive and sustainable growth include i) low human capital, ii) poor infrastructure, iii) government and market failures, and iv) high cost of capital. The Kyrgyz development model’s performance is a subject of concern not only for the government and other local stakeholders but also for the technical and financial partners of the Kyrgyz Republic, including the Islamic Development Bank. The MCPS aims to contribute to the global efforts made by the Kyrgyz Republic to meet its economic and social needs through leveraging opportunities offered by the new business model of the Bank. Given the Kyrgyz Republic’s positives, the Bank can consider financing transport, energy and ICT infrastructure projects and supporting manufacturing and agricultural sectors to assist economic growth.
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Claus, Ana, Borzooye Jafarizadeh, Azmal Huda Chowdhury, Neziah Pala et Chunlei Wang. Testbed for Pressure Sensors. Florida International University, octobre 2021. http://dx.doi.org/10.25148/mmeurs.009771.

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Currently, several studies and experiments are being done to create a new generation of ultra-low-power wearable sensors. For instance, our group is currently working towards the development of a high-performance flexible pressure sensor. However, with the creation of new sensors, a need for a standard test method is necessary. Therefore, we opted to create a standardized testbed to evaluate the pressure applied to sensors. A pulse wave is generated when the heart pumps blood causing a change in the volume of the blood vessel. In order to eliminate the need of human subjects when testing pressure sensors, we utilized polymeric material, which mimics human flesh. The goal is to simulate human pulse by pumping air into a polymeric pocket which s deformed. The project is realized by stepper motor and controlled with an Arduino board. Furthermore, this device has the ability to simulate pulse wave form with different frequencies. This in turn allows us to simulate conditions such as bradycardia, tachycardia, systolic pressure, and diastolic pressure.
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Nuttall, Albert H. Near-Optimum Detection Performance of Power-Law Processors for Random Signals of Unknown Locations, Structure, Extent, and Arbitrary Strengths,. Fort Belvoir, VA : Defense Technical Information Center, avril 1996. http://dx.doi.org/10.21236/ada309568.

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Boards for all ? A review of power, policy and people on the boards of organisations active in global health. Global Health 50/50, mars 2022. http://dx.doi.org/10.56649/ucet6863.

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The fifth annual Global Health 50/50 report, Boards for all?, presents our first-ever analysis of the gender and geography of who governs global health. Through an examination of the demographics of over 2,000 board members of the most influential organisations active in global health, the report warns that global health is not living up to its name. The report further presents its annual review of the equality- and gender-related policies and practices of 200 global organisations. Building on five years of evidence, it finds signs of rapid progress in building more equitable and gender-responsive global health organisations, while also revealing stagnating progress among a large subset of global health organisations. For the first time, the Index categorises all organisations by performance and presents dedicated pages for each organisation to explore and compare findings. Boards for all? is a call to realise a globally representative and equitable global health governance that can deliver health for all. "Ensuring the leadership and influence of people from low- and middle-income countries, and especially women, is not only a question of equity - however essential - but of the very relevance, effectiveness and impact of the global health enterprise." Elhadj As Sy, Chair of the Kofi Annan Foundation
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