Littérature scientifique sur le sujet « LNA CIRCUIT »
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Articles de revues sur le sujet "LNA CIRCUIT"
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Malmqvist, R., C. Samuelsson, A. Gustafsson, P. Rantakari, S. Reyaz, T. Vähä-Heikkilä, A. Rydberg, J. Varis, D. Smith et R. Baggen. « A K-Band RF-MEMS-Enabled Reconfigurable and Multifunctional Low-Noise Amplifier Hybrid Circuit ». Active and Passive Electronic Components 2011 (2011) : 1–7. http://dx.doi.org/10.1155/2011/284767.
Texte intégralRésumé :
A K-band (18–26.5 GHz) RF-MEMS-enabled reconfigurable and multifunctional dual-path LNA hybrid circuit (optimised for lowest/highest possible noise figure/linearity, resp.) is presented, together with its subcircuit parts. The two MEMS-switched low-NF (higher gain) and high-linearity (lower gain) LNA circuits (paths) present 16.0 dB/8.2 dB, 2.8 dB/4.9 dB and 15 dBm/20 dBm of small-signal gain, noise figure, and 1 dB compression point at 24 GHz, respectively. Compared with the two (fixed) LNA subcircuits used within this design, the MEMS-switched LNA circuit functions show minimum 0.6–1.3 dB higher NF together with similar values ofP1 dBat 18–25 GHz. The gain of one LNA circuit path is reduced by 25–30 dB when the MEMS switch and active circuitry used within in the same switching branch are switched off to select the other LNA path and minimise power consumption.
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Ma, Zhenyang, Jiahao Liu, Zhaobin Duan, Chunlei Shi et Shaonan He. « Analysis of Indirect Lightning Effects on Low-Noise Amplifier and Protection Design ». Electronics 12, no 24 (6 décembre 2023) : 4912. http://dx.doi.org/10.3390/electronics12244912.
Texte intégralRésumé :
In order to analyze the interference mechanisms of indirect lightning effects on a low-noise amplifier (LNA), a circuit model of the LNA was constructed based on the advanced design system 2020 (ADS 2020) software. Lightning pulse injection simulations were conducted to explore the influence of lightning pulses on the performance of the LNA. A pin injection test was performed to investigate the interference and damage threshold of the LNA. A protective circuit incorporating the transient voltage suppressor (TVS) and Darlington structure was designed through simulation, employing the ADS 2020 for the LNA. The research findings reveal that the interference threshold for the LNA is 60 V, while the damage threshold is determined to be 100 V. The protective circuit demonstrates a measured insertion loss of 0.1 dB, a response time of 1.5 ns, and a peak output voltage of 20 V. The research results indicate that the protective circuit can effectively reduce the impact of lightning’s indirect effects on the LNA. In the future, we will continue the design work of the protective circuit and proceed with physical fabrication and experimental validation.
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Zhang, Yu, Shu Hui Yang et Yin Chao Chen. « Design and Simulation of a 5.8GHz Low Noise Amplifier Used in RFID ». Applied Mechanics and Materials 441 (décembre 2013) : 133–36. http://dx.doi.org/10.4028/www.scientific.net/amm.441.133.
Texte intégralRésumé :
A 5.8GHz single-stage low noise amplifier (LNA) for radio frequency identification devices (RFID) applications was proposed according to the theory of LNA. It has been realized by ATF-541M4 transistor and its peripheral circuit, such as bias circuit, input and output matching network. The proposed LNA provides a gain of 12.696dB from the analysis of ADS. The LNA achieves 0.951dB noise figure (NF) at the frequency of 5.8GHz. The simulation results show that this LNA has good noise characteristic, the NF is less than other published paper.
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Chopde, Abhay, Prashik Sadar, Ashutosh Sabale, Piyush Thite et Raghvendra Zarkar. « Design of 2.4 GHz LNA of 400 MHz Bandwidth ». International Journal of Innovative Technology and Exploring Engineering 11, no 3 (30 janvier 2022) : 65–69. http://dx.doi.org/10.35940/ijitee.c9760.0111322.
Texte intégralRésumé :
Low Noise Amplifier (LNA) is the most important front-end block of the receiver. LNA’s Noise figure (NF) and Scattering Parameters affect the overall performance of the whole receiver circuit. Nowadays in the era of 5G technology, The quality of data that is being transmitted is increased. So there is a need for higher bandwidth to transfer data with higher speed. In such a case, communication blocks need an update. The research is carried out for the advancement of the LNA. The primary goal of LNA design is to lower the Noise Figure and return losses. The paper aims to design a 2.4 GHz LNA having a bandwidth of 400 MHz. The circuit is designed with the help of single-stub microstrip lines. We tried to keep the length of microstrip lines as minimum as possible. The transistor ATF-21170 Gallium Arsenide Field Effect Transistor (GaAs FET) is used in this work. The circuit is simulated in the Keysight Advance Design System (ADS). The amplifier is manually designed using standard methods. LNA is unconditionally stable for the frequency range of 2.2 GHz to 2.6 GHz. To build impedance matching circuits of the amplifier smith chart is used. It is observed that the LNA gain (S21) is greater than 15.3 dB, NF less than 1.2 dB, Input return loss (S11) is less than -13.3 dB, Output return loss (S22) is less than -17.1 dB over the 400 MHz bandwidth ranging from 2.2 to 2.6 GHz. This has, to the best of the authors' knowledge, not been presented in literature before.
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Wei, Yiding, Jun Liu, Dengbao Sun, Guodong Su et Junchao Wang. « From Netlist to Manufacturable Layout : An Auto-Layout Algorithm Optimized for Radio Frequency Integrated Circuits ». Symmetry 15, no 6 (16 juin 2023) : 1272. http://dx.doi.org/10.3390/sym15061272.
Texte intégralRésumé :
Layout stitching is a repetitive and tedious task of the radio frequency integrated circuit (RFIC) design process. While academic research on layout splicing algorithms mainly focuses on analog and digital circuits, there is still a lack of well-developed algorithms for RFICs. An RFIC system usually has a symmetrical layout, such as transmitter and receiver components, low-noise amplifier (LNA), an SPDT switch, etc. This paper aims to address this gap by proposing an automated procedure for the layout of RFICs by relying on the basic device/PCell structure based on the interconnection among circuit topologies. This approach makes the in-series generation of layouts and automatic splicing based on circuit logic possible, resulting in superior stitching performance compared with related modules in Advanced Design System. To demonstrate the physical application possibilities, we implemented our algorithm on an LNA and a switch circuit.
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Castagnola, Juan L., Fortunato C. Dualibe, Agustín M. Laprovitta et Hugo García-Vázquez. « A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio ». Electronics 9, no 5 (11 mai 2020) : 785. http://dx.doi.org/10.3390/electronics9050785.
Texte intégralRésumé :
This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.
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Zhou, Shaohua, et Jian Wang. « An Experimental Investigation of the Degradation of CMOS Low-Noise Amplifier Specifications at Different Temperatures ». Micromachines 13, no 8 (6 août 2022) : 1268. http://dx.doi.org/10.3390/mi13081268.
Texte intégralRésumé :
To investigate the relationship between the specifications degradation of a low-noise amplifier (LNA) and temperature, we experimentally investigated the degradation characteristics of the specifications of the LNA at different temperatures. The small-signal gain (S21) of the LNA decreases with increasing temperature. This paper discusses and analyzes the experimental results in detail, and the reasons for the degradation of LNA specifications with temperature changes are known. Finally, we have tried to use the structure already available in the literature for the PA temperature compensation circuit for the temperature compensation of the LNA. The results show that the existing circuit structure for PA temperature compensation in the literature can also effectively compensate for the S21 and NF degradation of the LNA due to the temperature increase.
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Charisma, Atik, Nahal Widianto, M. Reza Hidayat et Handoko Rusiana Iskandar. « Low Noise Amplifier Dual Stage dengan Metode π-Junction untuk Long Term Evolution (LTE) ». TELKA - Telekomunikasi Elektronika Komputasi dan Kontrol 8, no 2 (21 novembre 2022) : 116–25. http://dx.doi.org/10.15575/telka.v8n2.116-125.
Texte intégralRésumé :
Long Term Evolution (LTE) merupakan teknologi tanpa kabel yang memerlukan komponen-komponen elektronika untuk mendukung performansinya. Salah satu komponen elektronika tersebut yaitu Low Noise Amplifier (LNA) sebagai penguat di bagian penerima. Penelitian ini merancamg Low Noise Amplifier dengan bantuan software berdasarkan perhitungan. LNA bekerja pada frekuensi 1,8 GHz yang merupakan pita frekuensi LTE. Tahapan perancangan LNA dimulai dari pemilihan transistor, rangkaian DC bias, dan penyesuai impedansi. Transistor ATF 34143 menjadi pilihan untuk LNA karena sesuai dengan spesifikasi yang dibutuhkan. Komponen perancangan LNA untuk rangkaian DC meliputi resistor, kapasitor, dan induktor. Salah satu metode yang digunakan pada rangkaian penyesui impedansi yaitu metode π-junction pada bagian input dan output. Rangkaian penyesuai impedansi menggunakan mikrostrip. Sebuah transitor ditambahkan secara cascade untuk meningkatkan performansi LNA. Paremeter-parameter penting sebagai kinerja LNA yaitu noise figure, faktor kestabilan, dan gain. Hasil simulasi perancangan LNA ini memperoleh nilai noise figure sebesar 0,561 dB, gain 36,463 dB, dan faktor kestabilan 1,785. Parameter hasil perancangan telah memenuhi spesfikasi LNA serta kebutuhan LTE.Long Term Evolution (LTE) is a wireless technology that requires electronic components to support its performance. One of the electronic components is the Low Noise Amplifier (LNA) as an amplifier at the receiver. This study designed a Low Noise Amplifier with the help of software based on calculations. LNA works on the 1.8 GHz frequency which is the LTE frequency band. The LNA design stages start from the selection of transistors, DC bias circuits, and impedance matching. The ATF 34143 transistor is the choice for LNA because it fits the required specifications. LNA design components for DC circuits include resistors, capacitors, and inductors. One of the methods used in impedance matching circuits is the π-junction method on the input and output sections. Impedance adjustment circuit using microstrip. A transistor is added cascade to improve LNA performance. Important parameters as the performance of LNA are noise figure, stability factor, and gain. The simulation results of this LNA design obtain a noise figure value of 0.561 dB, a gain of 36.463 dB, and a stability factor of 1.785. The design parameters have met the LNA specifications and LTE requirements.
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Radic, Jelena, Alena Djugova et Mirjana Videnovic-Misic. « Influence of current reuse LNA circuit parameters on its noise figure ». Serbian Journal of Electrical Engineering 6, no 3 (2009) : 439–49. http://dx.doi.org/10.2298/sjee0903439r.
Texte intégralRésumé :
A 2.4 GHz low noise amplifier (LNA) with a bias current reuse technique is proposed in this work. To obtain the optimum noise figure (NF) value, dependence of NF on its most influential LNA parameters has been analyzed. Taking into account the LNA design requirements for other figures of merit, values of the circuit parameters are given for the optimum noise figure.
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Sampath Kumar, V., et Kartik Upreti. « Novel low noise amplifier approach for deep brain stimulation ». Journal of Physics : Conference Series 2570, no 1 (1 août 2023) : 012033. http://dx.doi.org/10.1088/1742-6596/2570/1/012033.
Texte intégralRésumé :
Abstract This paper presents an analysis for a multi-stage Low Noise Amplifier (LNA) for application on deep brain stimulation. A low noise amplifier (LNA) with high gain, moderate bandwidth and reduced noise is designed and simulated using LT Spice and PTM BSIM4 CMOS models. The novel LNA circuit topology is proposed which uses a cascaded style to improve mid-band gain of an LNA. The proposed LNA achieves a gain margin which ranges between 60-67 (dB), 2X times; Phase Margin which ranges between 145 to 154 (deg), 3X times; Gain which ranges between 66 to 75 (dB), 2X times and bandwidth from kHz to MHz range. The current biasing circuit is used for enhancing stability and gain range. Also, optimal noise figure is achieved with the help of cascading input matching along with source degeneration technique.
Thèses sur le sujet "LNA CIRCUIT"
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Yu, Chuanzhao. « STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY ». Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3551.
Texte intégralRésumé :
The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices – low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices – from device level to circuit level; The more real voltage stress case – high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future.Ph.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
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Green, Matthew Richard. « Development of a temperature insensitive current controlled current source for LNA bias circuit applications ». Thesis, Oxford Brookes University, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.444330.
Texte intégralRésumé :
The research described in this thesis is concerned with the analysis, design and development of a novel temperature insensitive Current Controlled Current Source (CCCS), in bipolar technology, in order to provide accurate amplification of a Proportional To Absolute Temperature (PTAT) reference current. The output current of the CCCS is intended for application as the bias current for a bipolar Low Noise Amplifier (LNA) in order to minimise gain variations with temperature across the industrial temperature range (-40·C to 8S·C). The thesis begins with an explanation of key parameters concerned with LNA design and a target specification is defined. In Chapter 2, a conventional LNA, with constant with temperature bias current, is developed following a methodical approach based on conventional techniques. This meets the previously defined specification at room temperature but exhibits large gain variations with changes in temperature. The analysis and simulation results of this conventional LNA serve as a benchmark for comparison with later designs. In order to minimise any gain variations with temperature of a bipolar amplifier it is well known that the applied bias current should be PT AT. Thus, a thorough analysis and comparative review of traditional and novel PTAT reference current generator circuits is conducted in Chapters 3 and 4. Based on these findings the PTAT generator exhibiting best performance in terms of output current accuracy and insensitivity to power supply variations is presented. However, this circuit cannot accurately produce large rnA level currents necessary for LNA bias applications so that sufficient linearity of the LNA is maintained. Thus, a need for some form of accurate CCCS or Voltage Controlled Current Source (VCCS), which should be temperature insensitive in order to preserve the desired temperature coefficient of the reference current/voltage, is highlighted.Traditional VCCS/CCCS designs are investigated in Chapter 5. Limitations of these approaches leads to the design and development ofa novel CCCS with built in PTAT reference. The presented CCCS utilises a new, previously unseen, architecture and has led to a patent application [1]. The author has reported the majority of this work in technical literature [2-4]. In Chapter 6, the output of the novel CCCS is adapted to include the conventional LNA circuit designed previously in Chapter 2. The results of the combined LNA and CCCS are compared with the conventional LNA. The combined LNA and CCCS offers a dramatic reduction in gain variation with temperature.
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Costa, Arthur Liraneto Torres. « Inductorless balun low-noise amplifier (LNA) for RF wideband application to IEEE 802.22 ». reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/106442.
Texte intégralRésumé :
Um novo circuito amplificador de 50 MHz - 1 GHz com alta linearidade para o padrão IEEE 802.22 “wireless regional area” (WRAN) é apresentado. Ele foi implementado sem nenhum indutor e oferece uma saída diferencial para ser utilizada como balun. Técnicas de cancelamento de ruído e aumento de linearidade foram usadas para melhorar a performace do amplificador de modo que eles pudessem ser otimizados separadamente. A linearidade foi melhorada utilizando transistores conectados como diodo. O amplificador foi implementado em um processo CMOS 130 nm, em uma área compacta de 136 m x 71 m. As simulações são apresentadas para esquemáticos pós-leiaute para duas classes diferentes de projeto: um visando a melhor linearidade e o outro a melhor Figura de Ruído (FR). Quando otimizado para melhor linearidade, os resultados de simulação atingem um ganho de tensão > 23.7 dB (ganho de potência > 19.1 dB), uma figura de ruído < 3.6 dB na banda inteira (com 2.4 dB min), um ponto de intersecção de terceira ordem (IIP3) > 3.3 dBm (7.6 dBm max) e um coeficiente de reflexão de entrada S11 < -16 dB. Quando otimizado para melhor figura de ruído, ele atinge um ganho de tensão > 24.7 dB (ganho de potência > 19.8 dB), uma FR < 2 dB na banda inteira, um IIP3 > -0.3 dBm e um S11 < -11 dB. Resultados de simulação Monte Carlo confirmam baixa sensibilidade à variabilidade de processo. Além disso, uma baixa sensibilidade com a temperatura na faixa de -55 até 125 C foi observada para Ganho, FR e S11. Consumo de potência é 17.6 mA sob fonte de alimentação de 1.2 V.A new 50 MHz - 1 GHz low-noise amplifier circuit with high linearity for IEEE 802.22 wireless regional area network (WRAN) is presented. It was implemented without any inductor and offers a differential output for balun use. Noise cancelling and linearity boosting techniques were used to improve the amplifier performance in a way they can be separately optimized. Linearity was improved using diode-connected transistors. The amplifier was implemented in a 130 nm CMOS process in a compact 136 m x 71 m area. Simulations are presented for post-layout schematics for two classes of design: one for best linearity, another for best noise figure (NF). When optimized for best linearity, simulation results achieve a voltage gain > 23.7 dB (power gain > 19.1 dB), a NF < 3.6 dB over the entire band (with 2.4 dB min figure), an input third-order intercept point (IIP3) > 3.3 dBm (7.6 dBm max.) and an input power reflection coefficient S11 < -16 dB. When optimized for best NF, it achieves a voltage gain > 24.7 dB (power gain > 19.8 dB), a NF < 2 dB over the entire band, an IIP3 > -0.3 dBm and an S11 < -11 dB. Monte Carlo simulation results confirm low sensitivity to process variations. Also a low sensitivity to temperature within the range -55 to 125 C was observed for Gain, NF and S11. Power consumption is 17.6 mA under a 1.2 V supply.
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yasami, saeed. « Design and Evaluation of an Ultra-Low PowerLow Noise Amplifier LNA ». Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-50923.
Texte intégralRésumé :
This master thesis deals with the study of ultra low power Low Noise Amplifier (LNA) for use inmedical implant device. Usually, low power consumption is required for a long battery lifetime andlonger operation. The target technology is 90nm CMOS process.First basic principle of LNA is discussed. Then based on a literature review of LNA design, theproposed LNA is presented in sub-threshold region which reduce power consumption through scalingthe supply voltage and through scaling current.The circuit implementation and simulations is presented to testify the performance of LNA .Besides thepower consumption simulated under the typical supply voltage (1V), it is also measured under someother low supply voltages (down to 0.5V) to investigate the minimum power consumption and theminimum noise figure. Evaluation results show that at a supply voltage of 1V the LNA performs a totalpower consumption of 20mW and a noise of 1dB. Proper performance is achieved with a current ofdown to 200uA and supply voltage of down to 0.45V, and a total power consumption of 200uW
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Janse, van Rensburg Christo. « A SiGe BiCMOS LNA for mm-wave applications ». Diss., University of Pretoria, 2012. http://hdl.handle.net/2263/26501.
Texte intégralRésumé :
A 5 GHz continuous unlicensed bandwidth is available at millimeter-wave (mm-wave) frequencies around 60 GHz and offers the prospect for multi gigabit wireless applications. The inherent atmospheric attenuation at 60 GHz due to oxygen absorption makes the frequency range ideal for short distance communication networks. For these mm-wave wireless networks, the low noise amplifier (LNA) is a critical subsystem determining the receiver performance i.e., the noise figure (NF) and receiver sensitivity. It however proves challenging to realise high performance mm-wave LNAs in a silicon (Si) complementary metal-oxide semiconductor (CMOS) technology. The mm-wave passive devices, specifically on-chip inductors, experience high propagation loss due to the conductivity of the Si substrate at mm-wave frequencies, degrading the performance of the LNA and subsequently the performance of the receiver architecture. The research is aimed at realising a high performance mm-wave LNA in a Si BiCMOS technology. The focal points are firstly, the fundamental understanding of the various forms of losses passive inductors experience and the techniques to address these issues, and secondly, whether the performance of mm-wave passive inductors can be improved by means of geometry optimising. An associated hypothesis is formulated, where the research outcome results in a preferred passive inductor and formulates an optimised passive inductor for mm-wave applications. The performance of the mm-wave inductor is evaluated using the quality factor (Q-factor) as a figure of merit. An increased inductor Q-factor translates to improved LNA input and output matching performance and contributes to the lowering of the LNA NF. The passive inductors are designed and simulated in a 2.5D electromagnetic (EM) simulator. The electrical characteristics of the passive structures are exported to a SPICE netlist which is included in a circuit simulator to evaluate and investigate the LNA performance. Two LNAs are designed and prototyped using the 13μ-m SiGe BiCMOS process from IBM as part of the experimental process to validate the hypothesis. One LNA implements the preferred inductor structures as a benchmark, while the second LNA, identical to the first, replaces one inductor with the optimised inductor. Experimental verification allows complete characterization of the passive inductors and the performance of the LNAs to prove the hypothesis. According to the author's knowledge, the slow-wave coplanar waveguide (S-CPW) achieves a higher Q-factor than microstrip and coplanar waveguide (CPW) transmission lines at mm-wave frequencies implemented for the 130 nm SiGe BiCMOS technology node. In literature, specific S-CPW transmission line geometry parameters have previously been investigated, but this work optimises the signal-to-ground spacing of the S-CPW transmission lines without changing the characteristic impedance of the lines. Optimising the S-CPW transmission line for 60 GHz increases the Q-factor from 38 to 50 in simulation, a 32 % improvement, and from 8 to 10 in measurements. Furthermore, replacing only one inductor in the output matching network of the LNA with the higher Q-factor inductor, improves the input and output matching performance of the LNA, resulting in a 5 dB input and output reflection coefficient improvement. Although a 5 dB improvement in matching performance is obtained, the resultant noise and gain performance show no significant improvement. The single stage LNAs achieve a simulated gain and NF of 13 dB and 5.3 dB respectively, and dissipate 6 mW from the 1.5 V supply. The LNA focused to attain high gain and a low NF, trading off linearity and as a result obtained poor 1 dB compression of -21.7 dBm. The LNA results are not state of the art but are comparable to SiGe BiCMOS LNAs presented in literature, achieving similar gain, NF and power dissipation figures.Dissertation (MEng)--University of Pretoria, 2012.
Electrical, Electronic and Computer Engineering
unrestricted
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Gong, Fei. « Front End Circuit Module Designs for A Digitally Controlled Channelized SDR Receiver Architecture ». The Ohio State University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=osu1322606039.
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De, Sousa Marinho Rafael. « Co-design methodology of 60 GHz filter-L-NA ». Thesis, Limoges, 2019. http://www.theses.fr/2019LIMO0095.
Texte intégralRésumé :
Ce travail montre les résultats et discussions à propos du projet partagé des structures pour un récepteur radio-fréquence des ondes millimétriques. Deux structures ont été étudiés : Le LNA et le résonateur en anneau. Ces structures ont été développes en utilisant des nouvelles techniques de projet de circuit micro-électroniques et utilisation des outils CAD.Les circuit ont été fabriqués avec la technologie QuBIC NXP®BiCMOS SiGe:C de 0.25μm.Les résultats de mesure sont en conformité avec l’état de l’art pour des LNAThis work presents the results and discussions about shared design (co-design)of structures for a RF receptor in millimetric waves. Two structures were mainly studied: TheLNA and the resonator filter. Both structures were developed using novel microelectronic circuitdesign techniques and with the extensive use of CAD software. The circuits were fabricatedusing a0.25μmBiCMOS SiGe:C QuBIC technology from NXP®semiconductors, and themeasurement results are in conformity with the state-of-the-art
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Thrivikraman, Tushar. « Analysis and Design of Low-Noise Amplifiers in Silicon-Germanium Hetrojunction Bipolar Technology for Radar and Communication Systems ». Thesis, Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19755.
Texte intégralRésumé :
This thesis presents an overview of the simulation, design, and measurement of state-of-the-art Silicon-Germanium Hetro-Junction Bipolar Transistor (SiGe HBT) low-noise amplifiers (LNAs). The LNA design trade-off space is presented and methods for achieving an optimized design are discussed.
In Chapter 1, we review the importance of LNAs and the benefits of SiGe HBT technology in high frequency amplifier design. Chapter 2 introduces LNA design and basic noise theory. A graphical LNA design approach is presented to aid in understanding of the high-frequency LNA design process. Chapter 3 presents an LNA design optimization method for power constrained applications. Measured results using this design technique are highlighted and shown to have record performance. Lastly, in Chapter 4, we highlight cryogenic noise performance and present measured results from cryogenic operation of SiGe HBT LNAs.
We demonstrate in this thesis that SiGe HBT LNAs have the capability to meet the demanding needs for next generation wireless systems. The aim of the analysis presented herein is to provide designers with the fundamentals of designing SiGe HBT LNAs through relevant design examples and measured results.
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Poh, Chung Hang. « Radio frequency circuit design and packaging for silicon-germanium hetrojunction bipolar technology ». Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31662.
Texte intégralRésumé :
Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: Cressler, John; Committee Member: Laskar, Joy; Committee Member: Papapolymerou, John. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Gaubert, Jean. « Contribution à l'étude d'interfaces analogiques hautes fréquences pour objets communicants à faible coût de fabrication ». Habilitation à diriger des recherches, Université de Provence - Aix-Marseille I, 2007. http://tel.archives-ouvertes.fr/tel-00796512.
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Le premier chapitre de ce mémoire intitulé "Amplificateurs faible bruit accordés pour systèmes intégrés CMOS" s'intéresse aux méthodes de conception permettant l'intégration complète de l'amplificateur faible bruit d'une (LNA) depuis la gamme des radiofréquences jusqu'à la gamme des fréquences millimétriques. Ces travaux ont été menés dans le cadre de la Thèse de Mathieu Egels et dans le cadre d'une convention de recherche avec la société ST-Microélectronics financée par le Conseil Général des Bouches du Rhône. Le deuxième chapitre est intitulé "Amplificateurs bas niveau large bande pour systèmes intégrés CMOS". Ce chapitre présente les solutions que nous avons développées au laboratoire qui permettent de contrôler la bande passante des amplificateurs faible bruit pour systèmes intégrés destinés aux applications utilisant les normes UWB ainsi que des études plus prospectives sur l'amplification distribuée CMOS pour des applications à très grandes bandes passantes. Dans la dernière partie de ce chapitre nous décrivons nos travaux concernant la mise en boîtier des circuits et systèmes intégrés haute fréquence et large bande. Ces différents travaux ont été réalisés d'une part dans le cadre des Thèses de Mathieu Egels, et de Marc Battista, dans le cadre d'une convention de recherche avec la société ST-Microélectronics financée par le Conseil Général des Bouches du Rhône, et d'autre part dans le cadre de la thèse de Romen Cubillo avec le soutien de la plateforme conception du Centre Intégré de Microélectronique de la région PACA (CIMPACA). Le troisième chapitre "Convertisseurs RF/DC pour la téléalimentation haute fréquence en RFID" décrit nos activités de recherche concernant les circuits et architectures pour la télé-alimentation des circuits intégrés au moyen d'une onde électromagnétique. Les applications ciblées concernent essentiellement les étiquettes électroniques sans contact dans le domaine des fréquences UHF pour lesquelles nous avons développé des circuits et des architectures pour les technologies CMOS standard. Ces travaux ont été réalisés dans le cadre de la Thèse de Emmanuel Bergeret dans le cadre d'une convention de recherche avec la société ST-Microélectronics soutenue par le Conseil Général des Bouches du Rhône. Dans ce mémoire nous nous attacherons à décrire l'état de l'art des différents thèmes de recherche abordés et à situer nos travaux vis-à-vis de cet état de l'art. Le détail de nos travaux de recherche étant disponible dans les différents articles et thèses référencés, nous donnerons dans ce mémoire uniquement les grandes lignes de nos études et les principaux résultats obtenus.
Livres sur le sujet "LNA CIRCUIT"
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Constaín Aragón, Alfredo José, et Efraín Bernal Alzate. Electrónica análoga. Bogotá. Colombia : Universidad de La Salle. Ediciones Unisalle, 2009. http://dx.doi.org/10.19052/9789588939551.
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Este texto se orienta fundamentalmente, al diseño, pero haciendo énfasis en la presencia de la realimentación (retroalimentación) negativa como concepto básico de estabilización de la operación de los circuitos. Interesa simultáneamente: entender cómo operan los circuitos analógicos completos a partir de las características operativas de sus unidades aisladas, aprender a colocar las configuraciones óptimas con los valores correctos de los componentes, cualquiera que sea el objetivo del circuito (Diseño), aprender a establecer las relaciones mutuas entre los valores de esos componentes para que el diseño sea repetible (Diseño con retroalimentación negativa), presentar modelos físicos de los dispositivos activos mejor que modelos circuitales convencionales. Esta variante permite trabajar con facilidad ensambles multi-etapa y presentar diversos ejemplos resueltos para indicar detalladamente los procesos de diseño.
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Sánchez Salcedo, Alejandro. Theory on DC Electric Circuits. Bogotá. Colombia : Universidad de La Salle. Ediciones Unisalle, 2016. http://dx.doi.org/10.19052/9789588939933.
Texte intégralRésumé :
This book is intended as a major support for the DC Electric Circuits course from the Electrical Engineering program and the Automation Engineering program at Universidad de La Salle. Its main contribution is to provide the students with a step-by-step explanation and detailed illustrations about the main concepts and analysis techniques of DC electric circuits and their related measurement systems.
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Morrison, Ralph. Grounding and shielding : Circuits and interference. Hoboken, New Jersey : John Wiley & Sons Inc., 2016.
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Engineers, Institution of Electrical. IEE proceedings : Circuits, devices, and systems. Stevenage, Herts : IEE, 1989.
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Engineers, Institution of Electrical. IEE proceedings : Circuits, devices, and systems. Stevenage, Herts : Institution of Electrical Engineers, 1994.
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Raphael, Pinaud, Tremere Liisa A et De Weerd Peter, dir. Plasticity in the visual system : From genes to circuits. New York : Springer, 2005.
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Roth, Charles H. Instructor's solutions manual for fundamentals of logic design. Australia : Thomson, 2004.
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Bernal, Enrique Cordero y. Sindicalismo en corto circuito : Novela de actualidad inspirada en los archivos de un periodista. México : Edamex, 1991.
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Memory, microprocessor, and ASIC. Boca Raton : CRC Press, 2003.
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Christopher, Bull, dir. Appropriate technology : Tools, choices and implications. San Diego : Academic Press, 1999.
Trouver le texte intégralChapitres de livres sur le sujet "LNA CIRCUIT"
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Nordholt, Ernst H. « Structured LNA design ». Dans Analog Circuit Design, 47–76. Boston, MA : Springer US, 2002. http://dx.doi.org/10.1007/0-306-47951-6_3.
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Yuan, Jiann-Shiun. « LNA Design for Variability ». Dans CMOS RF Circuit Design for Reliability and Variability, 55–69. Singapore : Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-0884-9_7.
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Mak, Pui-In, et Rui Paulo Martins. « A Full-Band Mobile-TV LNA with Mixed-Voltage ESD Protection in 90-nm CMOS ». Dans High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS, 35–54. New York, NY : Springer New York, 2012. http://dx.doi.org/10.1007/978-1-4419-9539-1_3.
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Rahman, Mustafijur, et Ramesh Harjani. « Dual-Path Noise Cancelling LNA ». Dans Analog Circuits and Signal Processing, 41–56. Cham : Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-21333-6_4.
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Baltus, Peter. « Put your power into SOA LNAs ! » Dans Analog Circuit Design, 337–58. Boston, MA : Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-2983-2_15.
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Leenaerts, Domine, et Nenad Pavlovic. « Design of wireless LAN circuits in RF-CMOS ». Dans Analog Circuit Design, 345–63. Boston, MA : Springer US, 2002. http://dx.doi.org/10.1007/0-306-47951-6_15.
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Leroux, Paul, Michiel Steyaert et K. U. Leuven. « RF-ESD Co-Design for High Performance CMOS LNAs ». Dans Analog Circuit Design, 207–26. Boston, MA : Springer US, 2003. http://dx.doi.org/10.1007/0-306-48707-1_9.
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Selvi, M., K. Thangaramya, M. S. Saranya, K. Kulothungan, S. Ganapathy et A. Kannan. « Classification of Medical Dataset Along with Topic Modeling Using LDA ». Dans Nanoelectronics, Circuits and Communication Systems, 1–11. Singapore : Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-0776-8_1.
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Wang, Mu-Chun, Hsin-Chia Yang et Ren-Hau Yang. « Parasitic Effect Degrading Cascode LNA Circuits with 0.18μm CMOS Process for 2.4GHz RFID Applications ». Dans Lecture Notes in Electrical Engineering, 561–69. Berlin, Heidelberg : Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-21697-8_71.
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Morabito, Carmela. « Dall’area di Broca al sensorio digitale, trasformazioni antropologiche in atto e ‘cervelli in movimento’ : una mente incorporata in un mondo digitalizzato. » Dans La narrazione come incontro, 81–101. Florence : Firenze University Press, 2022. http://dx.doi.org/10.36253/979-12-215-0045-5.07.
Texte intégralRésumé :
The new forms of social communication, with the increasing presence of images within the text, make us necessary to reconsider the cerebral basis of literacy and theyr reconfiguration via neural recycling. In the theoretical framework of Embodied philosophy of mind, we propose an analysis of the ‘extended writing”, actually using emoticon and emoji, in the light of our contemporary neuropsychological knowledge (hemispheric specialization and the functional circuit of literacy).
Actes de conférences sur le sujet "LNA CIRCUIT"
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Lehmeyer, Bernhard, Michel T. Ivrlac et Josef A. Nossek. « LNA noise parameter measurement ». Dans 2015 European Conference on Circuit Theory and Design (ECCTD). IEEE, 2015. http://dx.doi.org/10.1109/ecctd.2015.7300071.
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Hamani, Rachid, Cristian Andrei, Bernard Jarry et Mien Lintignat. « LNA circuit design counting the interconnect line parasitics ». Dans 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, 2014. http://dx.doi.org/10.1109/icecs.2014.7049994.
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Jato, Yolanda, et Amparo Herrera. « ESD structures impact analysis on a WLAN 802.11a LNA ». Dans 2007 European Microwave Integrated Circuit Conference. IEEE, 2007. http://dx.doi.org/10.1109/emicc.2007.4412686.
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Jain, Malika, et Ramesh Bharti. « Simulation of Low Power DVCC Based LNA for Wireless Receiver ». Dans 2021 Devices for Integrated Circuit (DevIC). IEEE, 2021. http://dx.doi.org/10.1109/devic50843.2021.9455835.
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Kobayashi, Kevin W., Charles Campbell, Cathy Lee, Justin Gallagher, John Shust et Andrew Botelho. « A reconfigurable S-/X-band GaN cascode LNA MMIC ». Dans 2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS). IEEE, 2017. http://dx.doi.org/10.1109/csics.2017.8240424.
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Vidojkovic, Maja, Mihai Sanduleanu, Johan van der Tang, Peter Baltus et Arthur van Roermund. « A broadband, inductorless LNA for multi-standard aplications ». Dans 2007 European Conference on Circuit Theory and Design (ECCTD 2007). IEEE, 2007. http://dx.doi.org/10.1109/ecctd.2007.4529586.
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Ciccognani, Walter, Franco Giannini, Ernesto Limiti et Patrick E. Longhi. « Full W-Band High-Gain LNA in mHEMT MMIC Technology ». Dans 2008 European Microwave Integrated Circuit Conference (EuMIC). IEEE, 2008. http://dx.doi.org/10.1109/emicc.2008.4772292.
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Dederer, J., S. Chartier, T. Feger, U. Spitzberg, A. Trasser et H. Schumacher. « Highly compact 3.1 -10.6 GHz UWB LNA in SiGe HBT technology ». Dans 2007 European Microwave Integrated Circuit Conference. IEEE, 2007. http://dx.doi.org/10.1109/emicc.2007.4412695.
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Tripathy, Dhananjaya, Debasish Nayak, Sudhansu Mohan Biswal, Sanjit Kumar Swain, Biswajit Baral et Satish Kumar Das. « A Low Power LNA using Current Reused Technique for UWB Application ». Dans 2019 Devices for Integrated Circuit (DevIC). IEEE, 2019. http://dx.doi.org/10.1109/devic.2019.8783936.
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Rezaei, H., E. Abiri et M. R. Salehi. « UWB LNA with out-band interference rejection exploiting multistage matching circuit ». Dans 2012 IEEE International Conference on Electronics Design, Systems and Applications (ICEDSA). IEEE, 2012. http://dx.doi.org/10.1109/icedsa.2012.6507777.
Texte intégralRapports d'organisations sur le sujet "LNA CIRCUIT"
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Filippo, Agustín, Carlos Guaipatín, Lucas Navarro et Federico Wyss. México y la cadena de valor de los semiconductores : oportunidades de cara al nuevo escenario global. Banco Interamericano de Desarrollo, juin 2022. http://dx.doi.org/10.18235/0004276.
Texte intégralRésumé :
Los semiconductores, chips, o circuitos integrados, son insumos clave para la producción del más amplio y variado espectro de actividades sociales y productivas. Debido a la pandemia, y a las vulnerabilidades propias de esta cadena de valor -que fueron analizadas en un estudio previo, la economía global enfrenta una crisis de abastecimiento de semiconductores impulsada por un quiebre estructural hacia una mayor demanda de productos digitales. Esto derivó en cuantiosos anuncios de inversión de las empresas líderes del sector, junto con fuertes estímulos de los gobiernos, para expandir su capacidad de producción. El nuevo escenario global de la cadena global de valor (CGV) de semiconductores en los próximos años, donde Estados Unidos ganará mayor peso, abre la pregunta sobre cuáles son las oportunidades y desafíos que se plantean para México. El presente estudio identifica un conjunto de dimensiones clave, como el talento, la innovación, la base de proveedudría, la infraestructura y la facilitación del comercio, para desarrollar la CGV de semiconductores en México en donde la acción de la política pública puede ser determinante. El trabajo se estructura en tres secciones además de la presente: la Sección 2 describe la CGV de semiconductores y la crisis de abastecimiento que la afecta; la Sección 3 se enfoca en el sector de semiconductores en México y, finalmente, en la Sección 4 se presentan las conclusiones y recomendaciones de política.
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Betancur Ortiz, Idabely, Cristian Arbey Velarde et Celeny Ortiz Restrepo. Situación epidemiológica de las variantes del virus SARS-CoV-2 detectadas en Antioquia, de diciembre 2020 a enero 2022. Instituto Nacional de Salud, janvier 2022. http://dx.doi.org/10.33610/01229907.2022v4n1a4.
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Introducción: la secuenciación genómica es una herramienta que permite identificar variantes del SARSCoV-2. La red de vigilancia genómica de Antioquia, viene trabajando en la caracterización de las variantes circulantes en el territorio, con el propósito de aportar evidencia científica a los tomadores de decisiones en el marco de la pandemia. El objetivo del presente trabajo es describir la situación epidemiológica de las variantes de SARSCoV-2 detectadas en Antioquia desde diciembre de 2020 a enero de 2022. Materiales y métodos: estudio descriptivo de corte transversal. Las muestras secuenciadas hicieron parte de los muestreos probabilísticos y rutinarios del Instituto Nacional de Salud (INS). Para la secuenciación se usó la plataforma de Oxford nanopor, además se emplearon las bases de datos del Sivigila y de reporte de casos COVID-19 del INS para los datos sociodemográficos y clínicos. La identificación de los linajes y score de calidad de las secuencias se llevó a cabo en Nextclade y Pangolin. Resultados: en Antioquia se identificaron variantes circulantes de SARS-CoV-2 en 2 675 muestras. Dentro de las variantes y/o linajes identificados los Delta, Mu y Gamma comprendieron la mayor proporción, aportando el 39 %, 27 % y 14 % respectivamente, sin embargo, la variante Ómicron desde su identificación (10 diciembre de 2021) presentó una amplia distribución en el departamento. Discusión: la determinación de los linajes ha permitido evidenciar la diversidad genética viral que circula en la región mostrando una prevalencia diferencial espacio-temporal con respecto al contexto nacional. La vigilancia genómica se fortalecerá con el objetivo de monitorear el comportamiento en virtud a variables sociodemográficas.
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Morales Granados, Miguel Alfonso, Edwin Gilberto Medina Bejarano, Jhoan Sebastián Jimenéz Rodríguez et Sidney Enrique Muños Pastrana. Caracterización, diseño, mejora y puesta en funcionamiento de tres estaciones didácticas de hidráulica y electrohidráulica para practicas académicas en la ETITC. Escuela Tecnológica Instituto Técnico Central, 2022. http://dx.doi.org/10.55411/2023.23.
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Este proyecto pretende analizar, rediseñar y optimizar los bancos didácticos hidráulicos para el laboratorio de fluidos del ETITC que no se encuentran prestando ningún uso actualmente y representa una inversión de la ETITC y de algunos estudiantes en sus proyectos de grado que se está desaprovechando, la metodología propuesta analizará las diferentes variables, elementos y componentes que caracterizan el estudio de la transmisión de potencia específicamente la hidráulica. Con el fin de rediseñar, mejorar y poner a punto los bancos ya existentes ETITC, Contribuyendo con el mejoramiento y desarrollo integral y estructurado de los estudiantes de las diferentes carreras de la ETITC. En el banco estarán dispuestos elementos comunes y básicos como son los actuadores, válvulas manuales, electroválvulas, válvulas de distribución, finales de carrera, entre otros, así como sus respectivas fuentes de energía (bomba hidráulica), se propone máxima versatilidad para los montajes propuestos de manera que sean adaptables para que los estudiantes tengan la posibilidad de diseñar diferentes circuitos o sistemas. De igual manera estos tendrán un manual de operación y mantenimiento y un manual de ejercicios que ayudarán al estudiante en el conocimiento y aplicación de cada uno de los elementos que ayudarán a fortalecer el proceso de enseñanza-aprendizaje. De aprobarse este proyecto se tomará como base los bancos hidráulicos ya existentes en la ETITC, se revisará el estado real de los mismos su estado y funcionalidad, en seguida se procederá al proceso de mantenimiento, que permita posteriormente rediseño, mejoramiento y puesta a punto de los mismos, finalmente se realizarán pruebas de funcionamiento para así reajustar y poner a punto todos los sistemas. La implementación del banco se basará en un sistema lo más simple y eficientemente posible dando un ambiente de calidad, eficiencia y flexibilidad en la operación para los usuarios.
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Vargas-Herrera, Hernando, Pamela Andrea Cardozo-Ortiz, Clara Lía Machado-Franco, Carlos Alberto Cadena-Silva, Freddy Hernán Cepeda-López, Aura María Ciceri-Lozano, Carlos Eduardo León-Rincón et al. Reporte de Sistemas de Pago - Junio de 2021. Banco de la República de Colombia, juillet 2021. http://dx.doi.org/10.32468/rept-sist-pag.2021.
Texte intégralRésumé :
El Banco de la República, con el Reporte de Sistemas de Pago, entrega un panorama completo de la infraestructura financiera local, siendo este un producto importante de la labor de seguimiento a dicha infraestructura. Las cifras contenidas en este reporte corresponden al año 2020, período de pandemia durante el cual las medidas de confinamiento para aliviar la tensión sobre el sistema de salud generaron para Colombia, al igual que en la mayoría de los países, una fuerte reducción de la actividad económica y el consumo. Desde el comienzo de la pandemia, la Junta Directiva del Banco de la República adoptó las decisiones necesarias para otorgar al mercado amplia liquidez en pesos y dólares, garantizar la estabilidad de los mercados, proteger el sistema de pagos y preservar la oferta de crédito. El pronunciado crecimiento de los agregados monetarios reflejó la mayor preferencia por liquidez, la cual fue atendida oportunamente por el Banco de la República. Las decisiones adoptadas se realizaron mediante diferentes operaciones, las cuales fueron compensadas y liquidadas en la infraestructura financiera. Después de la introducción, la segunda sección del presente reporte de pagos analiza la evolución y el desempeño de las diferentes infraestructuras financieras. Se destaca que el sistema de pagos de alto valor CUD registró en 2020 un mayor dinamismo que el año anterior, principalmente por el aumento de los depósitos remunerados que en promedio diario realizó la Dirección General de Crédito Público y del Tesoro Nacional (DGCPTN) con el Banco de República, así como una mayor actividad del mercado de simultáneas de deuda pública. Consecuentemente con el crecimiento de la actividad en el CUD, el Depósito Central de Valores (DCV) registró una mayor actividad por el aumento del mercado monetario de deuda pública y por las colocaciones por parte del Gobierno Nacional en el mercado primario. El valor de las operaciones compensadas y liquidadas por intermedio de la Cámara de Riesgo Central de Contraparte (CRCC) continúa creciendo, jalonado principalmente por los contratos non delivery forward (NDF) peso/dólar. Con respecto a la CRCC, es oportuno mencionar que a partir de finales del año pasado esta cámara se encarga de administrar los riesgos y de compensar y liquidar las operaciones del mercado de contado peso/dólar, debido a la fusión con la Cámara de Compensación de Divisas de Colombia (CCDC). Así mismo, a partir del último trimestre del año 2020 la CRCC se encarga de compensar y liquidar el mercado de renta variable, labor que venía desempeñando la Bolsa de Valores de Colombia (BVC). En la sección tres se entrega una visión integral de los pagos en el mercado de bienes y servicios, es decir, de las transacciones efectuadas en el circuito de personas naturales y empresas no financieras. Durante la pandemia las transferencias electrónicas inter e intrabancarias, que en su mayoría son originadas por empresas, registraron un incremento tanto en número como en valor de operaciones frente a 2019. Por su parte, los pagos con tarjetas débito y crédito originados principalmente por personas naturales mostraron un comportamiento decreciente con respecto a 2019. Los pagos realizados con cheques siguen disminuyendo, presentando una tendencia a la baja muy pronunciada en el último año. Como complemento a la información sobre transferencias electrónicas, el reporte incluye en esta sección un sombreado sobre la caracterización de la población con cuenta de ahorro y corriente, empleando los datos de la encuesta del Banco de la República sobre percepción de uso de los instrumentos de pago en 2019. Se incluye también un recuadro sobre la evolución transaccional de una billetera móvil provista por una sociedad especializada en depósitos y pagos electrónicos (Sedpe), mostrando que desde su creación a finales del año 2017 ha incremento en el número de usuarios y el valor de las transacciones, con especial velocidad durante la pandemia. Adicionalmente, se presenta un diagnóstico sobre los efectos de la pandemia en los patrones de pago de la población, fundamentado en datos sobre el uso del efectivo en circulación, sobre los pagos con instrumentos electrónicos, y sobre el consumo y la confianza del consumidor. Se concluye que el desplome en el índice de confianza del consumidor y la caída en el consumo privado dieron lugar a cambios en los patrones de pago de las personas. Las compras con tarjetas de crédito y débito disminuyeron, mientras que los pagos por bienes y servicios mediante transferencia electrónica aumentaron. Estos resultados, junto con el considerable aumento del efectivo en circulación, podrían proveer indicios a favor de un posible atesoramiento del papel moneda con motivo precaución por parte de las personas y de un mayor uso del efectivo como instrumento de pago. Se incluye, además, un recuadro que presenta los principales cambios que se introdujeron en la regulación del sistema de pagos de bajo valor en el país mediante la expedición del Decreto 1692 de diciembre de 2020. La cuarta sección se refiere a las importantes innovaciones y cambios tecnológicos que se han observado en el sistema de pagos al por menor. Se destacan cuatro temas en esta línea. El primero se constituye en un punto clave para la construcción de la infraestructura financiera de pagos inmediatos. Consiste en el diseño e implementación de los llamados esquemas superpuestos, los cuales son un desarrollo tecnológico que permite una comunicación abierta entre los diferentes agentes de la cadena de pagos, logrando una alta interoperabilidad entre diferentes proveedores de servicios de pago. El segundo tema explora los avances en el debate internacional sobre la emisión de moneda digital por parte de los bancos centrales (CBDC por su sigla en inglés), con el fin de entender su posible impacto en el sistema de pagos de bajo valor y en el uso del efectivo. El tercer tema está relacionado con nuevas formas de iniciación de pagos, tales como los códigos QR, la biometría o la tecnología de comunicación de campos cercanos (NCF por su sigla en inglés). Estos cambios, aparentemente pequeños, pueden tener efectos importantes en la experiencia del usuario con el sistema de pagos de bajo valor. El cuarto tema, finalmente, es el crecimiento de los pagos vinculados con la telefonía móvil y el internet. El reporte finaliza en la sección cinco con una reseña de dos trabajos de investigación aplicada realizados en el Banco de la República en el año 2020. El primero analiza el nivel patrimonial de la CRCC, reconociendo el rol relevante que esta infraestructura ha adquirido en la compensación y liquidación de varios mercados financieros en el país. Se exploran los requerimientos de capital para las entidades de contrapartida central establecidos en algunas jurisdicciones, se identifican los riesgos que se busca cubrir desde la perspectiva del servicio que este tipo de entidades ofrece al mercado y aquellos asociados a su actividad corporativa. Se analizan los niveles patrimoniales de la CRCC a partir de lo observado en la regulación de la Unión Europea y se concluye que la CRCC cuenta con un esquema de anillos de seguridad muy similar al observado en la experiencia internacional y que su nivel patrimonial es superior al exigido por la regulación colombiana, siendo suficiente para cubrir otros riesgos. El segundo trabajo de investigación identifica y cuantifica las fuentes que utilizan las entidades participantes en el CUD para cumplir con sus obligaciones diarias contraídas en el mercado financiero local, y con su uso como herramienta de monitoreo de la liquidez intradía en condiciones normales. Leonardo Villar Gómez Gerente General
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Payment Systems Report - June of 2020. Banco de la República de Colombia, février 2021. http://dx.doi.org/10.32468/rept-sist-pag.eng.2020.
Texte intégralRésumé :
With its annual Payment Systems Report, Banco de la República offers a complete overview of the infrastructure of Colombia’s financial market. Each edition of the report has four objectives: 1) to publicize a consolidated account of how the figures for payment infrastructures have evolved with respect to both financial assets and goods and services; 2) to summarize the issues that are being debated internationally and are of interest to the industry that provides payment clearing and settlement services; 3) to offer the public an explanation of the ideas and concepts behind retail-value payment processes and the trends in retail payments within the circuit of individuals and companies; and 4) to familiarize the public, the industry, and all other financial authorities with the methodological progress that has been achieved through applied research to analyze the stability of payment systems. This edition introduces changes that have been made in the structure of the report, which are intended to make it easier and more enjoyable to read. The initial sections in this edition, which is the eleventh, contain an analysis of the statistics on the evolution and performance of financial market infrastructures. These are understood as multilateral systems wherein the participating entities clear, settle and register payments, securities, derivatives and other financial assets. The large-value payment system (CUD) saw less momentum in 2019 than it did the year before, mainly because of a decline in the amount of secondary market operations for government bonds, both in cash and sell/buy-backs, which was offset by an increase in operations with collective investment funds (CIFs) and Banco de la República’s operations to increase the money supply (repos). Consequently, the Central Securities Depository (DCV) registered less activity, due to fewer negotiations on the secondary market for public debt. This trend was also observed in the private debt market, as evidenced by the decline in the average amounts cleared and settled through the Central Securities Depository of Colombia (Deceval) and in the value of operations with financial derivatives cleared and settled through the Central Counterparty of Colombia (CRCC). Section three offers a comprehensive look at the market for retail-value payments; that is, transactions made by individuals and companies. During 2019, electronic transfers increased, and payments made with debit and credit cards continued to trend upward. In contrast, payments by check continued to decline, although the average daily value was almost four times the value of debit and credit card purchases. The same section contains the results of the fourth survey on how the use of retail-value payment instruments (for usual payments) is perceived. Conducted at the end of 2019, the main purpose of the survey was to identify the availability of these payment instruments, the public’s preferences for them, and their acceptance by merchants. It is worth noting that cash continues to be the instrument most used by the population for usual monthly payments (88.1% with respect to the number of payments and 87.4% in value). However, its use in terms of value has declined, having registered 89.6% in the 2017 survey. In turn, the level of acceptance by merchants of payment instruments other than cash is 14.1% for debit cards, 13.4% for credit cards, 8.2% for electronic transfers of funds and 1.8% for checks. The main reason for the use of cash is the absence of point-of-sale terminals at commercial establishments. Considering that the retail-payment market worldwide is influenced by constant innovation in payment services, by the modernization of clearing and settlement systems, and by the efforts of regulators to redefine the payment industry for the future, these trends are addressed in the fourth section of the report. There is an account of how innovations in technology-based financial payment services have developed, and it shows that while this topic is not new, it has evolved, particularly in terms of origin and vocation. One of the boxes that accompanies the fourth section deals with certain payment aspects of open banking and international experience in that regard, which has given the customers of a financial entity sovereignty over their data, allowing them, under transparent and secure conditions, to authorize a third party, other than their financial entity, to request information on their accounts with financial entities, thus enabling the third party to offer various financial services or initiate payments. Innovation also has sparked interest among international organizations, central banks, and research groups concerning the creation of digital currencies. Accordingly, the last box deals with the recent international debate on issuance of central bank digital currencies. In terms of the methodological progress that has been made, it is important to underscore the work that has been done on the role of central counterparties (CCPs) in mitigating liquidity and counterparty risk. The fifth section of the report offers an explanation of a document in which the work of CCPs in financial markets is analyzed and corroborated through an exercise that was built around the Central Counterparty of Colombia (CRCC) in the Colombian market for non-delivery peso-dollar forward exchange transactions, using the methodology of network topology. The results provide empirical support for the different theoretical models developed to study the effect of CCPs on financial markets. Finally, the results of research using artificial intelligence with information from the large-value payment system are presented. Based on the payments made among financial institutions in the large-value payment system, a methodology is used to compare different payment networks, as well as to determine which ones can be considered abnormal. The methodology shows signs that indicate when a network moves away from its historical trend, so it can be studied and monitored. A methodology similar to the one applied to classify images is used to make this comparison, the idea being to extract the main characteristics of the networks and use them as a parameter for comparison. Juan José Echavarría Governor
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Payment Systems Report - June of 2021. Banco de la República, février 2022. http://dx.doi.org/10.32468/rept-sist-pag.eng.2021.
Texte intégralRésumé :
Banco de la República provides a comprehensive overview of Colombia’s finan¬cial infrastructure in its Payment Systems Report, which is an important product of the work it does to oversee that infrastructure. The figures published in this edition of the report are for the year 2020, a pandemic period in which the con¬tainment measures designed and adopted to alleviate the strain on the health system led to a sharp reduction in economic activity and consumption in Colom¬bia, as was the case in most countries. At the start of the pandemic, the Board of Directors of Banco de la República adopted decisions that were necessary to supply the market with ample liquid¬ity in pesos and US dollars to guarantee market stability, protect the payment system and preserve the supply of credit. The pronounced growth in mone¬tary aggregates reflected an increased preference for liquidity, which Banco de la República addressed at the right time. These decisions were implemented through operations that were cleared and settled via the financial infrastructure. The second section of this report, following the introduction, offers an analysis of how the various financial infrastructures in Colombia have evolved and per¬formed. One of the highlights is the large-value payment system (CUD), which registered more momentum in 2020 than during the previous year, mainly be¬cause of an increase in average daily remunerated deposits made with Banco de la República by the General Directorate of Public Credit and the National Treasury (DGCPTN), as well as more activity in the sell/buy-back market with sovereign debt. Consequently, with more activity in the CUD, the Central Securi¬ties Depository (DCV) experienced an added impetus sparked by an increase in the money market for bonds and securities placed on the primary market by the national government. The value of operations cleared and settled through the Colombian Central Counterparty (CRCC) continues to grow, propelled largely by peso/dollar non-deliverable forward (NDF) contracts. With respect to the CRCC, it is important to note this clearing house has been in charge of managing risks and clearing and settling operations in the peso/dollar spot market since the end of last year, following its merger with the Foreign Exchange Clearing House of Colombia (CCDC). Since the final quarter of 2020, the CRCC has also been re¬sponsible for clearing and settlement in the equities market, which was former¬ly done by the Colombian Stock Exchange (BVC). The third section of this report provides an all-inclusive view of payments in the market for goods and services; namely, transactions carried out by members of the public and non-financial institutions. During the pandemic, inter- and intra-bank electronic funds transfers, which originate mostly with companies, increased in both the number and value of transactions with respect to 2019. However, debit and credit card payments, which are made largely by private citizens, declined compared to 2019. The incidence of payment by check contin¬ue to drop, exhibiting quite a pronounced downward trend during the past last year. To supplement to the information on electronic funds transfers, section three includes a segment (Box 4) characterizing the population with savings and checking accounts, based on data from a survey by Banco de la República con-cerning the perception of the use of payment instruments in 2019. There also is segment (Box 2) on the growth in transactions with a mobile wallet provided by a company specialized in electronic deposits and payments (Sedpe). It shows the number of users and the value of their transactions have increased since the wallet was introduced in late 2017, particularly during the pandemic. In addition, there is a diagnosis of the effects of the pandemic on the payment patterns of the population, based on data related to the use of cash in circu¬lation, payments with electronic instruments, and consumption and consumer confidence. The conclusion is that the collapse in the consumer confidence in¬dex and the drop in private consumption led to changes in the public’s pay¬ment patterns. Credit and debit card purchases were down, while payments for goods and services through electronic funds transfers increased. These findings, coupled with the considerable increase in cash in circulation, might indicate a possible precautionary cash hoarding by individuals and more use of cash as a payment instrument. There is also a segment (in Focus 3) on the major changes introduced in regulations on the retail-value payment system in Colombia, as provided for in Decree 1692 of December 2020. The fourth section of this report refers to the important innovations and tech¬nological changes that have occurred in the retail-value payment system. Four themes are highlighted in this respect. The first is a key point in building the financial infrastructure for instant payments. It involves of the design and im¬plementation of overlay schemes, a technological development that allows the various participants in the payment chain to communicate openly. The result is a high degree of interoperability among the different payment service providers. The second topic explores developments in the international debate on central bank digital currency (CBDC). The purpose is to understand how it could impact the retail-value payment system and the use of cash if it were to be issued. The third topic is related to new forms of payment initiation, such as QR codes, bio¬metrics or near field communication (NFC) technology. These seemingly small changes can have a major impact on the user’s experience with the retail-value payment system. The fourth theme is the growth in payments via mobile tele¬phone and the internet. The report ends in section five with a review of two papers on applied research done at Banco de la República in 2020. The first analyzes the extent of the CRCC’s capital, acknowledging the relevant role this infrastructure has acquired in pro¬viding clearing and settlement services for various financial markets in Colom¬bia. The capital requirements defined for central counterparties in some jurisdic¬tions are explored, and the risks to be hedged are identified from the standpoint of the service these type of institutions offer to the market and those associated with their corporate activity. The CRCC’s capital levels are analyzed in light of what has been observed in the European Union’s regulations, and the conclusion is that the CRCC has a scheme of security rings very similar to those applied internationally and the extent of its capital exceeds what is stipulated in Colombian regulations, being sufficient to hedge other risks. The second study presents an algorithm used to identify and quantify the liquidity sources that CUD’s participants use under normal conditions to meet their daily obligations in the local financial market. This algorithm can be used as a tool to monitor intraday liquidity. Leonardo Villar Gómez Governor