Littérature scientifique sur le sujet « Injection-Locked Oscillator (ILO) »

In Self Oscillating systems, locking of the oscillators can take place for injected signals close in frequency to nth harmonics of the free-running frequency. In this paper, we present a simple design for digital phase shift control by using a harmonically injection locked oscillator (ILO) of 35MHz frequency. Phase shifters at high frequencies are essential in many communication system applications such as frequency synthesis, quadrature signal generation and phase locked loops (PLLs).

In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28 nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors enables the creation of a Quadrature Ring Oscillator (QRO) reducing both size and power consumption compared to an LC tank oscillator. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we propose a low-power ILCDR with fast locking time and low jitter for burst-mode applications. The main novelty consists of the implementation of a complementary QRO based on back-gate control using FDSOI technology to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (PRBS7) at 868 Mbps, the recovered clock jitter is 26.7 ps (2.3% UIp-p) and the recovered data jitter is 11.9 ps (1% UIp-p). With a 0.6 V power supply, the power consumption is 318μW. All the results presented here are based on post-layout simulations, as no prototypes have been produced. Similarly, we can estimate the surface area of the chip (without the pad ring) at around 6600 μm2.

This paper presents a duty cycle-based, dual-mode simultaneous wireless information and power transceiver (SWIPT) for Internet of Things (IoT) devices in which a sensor node monitors the received power and adaptively controls the single-tone or multitone communication mode. An adaptive power-splitting (PS) ratio control scheme distributes the received radio frequency (RF) energy between the energy harvesting (EH) path and the information decoding (ID) path. The proposed SWIPT enables the self-powering of an ID transceiver above 20 dBm input power, leading to a battery-free network. The optimized PS ratio of 0.44 enables it to provide sufficient harvested energy for self-powering and energy-neutral operation of the ID transceiver. The ID transceiver can demodulate the amplitude-shift keying (ASK) and the binary phase-shift keying (BPSK) signals. Moreover, for low-input power level, a peak-to-average power ratio (PAPR) scheme based on multitone is also proposed for demodulation of the information-carrying RF signals. Due to the limited power, information is transmitted in uplink by backscatter modulation instead of RF signaling. To validate our proposed SWIPT architecture, a SWIPT printed circuit board (PCB) was designed with a multitone SWIPT board at 900 MHz. The demodulation of multitone by PAPR was verified separately on the PCB. Results showed the measured sensitivity of the SWIPT to be −7 dBm, and the measured peak power efficiency of the RF energy harvester was 69% at 20 dBm input power level. The power consumption of the injection-locked oscillator (ILO)-based phase detection path was 13.6 mW, and it could be supplied from the EH path when the input power level was high. The ID path could demodulate 4-ASK- and BPSK-modulated signals at the same time, thus receiving 3 bits from the demodulation process. Maximum data rate of 4 Mbps was achieved in the measurement.

Les systèmes modernes de communication de données s'appuient fortement sur des techniques de transmission synchrone pour optimiser la largeur de bande et minimiser la consommation d'énergie. Dans ces systèmes, seul le signal de données est transmis, ce qui nécessite la mise en œuvre de circuits de récupération d'horloge et de données (CDR) au niveau du récepteur. Cette thèse explore la nouvelle application de la technologie Fully-Depleted Silicon-On-Insulator (FDSOI) 28 nm pour améliorer les performances des circuits CDR en atténuant les effets de canaux courts grâce à des structures de transistors innovantes.L'une des contributions de cette thèse est le développement d'un circuit à résistance négative utilisant la grille arrière du transistor FDSOI. Ce circuit utilise un miroir de courant contrôlé par la grille arrière pour créer un oscillateur LC à résistance négative. En parallèle, ce travail présente l'implémentation de deux types d'oscillateurs : un oscillateur en anneau complémentaire et un oscillateur en anneau rapide. L'oscillateur en anneau complémentaire capitalise sur les inverseurs complémentaires, offrant un retour de biais automatique par le contrôle de la grille arrière, améliorant ainsi ses performances. L'oscillateur en anneau rapide utilise quant à lui des inverseurs rapides en combinaison avec des inverseurs complémentaires conçus pour minimiser les délais de propagation. La thèse présente une analyse comparative détaillée de ces oscillateurs, mettant en évidence leurs points forts et leurs limites. En outre, nous introduisons un signal d'injection dans l'oscillateur en anneau, ce qui permet de créer un oscillateur verrouillé par injection (ILO) à faible jitter. Cet oscillateur présente des caractéristiques de performance remarquables, notamment en ce qui concerne la réduction du bruit de phase et l'amélioration de la stabilité de la fréquence. Tirant parti des bonnes performances de l'ILO, nous proposons une nouvelle récupération d'horloge et de données verrouillée par injection (ILCDR) à faible coût et à faible consommation d'énergie, avec un temps de verrouillage rapide et une bonne jitter pour les applications en mode burst.Pour valider les conceptions proposées et leurs performances à différentes fréquences opérationnelles, des simulations approfondies ont été réalisées à l'aide de Cadence Virtuoso à 868 MHz et 2.4 GHz. En outre, la conception de layout et la simulation post layout de l'ILCDR basé sur l'oscillateur en anneau complémentaire sont également étudiées
Modern data communication systems heavily rely on synchronous transmission techniques to optimize bandwidth and minimize power consumption. In such systems, only the data signal is transmitted, necessitating the implementation of Clock and Data Recovery (CDR) circuits at the receiver end. This thesis explores the novel application of Fully-Depleted Silicon-On-Insulator (FDSOI) 28nm technology to enhance the performance of CDR circuits by mitigating short-channel effects through innovative transistor structures.One contribution of this thesis is the development of a negative resistance circuit using the back gate of the FDSOI transistor. This circuit employs a current mirror controlled by the back gate to create a negative resistance LC oscillator. In parallel, this work presents the implementation of two types of oscillators: a complementary ring oscillator and a fast ring oscillator. The complementary ring oscillator capitalizes on complementary inverters, offering automatic bias feedback by the back gate control, thereby enhancing its performance. Meanwhile, the fast ring oscillator uses fast inverters in combination with complementary inverters designed to minimize propagation delays. The thesis presents a detailed comparative analysis of these oscillators, highlighting their individual strengths and limitations. Furthermore, we introduce an injection signal into the ring oscillator, resulting in the creation of a low-jitter Injection-Locked Oscillator (ILO). This ILO exhibits remarkable performance characteristics, particularly in reducing phase noise and enhancing frequency stability. Taking advantage of the good performance of the ILO, we propose a novel low-cost and low-power Injection-Locked Clock and Data Recovery (ILCDR) with a fast-locking time and good jitter for burst-mode applications.To validate the proposed designs and their performance at different operational frequencies, extensive simulations have been carried out using Cadence Virtuoso at 868 MHz and 2.4 GHz. In addition, the layout design and post layout simulation of the ILCDR based on the complementary ring oscillator are also studied

by Chiu, Shek Fai.
Thesis (M.Phil.)--Chinese University of Hong Kong, 1995.
Includes bibliographical references (leaves [121]-[125]).
DEDICATION
ACKNOWLEDGE
ABSTRACT
Chapter Chapter 1 --- Introduction --- p.1-1
Chapter Chapter 2 --- Background --- p.2-1
Chapter 2.1 --- Basic Oscillator --- p.2-2
Chapter 2.1.1 --- Introduction --- p.2-2
Chapter 2.1.2 --- The basic feedback oscillator --- p.2-2
Chapter 2.1.3 --- The basic negative resistance oscillator --- p.2-3
Chapter 2.1.4 --- Implementation of an oscillator --- p.2-3
Chapter 2.1.5 --- The phase noise of an oscillator --- p.2-4
Chapter a) --- Lesson's model --- p.2-4
Chapter 2.2 --- Basic Mixer --- p.2-6
Chapter 2.2.1 --- Introduction --- p.2-6
Chapter 2.2.2 --- Non-linear resistance mixer --- p.2-6
Chapter 2.2.3 --- Y-parameter representation --- p.2-7
Chapter 2.2.4 --- Figure of merit --- p.2-9
Chapter 2.3 --- Negative Resistance Amplifier --- p.2-11
Chapter 2.3.1 --- Introdutction --- p.2-12
Chapter 2.3.2 --- Type of reflection amplifier --- p.2-12
Chapter 2.3.3 --- The noise figure --- p.2-13
Chapter 2.4 --- Fundamental Injection-locked Oscillator --- p.2-15
Chapter 2.4.1 --- Introduction --- p.2-15
Chapter 2.4.2 --- Injection-locked oscillator --- p.2-15
Chapter 2.4.3. --- Locking range --- p.2-15
Chapter 2.4.4 --- Noise behaviour --- p.2-16
Chapter 2.4.5 --- Applications of ILO --- p.2-17
Chapter 2.5 --- Quasi-static analysis --- p.2-18
Chapter 2.5.1 --- Introduction --- p.2-18
Chapter 2.5.2 --- free running oscillation --- p.2-18
Chapter 2.5.3 --- Conditions for injection locking --- p.2-22
Chapter a) --- Stability --- p.2-24
Chapter 2.5.4 --- Conditions for Two signal injection --- p.2-25
Chapter a) --- Stability --- p.2-26
Chapter Chapter 3 --- Frequency conversion of Injection-locked oscillator --- p.3-1
Chapter 3.1 --- Circuit Description --- p.3 -2
Chapter 3.1.1 --- One port equivalent circuit --- p.3-5
Chapter 3.1.2 --- Two port equivalent circuit --- p.3-6
Chapter 3.2 --- Injection Control Resistance --- p.3-7
Chapter 3.2.1 --- Introduction --- p.3-7
Chapter 3.2.2 --- Measurement Setup --- p.3-8
Chapter 3.2.3 --- Measurement and Experimental results --- p.3-9
Chapter 3.2.4 --- Discussion --- p.3-11
Chapter 3.2.5 --- Conclusion --- p.3-11
Chapter 3.3 --- Q Multiplication --- p.3-12
Chapter 3.3.1 --- Introduction --- p.3-12
Chapter 3.3.1 --- Measurement setup of reflection gain/loss --- p.3-16
Chapter a) --- Theory of measurement --- p.3-16
Chapter 3.3.3 --- Measurement and Experiment results --- p.3-17
Chapter 3.3.4 --- Discussion --- p.3-17
Chapter 3.3.5 --- Conclusion --- p.3-19
Chapter 3.4 --- Impedance Conversion --- p.3-20
Chapter 3.4.1 --- Introduction --- p.3-20
Chapter 3.4.2 --- Measurement and Experimental results --- p.3-22
Chapter 3.4.3 --- Discussion --- p.3-26
Chapter 3.4.5 --- Conclusion --- p.3-26
Chapter 3.5 --- Negative Resistance amplification --- p.3-27
Chapter 3.5.1 --- Introduction --- p.3-27
Chapter a) --- Small signal response --- p.3-27
Chapter 3.5.2 --- Measurement and Experimental Results --- p.3-31
Chapter 3.5.3 --- Discussion --- p.3-32
Chapter 3.5.4 --- Conclusion --- p.3-35
Chapter 3.6 --- Frequency Conversion and Noise performance --- p.3-36
Chapter 3.6.1 --- Frequency Conversion --- p.3-36
Chapter 3.6.2 --- Noise performance --- p.3-37
Chapter 3.6.3 --- Measurement setup --- p.3-41
Chapter 3.6.4 --- Measurement and Experimental results --- p.3-43
Chapter a) --- Results of the sensitivity measurement --- p.3-43
Chapter b) --- Results of 3 dB operation bandwidth measurement --- p.3-44
Chapter c) --- Results of the testing setup in figure 3.6.2 --- p.3-44
Chapter 3.6.5 --- Discussion --- p.3-46
Chapter 3.6.6 --- Conclusion --- p.3-48
Chapter 3.7 --- Large Signal Response --- p.3-49
Chapter 3.7.1 --- Introduction --- p.3-49
Chapter 3.7.2 --- Measurement and Experimental results --- p.3-51
Chapter a) --- The reflection characteristics of ILO at high RF signal level
Chapter a1) --- Gain bandwidth characteristics --- p.3-51
Chapter a2) --- Gain compression characteristics --- p.3-52
Chapter b) --- The reflection characteristics of ILO at high IF signal level
Chapter b1) --- Gain bandwidth characteristics --- p.3-54
Chapter b2) --- Gain compression characteristics --- p.3-55
Chapter c) --- The conversion properties of ILO
Chapter c1) --- Gain compression characteristics --- p.3-57
Chapter 3.7.3 --- Discussion --- p.3-60
Chapter 3.7.4 --- Conclusion --- p.3-61
Chapter 3.8 --- Image Signal Response --- p.3-62
Chapter 3.8.1 --- Introduction --- p.3-62
Chapter 3.8.2 --- Measurement and Experimental results --- p.3-63
Chapter 3.8.3 --- Discussion --- p.3-65
Chapter 3.8.4 --- Conclusion --- p.3-66
Chapter 3.9 --- Conclusion --- p.3-67
Chapter Chapter 4 --- ILO Regenerative Mixer --- p.4-1
Chapter 4.1 --- Introduction --- p.4-1
Chapter 4.2 --- Block diagram representation --- p.4-1
Chapter 4.3 --- Linear Regenerative Mixer Model --- p.4-2
Chapter 4.3.1 --- Y-parameter representation --- p.4-2
Chapter 4.3.2 --- Stability --- p.4-4
Chapter 4.3.3 --- Linear circuit model --- p.4-5
Chapter 4.4 --- Design Example and Circuit Description --- p.4-6
Chapter 4.5 --- Measurement Results --- p.4-8
Chapter 4.6 --- Conclusion --- p.4-11
Chapter Chapter 5 --- Conclusion --- p.5-1
REFERENCE --- p.R-1