Littérature scientifique sur le sujet « HV-CMOS design »

ABSTRACTA model of a High Voltage CMOS (HV-CMOS) Monolithic Active Pixel Sensor (MAPS) has been modelled using Technology Computer Aided Design (TCAD). The model has incorporated both the active region and the on-pixel readout circuits which were comprised of a source follower amplifier and an integrated charge amplifier. The simulation has examined the electrical characteristics and response output of a HV-CMOS MAPS sensor using typical dimensions, levels of doping in the structural layers and bias conditions for this sensor. The performance of two alternate designs of amplifier have been examined as a function of the operating parameters. The response of the sensor to the incidence of Minimum Ionizing Particles (MIPs) at different energies has been included in the model.

Abstract This paper presents the design and preliminary results of a shunt voltage regulator and two different bandgap reference designs for use with a monolithic High Voltage CMOS (HV-CMOS) sensor in a 150 nm technology node. One bandgap reference design is based on Bipolar Junction Transistors (BJTs) as the reference element of the circuit — the rest of the circuit is entirely designed with Metal–Oxide–Semiconductor Field-Effect Transistors (MOSFETs). The second bandgap reference design makes use of MOSFETs exclusively.

Abstract This article details the design of a silicon based polarimeter for use in a prototype storage ring for proton EDM (Electric Dipole Moment) studies. The polarimeter consists of layers of LGAD (Low Gain Avalanche Diode) sensors for a low material budget, time-of-flight measurement and complemented with HV-CMOS (High Voltage CMOS) sensors for accurate scattering angle measurement and tracking. This design has the objective to optimize the polarization measurement of protons with energy 30–45 MeV. Simulations show that the excellent time resolution of LGAD sensors provides a sufficient energy resolution to meet the experiment specifications. HV-CMOS sensors are included to provide complementary spatial resolution with minimal additional material budget. The simulations show that the detector configuration is capable of measuring the scattering angle of a proton scattered off a carbon target to just a few hundredths of a degree. The time-of-flight measurement performance is demonstrated with lab experiments using electrons from a Sr90 source.

The RD50-CMOS group aims to design and study High Voltage CMOS (HV-CMOS) chips for use in a high radiation environment. Currently, measurements are performed on RD50-MPW2 chip, the second prototype developed by this group. The active matrix of the prototype consists of 8x8 pixels with analog front end. Details of the analog front end and simulations have been already published earlier. This contribution focuses on the Caribou based readout system of the active matrix. Each pixel of the active matrix can be readout one after the other. Relevant aspects of hardware, firmware and software are introduced. As a first stage, firmware for a standalone setup is introduced and details on data flow are given. Afterwards, a second stage of the firmware capable of synchronizing with other detectors and accepting triggers is presented, focusing on operation of the chip in combination with a tracking telescope to measure efficiency and residuals.

Abstract HV-MAPS are a novel type of CMOS depleted active pixel sensors for ionizing particles, implemented in standard CMOS processes, that have been proposed in several future particle physics experiments for particle tracking. In depleted monolithic sensors, the sensor element is the n-well/p-substrate diode. The sensor matrix and the readout are integrated in one single piece of silicon and the electronics is embedded in shallow wells inside deep n-wells, isolated from the substrate. High voltage biasing increases the depth of the depletion region, improving sensor properties as signal amplitude, charge collection speed and radiation tolerance. ATLASPix3 is the first full reticle size high voltage Monolithic Active Pixel CMOS sensor, designed to meet the specifications of the outer layers of the ATLAS inner tracker (ITk). Its thin design, the excellent position resolution, high readout rate and high radiation tolerance make ATLASPix3 an ideal candidate for large-area tracking detector R&D of future collider experiments such as the Circular Electron Positron Collider (CEPC) silicon tracker.

This work presents a bandgap voltage reference (BGR) integrated in 0.25-μm bipolar-CMOS-DMOS (BCD) technology. The BGR circuit generates a reference voltage of 1.22 V. It is able to withstand large supply voltage variations of vehicle applications from 4.5 V, e.g., in case of cranking, up to 60-V, maximum value in case of emerging 48-V battery systems for hybrid and electrical vehicles. The circuit has an embedded high-voltage (HV) pseudo-regulator block that provides a more stable internal supply rail for a cascaded low-voltage bandgap core. HV MOS are used only in the pre-regulator block thus allowing the design of a BGR with compact size. The proposed architecture permits to withstand large input voltage variations with a temperature drift of a hundred of ppm/°C, a line regulation (LR) of few mV/V versus the external supply voltage and a power supply rejection ratio (PSRR) higher than 90 dB.

This paper presents an ultrasound transceiver application-specific integrated circuit (ASIC) directly integrated with an array of 12 × 80 piezoelectric transducer elements to enable next-generation ultrasound probes for 3D carotid artery imaging. The ASIC, implemented in a 0.18 µm high-voltage Bipolar-CMOS-DMOS (HV BCD) process, adopted a programmable switch matrix that allowed selected transducer elements in each row to be connected to a transmit and receive channel of an imaging system. This made the probe operate like an electronically translatable linear array, allowing large-aperture matrix arrays to be interfaced with a manageable number of system channels. This paper presents a second-generation ASIC that employed an improved switch design to minimize clock feedthrough and charge-injection effects of high-voltage metal–oxide–semiconductor field-effect transistors (HV MOSFETs), which in the first-generation ASIC caused parasitic transmissions and associated imaging artifacts. The proposed switch controller, implemented with cascaded non-overlapping clock generators, generated control signals with improved timing to mitigate the effects of these non-idealities. Both simulation results and electrical measurements showed a 20 dB reduction of the switching artifacts. In addition, an acoustic pulse-echo measurement successfully demonstrated a 20 dB reduction of imaging artifacts.

Le ultime novita in ambito automotive sono dovute principalmente ai compoenenti elettronici ed elettrici che favoriscono la riduzione dei livelli di emissione e creano maggiore sicurezza e comfort. L’utilizzo di questi componenti sta aumentando sempre di più, ed essendo generalmente connessi tramite dei bus, stanno rendendo il sistema di cablaggio sempre piu complesso fino a renderlo uno dei blocchi piu critici da progettare. Pertanto, si stanno cercando nuove tecniche per ridurre il numero di interconnessioni. In questo lavoro si analizza un nuovo metodo per integrare la comunicazione e l'alimentazione su un unico bus differenziale. Diversamente dai metodi Power over Ethernet (PoE), l'implementazione proposta si basa sull’iniezione di cariche ben definite sul bus di comunicazione, che allo stesso tempo alimenta i vari dispositivi, al fine di generare dei pulsi. Sono proposti due approcci basati su capacità di commutazione: il Charge Alternation (CA) e il Charge Pump (CP). Il metodo CA, a 2Mbps, richiede solo il 50% della potenza di modulazione del carico resistivo, e il CP migliora ancora di più le prestazioni grazie alla capacità di riutilizzare parzialmente la carica immagazinata. Entrambe i circuiti di transmissione sono validati da una scheda dimostrativa e da un test chip in tecnologia 180nm BCD-on-SOI da cui si sono ottenuti risultati eccellenti. Inoltre, un circuito di ricezione é mostrato ed implementato in un test chip che quindi realizza un ricetrasmettitore completo. La tesi é organizzata come segue: l'introduzione e le motivazioni alla base di questa attivitá sono mostrate nel Capitolo 1. Nel capitolo 2 sono analizzati il concetto basico di transmissione e la modellazione del bus differenziale. Il Capitolo 3 sono esaminate entrambe le implementazioni di trasmettitori proposti, andando nel dettaglio della caratteristica dei pulsi, della codifica e del consumo energetico. Una scheda dimostrativa fatta di componenti discreti e i relativi test sono presentati nel capitolo 4, rimpiazzando con successo un layer fisico di un applicazione simil-CAN per illuminazione interna delle auto. Vengono mostrati anche i risultati sulle emissioni elettromagnetiche che sono in linea con i requisiti standard. L'implentazione in silicio del trasmettitore, includendo entrambi circuiti sviluppati, é descritta dettagliatamente nel capitolo 5. Viene mostrata l’architettura degli switch ad alta tensione, la protezione ESD che fornisce un livello di HBM > 8kV e tutti i blocchi necessari per il funzionamento del chip. Alla fine dello stesso capitolo vengono mostrate le prestazioni del chip integrato. Nel Capitolo 6 si propone il circuito di ricezione e il composizione del chip che implementa il ricetrasmettitore completo in una struttura simile a quella precedente. I test top level del chip sono quindi esplicati prima di trarre le conclusioni finali.
The advancements in modern vehicles are mainly due to electrical and electronic components that support an increasing demand for lower emission levels, higher safety and comfort. Increasingly, these components are connected by bus systems, which lead to more complex wire harnesses in modern cars, than ever before. Because of this, the wire harness of a car became one of the most complex building blocks. Therefore, techniques to reduce the wiring overhead are becoming increasingly important. In this work, a new method for integrating the communication and power supply of network participants on one differential bus, is investigated. Different to methods such as Power over Ethernet (PoE), the proposed implementations are using charges to emit defined pulses in to the communication bus, that is also carrying the power supply. Two switched capacitor approaches are proposed, the charge alternation (CA) and the charge pump (CP) method. While the suggested CA mode, operating at 2, requires only 50% of the power of a resistive load modulation that reaches a comparable signal level, the CP mode improves this even further due to the inherent charge-reuse capability of the concept. The approaches are verified with a demonstrator and a transmitter test chip fabricated in a 180nm BCD-on-SOI technology, that both shows the excellent performance of the concept and the silicon implementation. Furthermore, the receiver is discussed and implemented as part of a transceiver test chip, fabricated in the same technology. The reminder of the work is organized as follows: After the introduction and motivation for this research project in chapter 1, basic transmission concepts are described as well as the modelling of the differential bus based on a twisted pair, is analysed in chapter 2. Chapter 3 examines both switched capacitor transmission concepts in detail, regarding pulse shape, encoding, and power consumption. To check the proposed transmission schemes in a real-world environment, a demonstrator using off-the-shelf components will be discussed and evaluated in chapter 4, that successfully replaces the existing physical layer of a CAN-like state-of-the-art application for interior car illumination. It shows also, that standards for electromagnetic emissions can be met with the proposed solutions. A silicon implementation for the transmitter part, realizing both methods, is described in detail in chapter 5. The architecture of the required high-voltage switches, the design of the ESD protection that withstand an HBM stress level > 8 and all necessary building blocks for a chip implementation that can work in a real network environment, are discussed. At the end of this chapter, the performance of the real silicon results are discussed. Chapter 6 proposes the receiver concept, and the transceiver chip level implementation using the same framework as developed with the transmitter test chip. The top-level verification of the build transceiver test chip is presented before conclusions are drawn.

This thesis addresses the potential of implementing watt-level class-AB Power Amplifier (PA) for WLAN in 65 nm CMOS technology, at 2.4 GHz frequency. In total, five PAs have been compared, where the examined parameters were output power (Pout), linearity, power added efficiency (PAE), and area consumption. Four PAs were implemented using conventional cascode topology with different combination of transistors sizes in 65nm CMOS, and one PA using a high-voltage Extended Drain MOS (EDMOS) device, implemented in the same 65 nm CMOS with no process or mask changes. All schematics were created using Cadence Virtuoso CAD tools. The test benches were created using the Agilent's Advance Design System ( ADS) and simulated with the ADS-Cadence dynamic link. The simulation results show that the EDMOS PA (L=350 nm) has the smallest area, but has harder to reach the required Pout. Cascode no. 3 (L= 500,260 nm) has the best Pout (29.1 dBm) and PAE (49.5 %). Cascode no. 2 (L= 500,350 nm) has the best linearity (low EVM). Cascode no. 1 (L=500,500 nm) has low Pout (27.7 dBm). Cascode no.4 (L=500,60 nm) has very bad linearity. The thesis also gives an overview for CMOS technology, discusses the most important aspects in RF PAs design, such as Pout, PAE, gain, and matching networks. Different PA classes are also discussed in this thesis.