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Articles de revues sur le sujet « HIGH GAIN LOW POWER »

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Auteur : Grafiati

Publié le 11 septembre 2023

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1

Astolfi, Daniele, Lorenzo Marconi, Laurent Praly et Andrew R. Teel. « Low-power peaking-free high-gain observers ». Automatica 98 (décembre 2018) : 169–79. http://dx.doi.org/10.1016/j.automatica.2018.09.009.

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2

Jain, Archita, et Anshu Gupta. « Low Power and High Gain Operational Transconductance Amplifier ». International Journal of Computer Applications 144, n^o 5 (17 juin 2016) : 30–33. http://dx.doi.org/10.5120/ijca2016910278.

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3

Durgam, Rajesh, S. Tamil et Nikhil Raj. « Design of Low Voltage Low Power High Gain Operational Transconductance Amplifier ». U.Porto Journal of Engineering 7, n^o 4 (26 novembre 2021) : 103–10. http://dx.doi.org/10.24840/2183-6493_007.004_0008.

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In this paper, a high gain structure of operational transconductance amplifier is presented. For low voltage operation with improved frequency response bulk driven quasi-floating gate MOSFET is used at the input. Further for achieving high gain the modified self cascode structure is used at the output. Compared to conventional self cascode the modified self cascode structure used provides higher transconductance which helps in significant boosting of gain of the amplifier. The modification is achieved by employing quasi-floating gate transistor which helps in scaling of the threshold which as a result increases the drain-to-source voltage of linear mode transistor thus changing it to saturation. This change of mode boosts the effective transconductance of self cascode MOSFET. The proposed operational transconductance amplifier when compared to its conventional showed improvement in DC gain by 30dB and also the unity gain bandwidth increases by 6 fold. The MOS models used for amplifier design are of 0.18µm CMOS technology at supply of 0.5V.

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4

Wei, Binbin, et Jinguang Jiang. « A low power high gain gain-controlled LNA + mixer for GNSS receivers ». Journal of Semiconductors 34, n^o 11 (novembre 2013) : 115002. http://dx.doi.org/10.1088/1674-4926/34/11/115002.

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5

Kim, Shin-Gon, Habib Rastegar, Min Yoon, Chul-Woo Park, Kyoungyong Park, Sookyoung Joung et Jee-Youl Ryu. « High-Gain and Low-Power Power Amplifier for 24-GHz Automotive Radars ». International Journal of Smart Home 9, n^o 2 (28 février 2015) : 27–34. http://dx.doi.org/10.14257/ijsh.2015.9.2.03.

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6

Qiurong He et Milton Feng. « Low-power, high-gain, and high-linearity SiGe BiCMOS wide-band low-noise amplifier ». IEEE Journal of Solid-State Circuits 39, n^o 6 (juin 2004) : 956–59. http://dx.doi.org/10.1109/jssc.2004.827801.

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7

Farzamiyan, Amir Hossein, et Ahmad Hakimi. « Low-power CMOS distributed amplifier using new cascade gain cell for high and low gain modes ». Analog Integrated Circuits and Signal Processing 74, n^o 2 (30 novembre 2012) : 453–60. http://dx.doi.org/10.1007/s10470-012-9990-9.

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8

Huang, Shou-Chien, Cheng-Hsiu Tsai et Yue-Ming Hsin. « Low power consumption and high gain ultra-wide-band low noise amplifier ». Microwave and Optical Technology Letters 51, n^o 2 (23 décembre 2008) : 382–84. http://dx.doi.org/10.1002/mop.24047.

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9

Cui, Lin Hai, Rui Xu, Zhan Peng Jiang et Chang Chun Dong. « Design of a Low-Voltage Low-Power CMOS Operational Amplifier ». Applied Mechanics and Materials 380-384 (août 2013) : 3283–86. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3283.

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A low voltage, low power two-stage operational amplifier (op-amp) was proposed in this paper. A folded-cascode structure is used in the input stage of the amplifier to get high gain. Current mirrors are used in the input stage to make the transconduotance constant. A simple push-pull common source amplifier is adopted as the output stage to take the advantages of its high efficiency. The experimental results show that the unity-gain bandwidth is 12.5MHz, the low-frequency open-loop voltage gain is 100dB,the phase margin is 65°, and power dissipation is 98.8μw.

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10

Karimi, Gholamreza, Saeed Gholami et Saeed Roshani. « A linear high-gain and low-power CMOS UWB mixer ». International Journal of Electronics Letters 1, n^o 4 (décembre 2013) : 159–67. http://dx.doi.org/10.1080/21681724.2013.829997.

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11

Toofan, S., A. R. Rahmati, A. Abrishamifar et G. Roientan Lahiji. « A low-power and high-gain fully integrated CMOS LNA ». Microelectronics Journal 38, n^o 12 (décembre 2007) : 1150–55. http://dx.doi.org/10.1016/j.mejo.2007.10.001.

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12

Seo, Jeong-Bae, Jong-Ha Kim, Hyuk Sun et Tae-Yeoul Yun. « A Low-Power and High-Gain Mixer for UWB Systems ». IEEE Microwave and Wireless Components Letters 18, n^o 12 (décembre 2008) : 803–5. http://dx.doi.org/10.1109/lmwc.2008.2007707.

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13

Iji, Ayobami, Xi Zhu et Michael Heimlich. « High gain/power quotient variable-gain wideband low-noise amplifier for capsule endoscopy application ». Microwave and Optical Technology Letters 54, n^o 11 (24 août 2012) : 2563–65. http://dx.doi.org/10.1002/mop.27111.

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14

Cen, Mingcan, et Shuxiang Song. « A High Gain, Low-Power Low-Noise Amplifier for Ultra-Wideband Wireless Systems ». Circuits, Systems, and Signal Processing 33, n^o 10 (7 mai 2014) : 3251–62. http://dx.doi.org/10.1007/s00034-014-9801-x.

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15

Chang, J. F., et Y. S. Lin. « Low-power, high-gain and low-noise CMOS distributed amplifier for UWB systems ». Electronics Letters 45, n^o 12 (2009) : 634. http://dx.doi.org/10.1049/el.2009.0354.

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16

Iji, Ayobami, Xie Zhu et Michael Heimlich. « Low power, high gain, low noise amplifier (LNA) for ultra wide-band applications ». Microwave and Optical Technology Letters 55, n^o 6 (27 mars 2013) : 1399–401. http://dx.doi.org/10.1002/mop.27588.

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17

Cao, Menghua, et Weixun Tang. « The High-Speed Low-Power Dynamic Comparator ». Journal of Physics : Conference Series 2113, n^o 1 (1 novembre 2021) : 012064. http://dx.doi.org/10.1088/1742-6596/2113/1/012064.

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Abstract This paper comments on four works for the optimization of comparator design. Today, with the development of integrated circuits, the requirements for comparators about low power, low delay, few offset voltage, and low noise are highly desirable. Specifically, these works made progress in the conventional comparator, which comprises a preamplifier and a latch. They also solved some problems, such as decreasing power and delay. Some works employ a positive feedback cross-coupled pares to provide a larger gain in the preamplifier, use PMOS switch transistors to accelerate the definition phase, or a double-tail architecture to increase the latch regeneration speed. Other work designs a charge pump to improve speed.

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18

Al-Anbagi, Haidar, Abdulghafor Abdulhameed, Ahmed Jasim, Maryam Jahanbakhshi et Abdulhameed Al Obaid. « Power Efficient LNA for Satellite Communications ». Iraqi Journal for Electrical and Electronic Engineering 19, n^o 2 (10 juillet 2023) : 110–17. http://dx.doi.org/10.37917/ijeee.19.2.13.

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This article presents a power-efficient low noise amplifier (LNA) with high gain and low noise figure (NF) dedicated to satellite communications at a frequency of 435 MHz. LNAs’ gain and NF play a significant role in the designs for satellite ground terminals seeking high amplification and maintaining a high signal-to-noise ratio (SNR). The proposed design utilized the transistor (BFP840ESD) to achieve a low NF of 0.459 dB and a high-power gain of 26.149 dB. The study carries out the LNA design procedure, from biasing the transistor, testing its stability at the operation frequency, and finally terminating the appropriate matching networks. In addition to the achieved high gain and low NF, the proposed LNA consumes as low power as only 2 mW.

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19

Salah Toubet, Moustapha, Mohamad Hajj, Regis Chantalat, Eric Arnaud, Bernard Jecko, Thierry Monediere, Hongjiang Zhang et Jean-Christophe Diot. « Wide Bandwidth, High-Gain, and Low-Profile EBG Prototype for High Power Applications ». IEEE Antennas and Wireless Propagation Letters 10 (2011) : 1362–65. http://dx.doi.org/10.1109/lawp.2011.2177953.

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20

Singh, Priya, Vandana Niranjan et Ashwni Kumar. « Design and Simulation of Low Power Differential Transimpedance Amplifier Using Degenerations Capacitors ». Journal of Nanoelectronics and Optoelectronics 17, n^o 10 (1 octobre 2022) : 1370–78. http://dx.doi.org/10.1166/jno.2022.3306.

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In today’s internet-connected culture, high-speed data transmission techniques are in high demand. Optical communication is most used techniques for data transmission with speed. High-speed amplifiers are needed, nevertheless, to obtain high gains and transform current signals into voltage gains. This is accomplished via transimpedance amplifiers, a crucial component of optical receivers. In this work, a high-speed transimpedance amplifier with negative degeneration capacitors and complete differential operation is built. The proposed design has a transimpedance gain of approximately 52.4 dB at 19.8 GHz and an average input-referred noise current of roughly 23.3 pA/√Hz. The suggested circuit also has an high gain, and low input-referred noise, excellent bandwidth all of which contribute to its low power consumption of roughly 215 uW. This makes it appropriate for Internet of Things (IoT) devices, smart devices, mobile phones, laptops, and other computer peripherals.

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21

Jin, Ho Jeong, on Sik Cho et Young-Jin Kim. « Zigbee Transmitter using a Low-power High-gain Up-conversion Mixer ». JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 17, n^o 5 (31 octobre 2017) : 660–65. http://dx.doi.org/10.5573/jsts.2017.17.5.660.

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22

Baik, Seyoung, Changwon Seo, Ho Jeong Jin et Choon Sik Cho. « Zigbee Transmitter Using a Low-Power High-Gain Up-Conversion Mixer ». Journal of Korean Institute of Electromagnetic Engineering and Science 27, n^o 9 (30 septembre 2016) : 825–33. http://dx.doi.org/10.5515/kjkiees.2016.27.9.825.

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23

Sporea, Radu A., Michael J. Trainor, Nigel D. Young, John M. Shannon et S. Ravi P. Silva. « Field Plate Optimization in Low-Power High-Gain Source-Gated Transistors ». IEEE Transactions on Electron Devices 59, n^o 8 (août 2012) : 2180–86. http://dx.doi.org/10.1109/ted.2012.2198823.

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24

Kasthuri Bha, J. K., et P. Aruna Priya. « Low power & ; high gain differential amplifier using 16 nm FinFET ». Microprocessors and Microsystems 71 (novembre 2019) : 102873. http://dx.doi.org/10.1016/j.micpro.2019.102873.

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25

Zhang, Wanyang, David J. Comer et Shiuh-hua Wood Chiang. « Design of low-power ultra-high voltage gain differential cascode stages ». International Journal of Electronics 104, n^o 6 (21 janvier 2017) : 982–92. http://dx.doi.org/10.1080/00207217.2017.1279229.

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26

Li, Cai, Fu Zhongqian et Huang Lu. « A low power high gain UWB LNA in 0.18-μm CMOS ». Journal of Semiconductors 30, n^o 11 (novembre 2009) : 115004. http://dx.doi.org/10.1088/1674-4926/30/11/115004.

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27

Machiels, Brecht, Patrick Reynaert et Michiel S. J. Steyaert. « The tapered matrix amplifier : a low-power high-gain broadband amplifier ». Analog Integrated Circuits and Signal Processing 73, n^o 3 (25 février 2012) : 961–72. http://dx.doi.org/10.1007/s10470-012-9838-3.

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28

Ghaemnia, Afifeh, et Omid Hashemipour. « An ultra-low power high gain CMOS OTA for biomedical applications ». Analog Integrated Circuits and Signal Processing 99, n^o 3 (12 mars 2019) : 529–37. http://dx.doi.org/10.1007/s10470-019-01438-6.

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29

Jin, Ho Jeong, Yeong Seok Choi, Choon Sik Cho et Young-Jin Kim. « Zigbee transmitter using a low-power high-gain up-conversion mixer ». Microwave and Optical Technology Letters 60, n^o 1 (1 décembre 2017) : 277–80. http://dx.doi.org/10.1002/mop.30946.

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30

Bai, Na, Xiaolong Li et Yaohua Xu. « A Low-Voltage, Ultra-Low-Power, High-Gain Operational Amplifier Design for Portable Wearable Devices ». Electronics 11, n^o 1 (27 décembre 2021) : 74. http://dx.doi.org/10.3390/electronics11010074.

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Based on the SMIC 0.13 um CMOS technology, this paper uses a 0.8 V supply voltage to design a low-voltage, ultra-low-power, high-gain, two-stage, fully differential operational amplifier. Through the simulation analysis, when the supply voltage is 0.8 V, the design circuit meets the ultra-low power consumption and also has the characteristic of high gain. The five-tube, fully differential, and common-source amplifier circuits provide the operational amplifier with high gain and large swing. Unlike the traditional common-mode feedback, this paper uses the output of the common-mode feedback as the bias voltage of the five-tube operational transconductance amplifier load, which reduces the design cost of the circuit; the structure involves self-cascoding composite MOS, which makes the common-mode feedback loop more sensitive. The frequency compensation circuit adopts Miller compensation technology with zero-pole separation, which increases the stability of the circuit. The input of the circuit uses the current mirror. A small reference current is chosen to reduce power consumption. A detailed performance simulation analysis of this operational amplifier circuit is carried out on the Cadence spectre platform. The open-loop gain of this operational amplifier is 74.1 dB, the phase margin is 61°, the output swing is 0.7 V, the common-mode rejection ratio is 109 dB, and the static power consumption is only 11.2 uW.

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31

P, Bhavana. « Maximum Power Extraction in Low Power PV FED High Voltage Gain Boost Converter using Optimization Algorithm (PO & ; INC) by Limiting the Oscillations ». Revista Gestão Inovação e Tecnologias 11, n^o 4 (10 juillet 2021) : 1163–76. http://dx.doi.org/10.47059/revistageintec.v11i4.2176.

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32

VASUDEVA, G., et B. V. UMA. « Low Voltage Low Power And High Speed OPAMP Design using High-K FinFET Device ». WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS 20 (28 juin 2021) : 80–87. http://dx.doi.org/10.37394/23201.2021.20.11.

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In this paper, operational amplifier circuit is designed using model parameters of high-k FinFET in 22nm technology. The conventional design expressions for MOSFET based OPAMP design are fine tuned to design FinFET based OPAMP. The OPAMP design is suitable for use as sub circuit in ADC design as it supports low voltage, high speed and low power dissipation. The transistor geometries are identified so as to achieve high performance and energy efficient OPAMP. Schematic capture is carried out using Cadence tool. From the simulation studies, the designed OPAMP has a unity gain bandwidth of 100 GHz and slew rate is equal to 1V/μS. The maximum power dissipation of differential amplifier circuit is 800nW and hence suitable for all low power analog and digital circuits.

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33

Sahu, Rashmi, Maitraiyee Konar et Sudip Kundu. « Improvement of Gain Accuracy and CMRR of Low Power Instrumentation Amplifier Using High Gain Operational Amplifiers ». Micro and Nanosystems 12, n^o 3 (1 décembre 2020) : 168–74. http://dx.doi.org/10.2174/1876402912666200123153318.

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Background: Sensing of biomedical signals is crucial for monitoring of various health conditions. These signals have a very low amplitude (in μV) and a small frequency range (<500 Hz). In the presence of various common-mode interferences, biomedical signals are difficult to detect. Instrumentation amplifiers (INAs) are usually preferred to detect these signals due to their high commonmode rejection ratio (CMRR). Gain accuracy and CMRR are two important parameters associated with any INA. This article, therefore, focuses on the improvement of the gain accuracy and CMRR of a low power INA topology. Objective: The objective of this article is to achieve high gain accuracy and CMRR of low power INA by having high gain operational amplifiers (Op-Amps), which are the building blocks of the INAs. Methods: For the implementation of the Op-Amps and the INAs, the Cadence Virtuoso tool was used. All the designs and implementation were realized in 0.18 μm CMOS technology. Results: Three different Op-Amp topologies namely single-stage differential Op-Amp, folded cascode Op-Amp, and multi-stage Op-Amp were implemented. Using these Op-Amp topologies separately, three Op-Amp-based INAs were realized and compared. The INA designed using the high gain multistage Op-Amp topology of low-frequency gain of 123.89 dB achieves a CMRR of 164.1 dB, with the INA’s gain accuracy as good as 99%, which is the best when compared to the other two INAs realized using the other two Op-Amp topologies implemented. Conclusion: Using very high gain Op-Amps as the building blocks of the INA improves the gain accuracy of the INA and enhances the CMRR of the INA. The three Op-Amp-based INA designed with the multi-stage Op-Amps shows state-of-the-art characteristics as its gain accuracy is 99% and CMRR is as high as 164.1 dB. The power consumed by this INA is 29.25 μW by operating on a power supply of ±0.9V. This makes this INA highly suitable for low power measurement applications.

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34

Huang, Chun-Chieh, Hsin-Chih Kuo, Tzuen-Hsi Huang et Huey-Ru Chuang. « Low-Power, High-Gain V-Band CMOS Low Noise Amplifier for Microwave Radiometer Applications ». IEEE Microwave and Wireless Components Letters 21, n^o 2 (février 2011) : 104–6. http://dx.doi.org/10.1109/lmwc.2010.2091401.

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35

Mousavi, S., et M. Guay. « Noise Sensitivity Reduction in Low-power Multi High Gain Observers Using Low-pass Filters ». IFAC-PapersOnLine 56, n^o 1 (2023) : 79–84. http://dx.doi.org/10.1016/j.ifacol.2023.02.014.

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36

Shahraki, Hamed, Ahmad Hakimi, Kambiz Afrooz et Mohammad Mahdi Pezhman. « High gain dual-band distributed amplifier using new composite right/left-handed transmission line ». International Journal of Microwave and Wireless Technologies 10, n^o 10 (4 octobre 2018) : 1118–27. http://dx.doi.org/10.1017/s1759078718001265.

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AbstractIn this paper, a high-gain dual-band distributed amplifier (DBDA) based on the metamaterial transmission line (TL) is proposed. To have two separate frequency bands in the distributed amplifiers, the composite right/left-handed (CRLH) TLs are used instead of conventional TLs. Although both forward and reverse gains of the distributed amplifiers are available in this case, they suffer from their low gains. In this paper, to increase the DBDA power gain, a new circuit architecture for the CRLH TL is introduced. By using the proposed CRLH TL, a lower wave attenuation coefficient at the forward band of the DBDA is achieved than the conventional structures, which causes a higher forward power gain. Simulation results also show that the power gain of the proposed DBDA is about 28.5 dB at the desired frequency bands, and good agreement between the measurement and simulation results confirms the accuracy of the design method.

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37

Bakkali, Moustapha El, Said Elkhaldi, Intissar Hamzi, Abdelhafid Marroun et Naima Amar Touhami. « UWB-MMIC Matrix Distributed Low Noise Amplifier ». Proceedings 63, n^o 1 (25 décembre 2020) : 52. http://dx.doi.org/10.3390/proceedings2020063052.

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In this paper, a 3.1–11 GHz ultra-wideband low noise amplifier with low noise figure, high power gain S21, low reverse gain S12, and high linearity using the OMMIC ED02AH process, which employs a 0.18 μm Pseudomorphic High Electron Mobility Transistor is presented. This Low Noise Amplifier (LNA) was designed with the Advanced Design System simulator in distributed matrix architecture. For the low noise amplifier, four stages were used obtaining a good input/output matching. An average power gain S21 of 11.6 dB with a gain ripple of ±0.6 dB and excellent noise figure of 3.55 to 4.25 dB is obtained in required band with a power dissipation of 48 mW under a supply voltage of 2 V. The input compression point 1 dB and third-order input intercept point are −1.5 and 23 dBm respectively. The core layout size is 1.8 × 1.2 mm2.

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38

Lee, Hyung Seok, Martin Domeij, Carl Mikael Zetterling et Mikael Östling. « 4H-SiC Power BJTs with High Current Gain and Low On-Resistance ». Materials Science Forum 556-557 (septembre 2007) : 767–70. http://dx.doi.org/10.4028/www.scientific.net/msf.556-557.767.

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4H-SiC BJTs have been fabricated with varying geometrical designs. The maximum value of the current gain was about 30 at IC=85 mA, VCE=14 V and room temperature (RT) for a 20 μm emitter width structure. A collector-emitter voltage drop VCE of 2 V at a forward collector current 55 mA (JC = 128 A/cm2) was obtained and a specific on-resistance of 15.4 m2·cm2 was extracted at RT. Optimum emitter finger widths and base-contact implant distances were derived from measurement. The temperature dependent DC I-V characteristics of the BJTs have been studied resulting in 45 % reduction of the gain and 75 % increase of the on-resistance at 225 oC compared to RT. Forward-bias stress on SiC BJTs was investigated and about 20 % reduction of the initial current gain was found after 27.5 hours. Resistive switching measurements with packaged SiC BJTs were performed showing a resistive fast turn-on with a VCE fall-time of 90 ns. The results indicate that significantly faster switching can be obtained by actively controlling the base current.

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39

Kim, Youngil, et Sangsun Lee. « Low power high-gain class-AB OTA with dynamic output current scaling ». IEICE Electronics Express 10, n^o 3 (2013) : 20130042. http://dx.doi.org/10.1587/elex.10.20130042.

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40

Yaseen, Md, et Dr P. Usha. « Transformerless high gain boost converter for low power applications with feedback control ». TELKOMNIKA Indonesian Journal of Electrical Engineering 16, n^o 2 (1 novembre 2015) : 244. http://dx.doi.org/10.11591/tijee.v16i2.1609.

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A transformer-less boost converter which provides high voltage gain without utilizing transformer or coupled inductors and extreme duty cycle is proposed in this paper. Also it is able to cancel the ripples in the input current at a preselected duty cycle, without increasing the number of components. The converter combines the features of boost converter and a three switch high voltage converter. At the input side, two inductors are interleaved for cancelling the input current ripple and at the output side switched capacitor voltage multiplier is used to increase the voltage gain. Feedback control is used to make the output voltage constant in spite of variation in the input or load or both i.e. both line and load regulation is accompanied. This proposed converter configuration helps eliminate the input current ripple and provides voltage deregulation for low power applications.

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41

Heo, Minuk, Daehyeon Kwon et Minjae Lee. « Low‐power programmable high‐gain time difference amplifier with regeneration time control ». Electronics Letters 50, n^o 16 (juillet 2014) : 1129–31. http://dx.doi.org/10.1049/el.2014.1782.

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42

Kumar, B. P., G. R. Branner, D. Xu et A. Ching. « Optimized compact active downconverters having low power consumption and high conversion gain ». IEEE Microwave and Wireless Components Letters 12, n^o 7 (juillet 2002) : 270–72. http://dx.doi.org/10.1109/lmwc.2002.800850.

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43

Li, Yichen. « The Performance analysis of Low-Power High-Speed comparators ». Highlights in Science, Engineering and Technology 27 (27 décembre 2022) : 72–82. http://dx.doi.org/10.54097/hset.v27i.3723.

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Comparators are the essential block for planning high-speed analog and. This paper presents three inventive designs of the comparators in recent years. First, innovated by classic two-stage comparator, the comparator with a transconductance-enhanced latching stage is suitable for low-power, high-speed operation. Second, triple-latch feed-forward(TLFF) fully dynamic comparator guarantees the maximum possible gain and speed for a specific power across the entire input range. Finally, the comparator with a dynamic floating inverter maximizes efficiency by reusing the current.

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44

Bouzerara, Lyes, Tahar Belaroussi et Boualem Amirouche. « Low-voltage, low-power and high gain cmosota using active positive feedback with feed forward and FDCM techniques ». Facta universitatis - series : Electronics and Energetics 15, n^o 1 (2002) : 93–101. http://dx.doi.org/10.2298/fuee0201093b.

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A low voltage, high dc gain and wideband load compensated cas code operational transconductance amplifier (OTA), using an active positive feedback with feed forward technique and frequency-dependent current mirrors (FDCM), is presented and analyzed. Such techniques stand as a powerful method of gain bandwidth and phase margin enhancements. In this paper, a frequency-dependent current mirror, whose input impedance increases with frequency, is used to form the feed forward path at the input of the current mirror with a feed forward capacitor. By using these techniques, the gain bandwidth product of the amplifier is improved from 115 MHz to 194 MHz, the phase margin is also improved from 85? to 95? and the gain is enhanced from 11 dB to 93 dB. This amplifier operates at 2.5 V power supply voltage drives a capacitive load of 1pF and gives a power dissipation of 7 mW. The predicted performance is verified by simulations using HSPICE tool with 0.8 fim CMOS AMS parameters.

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Huang, Zhe Yang, Che Cheng Huang, Jung Mao Lin et Chung Chih Hung. « High Gain and Low Noise Single Balanced Wireless Receiver Front-End Circuit Design ». Applied Mechanics and Materials 284-287 (janvier 2013) : 2647–51. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.2647.

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This paper presents a wideband wireless receiver front-end for 3.1-5.0GHz band group-1 (BG-1) WiMedia application. The front-end circuits are designed in 0.18um standard CMOS process. The experimental results show the maximum conversion power gain is 45.5dB; minimum noise figure is 2.9dB. Input return loss is lower than -9.3dB and output return loss is lower than -6.8dB. The maximum LO conversion power is 0dBm. 3dB working frequency is 1.9GHz (3.1GHz-5.0GHz) Total power consumption is 24.3mW including LNA, mixer and all buffers. Total chip area is 1.27mm2 including dummy and pads.

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Chen, Jun-Da, et Song-Hao Wang. « A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology ». Journal of Circuits, Systems and Computers 26, n^o 09 (24 avril 2017) : 1750134. http://dx.doi.org/10.1142/s0218126617501341.

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The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

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Zhao, Lv, et Chunhua Wang. « A Low Power High Gain CMOS LNA with Multiple-Feedback Network for Low Voltage UWB Receiver ». Journal of Circuits, Systems and Computers 25, n^o 06 (31 mars 2016) : 1650051. http://dx.doi.org/10.1142/s0218126616500511.

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In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18[Formula: see text][Formula: see text]m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4–10.1[Formula: see text]GHz UWB LNA accomplishes a maximum gain of 14.26[Formula: see text]dB with only 2.33[Formula: see text]mW power consumption at 0.8[Formula: see text]V supply voltage, while Noise Figure (NF) is 1.49–3.41[Formula: see text]dB and the chip area is 0.46[Formula: see text]mm2 including test pads (core area is 0.23[Formula: see text]mm2).

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Chen, Yung Chin, Kun Long Zheng, Zong Ye Wu, Tin Fang Zheng et Chie Nan Lai. « High Pumping Gain Dickson Charge Pump Using Bootstrapped Technique ». Applied Mechanics and Materials 145 (décembre 2011) : 557–61. http://dx.doi.org/10.4028/www.scientific.net/amm.145.557.

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This paper proposed a bootstrapped type high-efficient charge pump circuit based on the Dickson charge pump for high output power and pump-efficiency. By using bootstrapped technique, it can increase both of pump-efficiency and power-efficiency. The proposed bootstrapped based charge pump can avoid the threshold voltage drop and enable to generate a higher output voltage. Simulation by using HSPICE level 3 model shows that for conventional Dickson charge pump, it convert the input low DC-voltage (Vin=1.5V) up to 3.8 times of it (VOUT=5.77V), the pump efficiency was 76.93%. Our work, however, can convert the low input DC-voltage (Vin=1.5V) up near to 4.4 times of it (VOUT=6.62V), pump efficiency can reach up to 88.26%.

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Sayed, Alhassan, Hesham Hamed et El-Sayed Hasaneen. « Low power, Low Voltage and High Gain UWB Low-Noise Amplifier in the 0.13 μm CMOS technology ». International Conference on Electrical Engineering 7, n^o 7 (1 mai 2010) : 1–11. http://dx.doi.org/10.21608/iceeng.2010.33283.

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Ramiah, Harikrishnan, U. Eswaran et J. Kanesan. « A high gain and high linearity class-AB power amplifier for WCDMA applications ». Microelectronics International 31, n^o 1 (20 décembre 2013) : 1–7. http://dx.doi.org/10.1108/mi-09-2012-0069.

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Purpose – The purpose of this paper is to design and realize a high gain power amplifier (PA) with low output back-off power using the InGaP/GaAs HBT process for WCDMA applications from 1.85 to 1.91 GHz. Design/methodology/approach – A three stages cascaded PA is designed which observes a high power gain. A 100 mA of quiescent current helps the PA to operate efficiently. The final stage device dimension has been selected diligently in order to deliver a high output power. The inter-stage match between the driver and main stage has been designed to provide maximum power transfer. The output matching network is constructed to deliver a high linear output power which meets the WCDMA adjacent channel leakage ratio (ACLR) requirement of −33 dBc close to the 1 dB gain compression point. Findings – With the cascaded topology, a maximum 31.3 dB of gain is achieved at 1.9 GHz. S11 of less than −18 dB is achieved across the operating frequency band. The maximum output power is indicated to be 32.7 dBm. An ACLR of −33 dBc is achieved at maximum linear output power of 31 dBm. Practical implications – The designed PA is an excellent candidate to be employed in the WCDMA transmitter chain without the aid of additional driver amplifier and linearization circuits. Originality/value – In this work, a fully integrated GaAs HBT PA has been implemented which is capable to operate linearly close to its 1 dB gain compression point.

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