Littérature scientifique sur le sujet « Hardware Model Checking, Formal Verification, SAT, Satisfiability »
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Articles de revues sur le sujet "Hardware Model Checking, Formal Verification, SAT, Satisfiability"
Yamane, Satoshi, Junpei Kobashi et Kosuke Uemura. « Verification Method of Safety Properties of Embedded Assembly Program by Combining SMT-Based Bounded Model Checking and Reduction of Interrupt Handler Executions ». Electronics 9, no 7 (27 juin 2020) : 1060. http://dx.doi.org/10.3390/electronics9071060.
Texte intégralKoch, Alexander, Michael Schrempp et Michael Kirsten. « Card-Based Cryptography Meets Formal Verification ». New Generation Computing 39, no 1 (avril 2021) : 115–58. http://dx.doi.org/10.1007/s00354-020-00120-0.
Texte intégralGeng, Mengtao, Xiaoyu Zhang et Jianwen Li. « Finding More Property Violations in Model Checking via the Restart Policy ». Electronics 10, no 23 (27 novembre 2021) : 2957. http://dx.doi.org/10.3390/electronics10232957.
Texte intégralPorncharoenwase, Sorawee, Luke Nelson, Xi Wang et Emina Torlak. « A formal foundation for symbolic evaluation with merging ». Proceedings of the ACM on Programming Languages 6, POPL (16 janvier 2022) : 1–28. http://dx.doi.org/10.1145/3498709.
Texte intégralPeres, Augusto, Jaime Ramos et Francisco DionÍsio. « Bounded model checking distributed temporal logic ». Journal of Logic and Computation, 27 juin 2022. http://dx.doi.org/10.1093/logcom/exac042.
Texte intégralThèses sur le sujet "Hardware Model Checking, Formal Verification, SAT, Satisfiability"
Arora, Rajat. « Enhancing SAT-based Formal Verification Methods using Global Learning ». Thesis, Virginia Tech, 2004. http://hdl.handle.net/10919/32987.
Texte intégralMaster of Science
Baud-Berthier, Guillaume. « Encodage Efficace des Systèmes Critiques pour la Vérificaton Formelle par Model Checking à base de Solveurs SAT ». Thesis, Bordeaux, 2018. http://www.theses.fr/2018BORD0147/document.
Texte intégralThe design of electronic circuits and safety-critical software systems in railway or avionic domains for instance, is usually associated with a formal verification process. More precisely, test methods for which it is hard to show completeness are combined with approaches that are complete by definition. Model Checking is one of those approaches and is probably the most prevalent in industry. Reasons of its success are mainly due to two characteristics, namely: (i) its fully automatic aspect, and (ii) its ability to produce a short execution trace of undesired behaviors, which is very helpful for designers to fix the issues. However, the increasing complexity of systems to be verified is a real challenge for the scalability of existing techniques. To tackle this challenge, different model checking algorithms (e.g., symbolic model checking, interpolation), various complementary methods (e.g., abstraction, automatic generation of invariants) and multiple decision procedures (e.g., decision diagram, SMT solver) can be considered. In this thesis, we particularly focus on temporal induction. It is a model checking algorithm widely used in the industry to check safety-critical systems. This is also the core algorithm of the tool developed within SafeRiver, company in which this thesis was carried out. More precisely, temporal induction consists of a combination of BMC (Bounded Model Checking) and k-induction. BMC is a very efficient bugfinding method. While k-induction adds a termination criterion to BMC when the system does not admit bugs. These two techniques generate formulas for which it is necessary to determine their satisfiability. To this end, we use a SAT solver as a decision procedure to determine whether a propositional formula has a solution. The main contribution of this thesis aims to strengthen the collaboration between the SAT solver and the model checker. The improvements proposed mainly focus on increasing the interconnections of these two modules by exploiting the high-level structure of the problem.We have therefore defined several methods taking advantage of the symmetrical structure of the formulas. This structure emerges during the successive unfolding of the transition relation, and allows us to duplicate clauses or even unroll the transitions in different directions (i.e., forward or backward). We also established a communication between the solver and the model checker, which has for purpose to: (i) simplify the model checker representation using the information inferred by the solver, and (ii) assist the solver during resolution with simplifications performed on the high-level representation. Another important contribution of this thesis is the empirical evaluation of the proposed algorithms on well-established benchmarks. This is achieved concretely via the implementation of a model checker taking AIG (And-Inverter Graph) as input, from which we were able to evaluate the effectiveness of our algorithms
Chapitres de livres sur le sujet "Hardware Model Checking, Formal Verification, SAT, Satisfiability"
Yu, Emily, Armin Biere et Keijo Heljanko. « Progress in Certifying Hardware Model Checking Results ». Dans Computer Aided Verification, 363–86. Cham : Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81688-9_17.
Texte intégralBiere, Armin. « Chapter 18. Bounded Model Checking ». Dans Frontiers in Artificial Intelligence and Applications. IOS Press, 2021. http://dx.doi.org/10.3233/faia201002.
Texte intégral